1*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7710_H_ 2*4882a593Smuzhiyun #define _ASM_CPU_SH7710_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 4 5*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000000D 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* MMU and Cache control */ 8*4882a593Smuzhiyun #define MMUCR 0xFFFFFFE0 9*4882a593Smuzhiyun #define CCR 0xFFFFFFEC 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* PFC */ 12*4882a593Smuzhiyun #define PACR 0xA4050100 13*4882a593Smuzhiyun #define PBCR 0xA4050102 14*4882a593Smuzhiyun #define PCCR 0xA4050104 15*4882a593Smuzhiyun #define PETCR 0xA4050106 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Port Data Registers */ 18*4882a593Smuzhiyun #define PADR 0xA4050120 19*4882a593Smuzhiyun #define PBDR 0xA4050122 20*4882a593Smuzhiyun #define PCDR 0xA4050124 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* BSC */ 23*4882a593Smuzhiyun #define CMNCR 0xA4FD0000 24*4882a593Smuzhiyun #define CS0BCR 0xA4FD0004 25*4882a593Smuzhiyun #define CS2BCR 0xA4FD0008 26*4882a593Smuzhiyun #define CS3BCR 0xA4FD000C 27*4882a593Smuzhiyun #define CS4BCR 0xA4FD0010 28*4882a593Smuzhiyun #define CS5ABCR 0xA4FD0014 29*4882a593Smuzhiyun #define CS5BBCR 0xA4FD0018 30*4882a593Smuzhiyun #define CS6ABCR 0xA4FD001C 31*4882a593Smuzhiyun #define CS6BBCR 0xA4FD0020 32*4882a593Smuzhiyun #define CS0WCR 0xA4FD0024 33*4882a593Smuzhiyun #define CS2WCR 0xA4FD0028 34*4882a593Smuzhiyun #define CS3WCR 0xA4FD002C 35*4882a593Smuzhiyun #define CS4WCR 0xA4FD0030 36*4882a593Smuzhiyun #define CS5AWCR 0xA4FD0034 37*4882a593Smuzhiyun #define CS5BWCR 0xA4FD0038 38*4882a593Smuzhiyun #define CS6AWCR 0xA4FD003C 39*4882a593Smuzhiyun #define CS6BWCR 0xA4FD0040 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* SDRAM controller */ 42*4882a593Smuzhiyun #define SDCR 0xA4FD0044 43*4882a593Smuzhiyun #define RTCSR 0xA4FD0048 44*4882a593Smuzhiyun #define RTCNT 0xA4FD004C 45*4882a593Smuzhiyun #define RTCOR 0xA4FD0050 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* SCIF */ 48*4882a593Smuzhiyun #define SCSMR_0 0xA4400000 49*4882a593Smuzhiyun #define SCIF0_BASE SCSMR_0 50*4882a593Smuzhiyun #define SCSMR_0 0xA4410000 51*4882a593Smuzhiyun #define SCIF1_BASE SCSMR_1 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Timer */ 54*4882a593Smuzhiyun #define TMU_BASE 0xA412FE90 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* On chip oscillator circuits */ 57*4882a593Smuzhiyun #define FRQCR 0xA415FF80 58*4882a593Smuzhiyun #define WTCNT 0xA415FF84 59*4882a593Smuzhiyun #define WTCSR 0xA415FF86 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7710_H_ */ 62