1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008, 2011 Renesas Solutions Corp. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SH7734 Internal I/O register 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7734_H_ 10*4882a593Smuzhiyun #define _ASM_CPU_SH7734_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CCR 0xFF00001C 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 4 15*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000090d 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* SCIF */ 18*4882a593Smuzhiyun #define SCIF0_BASE 0xFFE40000 19*4882a593Smuzhiyun #define SCIF1_BASE 0xFFE41000 20*4882a593Smuzhiyun #define SCIF2_BASE 0xFFE42000 21*4882a593Smuzhiyun #define SCIF3_BASE 0xFFE43000 22*4882a593Smuzhiyun #define SCIF4_BASE 0xFFE44000 23*4882a593Smuzhiyun #define SCIF5_BASE 0xFFE45000 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Timer */ 26*4882a593Smuzhiyun #define TMU_BASE 0xFFD80000 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* PFC */ 29*4882a593Smuzhiyun #define PMMR (0xFFFC0000) 30*4882a593Smuzhiyun #define MODESEL0 (0xFFFC004C) 31*4882a593Smuzhiyun #define MODESEL2 (MODESEL0 + 0x4) 32*4882a593Smuzhiyun #define MODESEL2_INIT (0x00003000) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define IPSR0 (0xFFFC001C) 35*4882a593Smuzhiyun #define IPSR1 (IPSR0 + 0x4) 36*4882a593Smuzhiyun #define IPSR2 (IPSR0 + 0x8) 37*4882a593Smuzhiyun #define IPSR3 (IPSR0 + 0xC) 38*4882a593Smuzhiyun #define IPSR4 (IPSR0 + 0x10) 39*4882a593Smuzhiyun #define IPSR5 (IPSR0 + 0x14) 40*4882a593Smuzhiyun #define IPSR6 (IPSR0 + 0x18) 41*4882a593Smuzhiyun #define IPSR7 (IPSR0 + 0x1C) 42*4882a593Smuzhiyun #define IPSR8 (IPSR0 + 0x20) 43*4882a593Smuzhiyun #define IPSR9 (IPSR0 + 0x24) 44*4882a593Smuzhiyun #define IPSR10 (IPSR0 + 0x28) 45*4882a593Smuzhiyun #define IPSR11 (IPSR0 + 0x2C) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define GPSR0 (0xFFFC0004) 48*4882a593Smuzhiyun #define GPSR1 (GPSR0 + 0x4) 49*4882a593Smuzhiyun #define GPSR2 (GPSR0 + 0x8) 50*4882a593Smuzhiyun #define GPSR3 (GPSR0 + 0xC) 51*4882a593Smuzhiyun #define GPSR4 (GPSR0 + 0x10) 52*4882a593Smuzhiyun #define GPSR5 (GPSR0 + 0x14) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7734_H_ */ 56