1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2008, 2011 Renesas Solutions Corp. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SH7724 Internal I/O register 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7724_H_ 10*4882a593Smuzhiyun #define _ASM_CPU_SH7724_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 4 13*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000090d 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* EXP */ 16*4882a593Smuzhiyun #define TRA 0xFF000020 17*4882a593Smuzhiyun #define EXPEVT 0xFF000024 18*4882a593Smuzhiyun #define INTEVT 0xFF000028 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* MMU */ 21*4882a593Smuzhiyun #define PTEH 0xFF000000 22*4882a593Smuzhiyun #define PTEL 0xFF000004 23*4882a593Smuzhiyun #define TTB 0xFF000008 24*4882a593Smuzhiyun #define TEA 0xFF00000C 25*4882a593Smuzhiyun #define MMUCR 0xFF000010 26*4882a593Smuzhiyun #define PASCR 0xFF000070 27*4882a593Smuzhiyun #define IRMCR 0xFF000078 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* CACHE */ 30*4882a593Smuzhiyun #define CCR 0xFF00001C 31*4882a593Smuzhiyun #define RAMCR 0xFF000074 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* INTC */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* BSC */ 36*4882a593Smuzhiyun #define MMSELR 0xFF800020 37*4882a593Smuzhiyun #define CMNCR 0xFEC10000 38*4882a593Smuzhiyun #define CS0BCR 0xFEC10004 39*4882a593Smuzhiyun #define CS2BCR 0xFEC10008 40*4882a593Smuzhiyun #define CS4BCR 0xFEC10010 41*4882a593Smuzhiyun #define CS5ABCR 0xFEC10014 42*4882a593Smuzhiyun #define CS5BBCR 0xFEC10018 43*4882a593Smuzhiyun #define CS6ABCR 0xFEC1001C 44*4882a593Smuzhiyun #define CS6BBCR 0xFEC10020 45*4882a593Smuzhiyun #define CS0WCR 0xFEC10024 46*4882a593Smuzhiyun #define CS2WCR 0xFEC10028 47*4882a593Smuzhiyun #define CS4WCR 0xFEC10030 48*4882a593Smuzhiyun #define CS5AWCR 0xFEC10034 49*4882a593Smuzhiyun #define CS5BWCR 0xFEC10038 50*4882a593Smuzhiyun #define CS6AWCR 0xFEC1003C 51*4882a593Smuzhiyun #define CS6BWCR 0xFEC10040 52*4882a593Smuzhiyun #define RBWTCNT 0xFEC10054 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* SBSC */ 55*4882a593Smuzhiyun #define SBSC_SDCR 0xFE400008 56*4882a593Smuzhiyun #define SBSC_SDWCR 0xFE40000C 57*4882a593Smuzhiyun #define SBSC_SDPCR 0xFE400010 58*4882a593Smuzhiyun #define SBSC_RTCSR 0xFE400014 59*4882a593Smuzhiyun #define SBSC_RTCNT 0xFE400018 60*4882a593Smuzhiyun #define SBSC_RTCOR 0xFE40001C 61*4882a593Smuzhiyun #define SBSC_RFCR 0xFE400020 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* DSBC */ 64*4882a593Smuzhiyun #define DBKIND 0xFD000008 65*4882a593Smuzhiyun #define DBSTATE 0xFD00000C 66*4882a593Smuzhiyun #define DBEN 0xFD000010 67*4882a593Smuzhiyun #define DBCMDCNT 0xFD000014 68*4882a593Smuzhiyun #define DBCKECNT 0xFD000018 69*4882a593Smuzhiyun #define DBCONF 0xFD000020 70*4882a593Smuzhiyun #define DBTR0 0xFD000030 71*4882a593Smuzhiyun #define DBTR1 0xFD000034 72*4882a593Smuzhiyun #define DBTR2 0xFD000038 73*4882a593Smuzhiyun #define DBTR3 0xFD00003C 74*4882a593Smuzhiyun #define DBRFPDN0 0xFD000040 75*4882a593Smuzhiyun #define DBRFPDN1 0xFD000044 76*4882a593Smuzhiyun #define DBRFPDN2 0xFD000048 77*4882a593Smuzhiyun #define DBRFSTS 0xFD00004C 78*4882a593Smuzhiyun #define DBMRCNT 0xFD000060 79*4882a593Smuzhiyun #define DBPDCNT0 0xFD000108 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* DMAC */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* CPG */ 84*4882a593Smuzhiyun #define FRQCRA 0xA4150000 85*4882a593Smuzhiyun #define FRQCRB 0xA4150004 86*4882a593Smuzhiyun #define FRQCR FRQCRA 87*4882a593Smuzhiyun #define VCLKCR 0xA4150004 88*4882a593Smuzhiyun #define SCLKACR 0xA4150008 89*4882a593Smuzhiyun #define SCLKBCR 0xA415000C 90*4882a593Smuzhiyun #define IRDACLKCR 0xA4150018 91*4882a593Smuzhiyun #define PLLCR 0xA4150024 92*4882a593Smuzhiyun #define DLLFRQ 0xA4150050 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* LOW POWER MODE */ 95*4882a593Smuzhiyun #define STBCR 0xA4150020 96*4882a593Smuzhiyun #define MSTPCR0 0xA4150030 97*4882a593Smuzhiyun #define MSTPCR1 0xA4150034 98*4882a593Smuzhiyun #define MSTPCR2 0xA4150038 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* RWDT */ 101*4882a593Smuzhiyun #define RWTCNT 0xA4520000 102*4882a593Smuzhiyun #define RWTCSR 0xA4520004 103*4882a593Smuzhiyun #define WTCNT RWTCNT 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* TMU */ 106*4882a593Smuzhiyun #define TMU_BASE 0xFFD80000 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* TPU */ 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* CMT */ 111*4882a593Smuzhiyun #define CMSTR 0xA44A0000 112*4882a593Smuzhiyun #define CMCSR 0xA44A0060 113*4882a593Smuzhiyun #define CMCNT 0xA44A0064 114*4882a593Smuzhiyun #define CMCOR 0xA44A0068 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* MSIOF */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* SCIF */ 119*4882a593Smuzhiyun #define SCIF0_BASE 0xFFE00000 120*4882a593Smuzhiyun #define SCIF1_BASE 0xFFE10000 121*4882a593Smuzhiyun #define SCIF2_BASE 0xFFE20000 122*4882a593Smuzhiyun #define SCIF3_BASE 0xa4e30000 123*4882a593Smuzhiyun #define SCIF4_BASE 0xa4e40000 124*4882a593Smuzhiyun #define SCIF5_BASE 0xa4e50000 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* RTC */ 127*4882a593Smuzhiyun /* IrDA */ 128*4882a593Smuzhiyun /* KEYSC */ 129*4882a593Smuzhiyun /* USB */ 130*4882a593Smuzhiyun /* IIC */ 131*4882a593Smuzhiyun /* FLCTL */ 132*4882a593Smuzhiyun /* VPU */ 133*4882a593Smuzhiyun /* VIO(CEU) */ 134*4882a593Smuzhiyun /* VIO(VEU) */ 135*4882a593Smuzhiyun /* VIO(BEU) */ 136*4882a593Smuzhiyun /* 2DG */ 137*4882a593Smuzhiyun /* LCDC */ 138*4882a593Smuzhiyun /* VOU */ 139*4882a593Smuzhiyun /* TSIF */ 140*4882a593Smuzhiyun /* SIU */ 141*4882a593Smuzhiyun /* ATAPI */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* PFC */ 144*4882a593Smuzhiyun #define PACR 0xA4050100 145*4882a593Smuzhiyun #define PBCR 0xA4050102 146*4882a593Smuzhiyun #define PCCR 0xA4050104 147*4882a593Smuzhiyun #define PDCR 0xA4050106 148*4882a593Smuzhiyun #define PECR 0xA4050108 149*4882a593Smuzhiyun #define PFCR 0xA405010A 150*4882a593Smuzhiyun #define PGCR 0xA405010C 151*4882a593Smuzhiyun #define PHCR 0xA405010E 152*4882a593Smuzhiyun #define PJCR 0xA4050110 153*4882a593Smuzhiyun #define PKCR 0xA4050112 154*4882a593Smuzhiyun #define PLCR 0xA4050114 155*4882a593Smuzhiyun #define PMCR 0xA4050116 156*4882a593Smuzhiyun #define PNCR 0xA4050118 157*4882a593Smuzhiyun #define PQCR 0xA405011A 158*4882a593Smuzhiyun #define PRCR 0xA405011C 159*4882a593Smuzhiyun #define PSCR 0xA405011E 160*4882a593Smuzhiyun #define PTCR 0xA4050140 161*4882a593Smuzhiyun #define PUCR 0xA4050142 162*4882a593Smuzhiyun #define PVCR 0xA4050144 163*4882a593Smuzhiyun #define PWCR 0xA4050146 164*4882a593Smuzhiyun #define PXCR 0xA4050148 165*4882a593Smuzhiyun #define PYCR 0xA405014A 166*4882a593Smuzhiyun #define PZCR 0xA405014C 167*4882a593Smuzhiyun #define PSELA 0xA405014E 168*4882a593Smuzhiyun #define PSELB 0xA4050150 169*4882a593Smuzhiyun #define PSELC 0xA4050152 170*4882a593Smuzhiyun #define PSELD 0xA4050154 171*4882a593Smuzhiyun #define PSELE 0xA4050156 172*4882a593Smuzhiyun #define HIZCRA 0xA4050158 173*4882a593Smuzhiyun #define HIZCRB 0xA405015A 174*4882a593Smuzhiyun #define HIZCRC 0xA405015C 175*4882a593Smuzhiyun #define HIZCRD 0xA405015E 176*4882a593Smuzhiyun #define MSELCRA 0xA4050180 177*4882a593Smuzhiyun #define MSELCRB 0xA4050182 178*4882a593Smuzhiyun #define PULCR 0xA4050184 179*4882a593Smuzhiyun #define DRVCRA 0xA405018A 180*4882a593Smuzhiyun #define DRVCRB 0xA405018C 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* I/O Port */ 183*4882a593Smuzhiyun #define PADR 0xA4050120 184*4882a593Smuzhiyun #define PBDR 0xA4050122 185*4882a593Smuzhiyun #define PCDR 0xA4050124 186*4882a593Smuzhiyun #define PDDR 0xA4050126 187*4882a593Smuzhiyun #define PEDR 0xA4050128 188*4882a593Smuzhiyun #define PFDR 0xA405012A 189*4882a593Smuzhiyun #define PGDR 0xA405012C 190*4882a593Smuzhiyun #define PHDR 0xA405012E 191*4882a593Smuzhiyun #define PJDR 0xA4050130 192*4882a593Smuzhiyun #define PKDR 0xA4050132 193*4882a593Smuzhiyun #define PLDR 0xA4050134 194*4882a593Smuzhiyun #define PMDR 0xA4050136 195*4882a593Smuzhiyun #define PNDR 0xA4050138 196*4882a593Smuzhiyun #define PQDR 0xA405013A 197*4882a593Smuzhiyun #define PRDR 0xA405013C 198*4882a593Smuzhiyun #define PSDR 0xA405013E 199*4882a593Smuzhiyun #define PTDR 0xA4050160 200*4882a593Smuzhiyun #define PUDR 0xA4050162 201*4882a593Smuzhiyun #define PVDR 0xA4050164 202*4882a593Smuzhiyun #define PWDR 0xA4050166 203*4882a593Smuzhiyun #define PXDR 0xA4050168 204*4882a593Smuzhiyun #define PYDR 0xA405016A 205*4882a593Smuzhiyun #define PZDR 0xA405016C 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* Ether */ 208*4882a593Smuzhiyun #define EDMR 0xA4600000 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* UBC */ 211*4882a593Smuzhiyun /* H-UDI */ 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7724_H_ */ 214