1*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7706_H_ 2*4882a593Smuzhiyun #define _ASM_CPU_SH7706_H_ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 4 5*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000000D 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* MMU and Cache control */ 8*4882a593Smuzhiyun #define MMUCR 0xFFFFFFE0 9*4882a593Smuzhiyun #define CCR 0xFFFFFFEC 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* PFC */ 12*4882a593Smuzhiyun #define PACR 0xA4050100 13*4882a593Smuzhiyun #define PBCR 0xA4050102 14*4882a593Smuzhiyun #define PCCR 0xA4050104 15*4882a593Smuzhiyun #define PETCR 0xA4050106 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Port Data Registers */ 18*4882a593Smuzhiyun #define PADR 0xA4050120 19*4882a593Smuzhiyun #define PBDR 0xA4050122 20*4882a593Smuzhiyun #define PCDR 0xA4050124 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* BSC */ 23*4882a593Smuzhiyun #define FRQCR 0xffffff80 24*4882a593Smuzhiyun #define BCR1 0xffffff60 25*4882a593Smuzhiyun #define BCR2 0xffffff62 26*4882a593Smuzhiyun #define WCR1 0xffffff64 27*4882a593Smuzhiyun #define WCR2 0xffffff66 28*4882a593Smuzhiyun #define MCR 0xffffff68 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* SDRAM controller */ 31*4882a593Smuzhiyun #define DCR 0xffffff6a 32*4882a593Smuzhiyun #define RTCSR 0xffffff6e 33*4882a593Smuzhiyun #define RTCNT 0xffffff70 34*4882a593Smuzhiyun #define RTCOR 0xffffff72 35*4882a593Smuzhiyun #define RFCR 0xffffff74 36*4882a593Smuzhiyun #define SDMR 0xFFFFD000 37*4882a593Smuzhiyun #define CS3_R 0xFFFFE460 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* SCIF */ 40*4882a593Smuzhiyun #define SCSMR_2 0xA4000150 41*4882a593Smuzhiyun #define SCIF0_BASE SCSMR_2 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Timer */ 44*4882a593Smuzhiyun #define TMU_BASE 0xFFFFFE90 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* On chip oscillator circuits */ 47*4882a593Smuzhiyun #define WTCNT 0xFFFFFF84 48*4882a593Smuzhiyun #define WTCSR 0xFFFFFF86 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7706_H_ */ 51