1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SH7750/SH7750S/SH7750R/SH7751/SH7751R 5*4882a593Smuzhiyun * Internal I/O register 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_CPU_SH7750_H_ 11*4882a593Smuzhiyun #define _ASM_CPU_SH7750_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifdef CONFIG_CPU_TYPE_R 14*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 2 15*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ 16*4882a593Smuzhiyun #else 17*4882a593Smuzhiyun #define CACHE_OC_NUM_WAYS 1 18*4882a593Smuzhiyun #define CCR_CACHE_INIT 0x0000090B 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* OCN */ 22*4882a593Smuzhiyun #define PTEH 0xFF000000 23*4882a593Smuzhiyun #define PTEL 0xFF000004 24*4882a593Smuzhiyun #define TTB 0xFF000008 25*4882a593Smuzhiyun #define TEA 0xFF00000C 26*4882a593Smuzhiyun #define MMUCR 0xFF000010 27*4882a593Smuzhiyun #define BASRA 0xFF000014 28*4882a593Smuzhiyun #define BASRB 0xFF000018 29*4882a593Smuzhiyun #define CCR 0xFF00001C 30*4882a593Smuzhiyun #define TRA 0xFF000020 31*4882a593Smuzhiyun #define EXPEVT 0xFF000024 32*4882a593Smuzhiyun #define INTEVT 0xFF000028 33*4882a593Smuzhiyun #define PTEA 0xFF000034 34*4882a593Smuzhiyun #define QACR0 0xFF000038 35*4882a593Smuzhiyun #define QACR1 0xFF00003C 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* UBC */ 38*4882a593Smuzhiyun #define BARA 0xFF200000 39*4882a593Smuzhiyun #define BAMRA 0xFF200004 40*4882a593Smuzhiyun #define BBRA 0xFF200008 41*4882a593Smuzhiyun #define BARB 0xFF20000C 42*4882a593Smuzhiyun #define BAMRB 0xFF200010 43*4882a593Smuzhiyun #define BBRB 0xFF200014 44*4882a593Smuzhiyun #define BDRB 0xFF200018 45*4882a593Smuzhiyun #define BDMRB 0xFF20001C 46*4882a593Smuzhiyun #define BRCR 0xFF200020 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* BSC */ 49*4882a593Smuzhiyun #define BCR1 0xFF800000 50*4882a593Smuzhiyun #define BCR2 0xFF800004 51*4882a593Smuzhiyun #define BCR3 0xFF800050 52*4882a593Smuzhiyun #define BCR4 0xFE0A00F0 53*4882a593Smuzhiyun #define WCR1 0xFF800008 54*4882a593Smuzhiyun #define WCR2 0xFF80000C 55*4882a593Smuzhiyun #define WCR3 0xFF800010 56*4882a593Smuzhiyun #define MCR 0xFF800014 57*4882a593Smuzhiyun #define PCR 0xFF800018 58*4882a593Smuzhiyun #define RTCSR 0xFF80001C 59*4882a593Smuzhiyun #define RTCNT 0xFF800020 60*4882a593Smuzhiyun #define RTCOR 0xFF800024 61*4882a593Smuzhiyun #define RFCR 0xFF800028 62*4882a593Smuzhiyun #define PCTRA 0xFF80002C 63*4882a593Smuzhiyun #define PDTRA 0xFF800030 64*4882a593Smuzhiyun #define PCTRB 0xFF800040 65*4882a593Smuzhiyun #define PDTRB 0xFF800044 66*4882a593Smuzhiyun #define GPIOIC 0xFF800048 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* DMAC */ 69*4882a593Smuzhiyun #define SAR0 0xFFA00000 70*4882a593Smuzhiyun #define DAR0 0xFFA00004 71*4882a593Smuzhiyun #define DMATCR0 0xFFA00008 72*4882a593Smuzhiyun #define CHCR0 0xFFA0000C 73*4882a593Smuzhiyun #define SAR1 0xFFA00010 74*4882a593Smuzhiyun #define DAR1 0xFFA00014 75*4882a593Smuzhiyun #define DMATCR1 0xFFA00018 76*4882a593Smuzhiyun #define CHCR1 0xFFA0001C 77*4882a593Smuzhiyun #define SAR2 0xFFA00020 78*4882a593Smuzhiyun #define DAR2 0xFFA00024 79*4882a593Smuzhiyun #define DMATCR2 0xFFA00028 80*4882a593Smuzhiyun #define CHCR2 0xFFA0002C 81*4882a593Smuzhiyun #define SAR3 0xFFA00030 82*4882a593Smuzhiyun #define DAR3 0xFFA00034 83*4882a593Smuzhiyun #define DMATCR3 0xFFA00038 84*4882a593Smuzhiyun #define CHCR3 0xFFA0003C 85*4882a593Smuzhiyun #define DMAOR 0xFFA00040 86*4882a593Smuzhiyun #define SAR4 0xFFA00050 87*4882a593Smuzhiyun #define DAR4 0xFFA00054 88*4882a593Smuzhiyun #define DMATCR4 0xFFA00058 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* CPG */ 91*4882a593Smuzhiyun #define FRQCR 0xFFC00000 92*4882a593Smuzhiyun #define STBCR 0xFFC00004 93*4882a593Smuzhiyun #define WTCNT 0xFFC00008 94*4882a593Smuzhiyun #define WTCSR 0xFFC0000C 95*4882a593Smuzhiyun #define STBCR2 0xFFC00010 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* RTC */ 98*4882a593Smuzhiyun #define R64CNT 0xFFC80000 99*4882a593Smuzhiyun #define RSECCNT 0xFFC80004 100*4882a593Smuzhiyun #define RMINCNT 0xFFC80008 101*4882a593Smuzhiyun #define RHRCNT 0xFFC8000C 102*4882a593Smuzhiyun #define RWKCNT 0xFFC80010 103*4882a593Smuzhiyun #define RDAYCNT 0xFFC80014 104*4882a593Smuzhiyun #define RMONCNT 0xFFC80018 105*4882a593Smuzhiyun #define RYRCNT 0xFFC8001C 106*4882a593Smuzhiyun #define RSECAR 0xFFC80020 107*4882a593Smuzhiyun #define RMINAR 0xFFC80024 108*4882a593Smuzhiyun #define RHRAR 0xFFC80028 109*4882a593Smuzhiyun #define RWKAR 0xFFC8002C 110*4882a593Smuzhiyun #define RDAYAR 0xFFC80030 111*4882a593Smuzhiyun #define RMONAR 0xFFC80034 112*4882a593Smuzhiyun #define RCR1 0xFFC80038 113*4882a593Smuzhiyun #define RCR2 0xFFC8003C 114*4882a593Smuzhiyun #define RCR3 0xFFC80050 115*4882a593Smuzhiyun #define RYRAR 0xFFC80054 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* ICR */ 118*4882a593Smuzhiyun #define ICR 0xFFD00000 119*4882a593Smuzhiyun #define IPRA 0xFFD00004 120*4882a593Smuzhiyun #define IPRB 0xFFD00008 121*4882a593Smuzhiyun #define IPRC 0xFFD0000C 122*4882a593Smuzhiyun #define IPRD 0xFFD00010 123*4882a593Smuzhiyun #define INTPRI 0xFE080000 124*4882a593Smuzhiyun #define INTREQ 0xFE080020 125*4882a593Smuzhiyun #define INTMSK 0xFE080040 126*4882a593Smuzhiyun #define INTMSKCL 0xFE080060 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* CPG */ 129*4882a593Smuzhiyun #define CLKSTP 0xFE0A0000 130*4882a593Smuzhiyun #define CLKSTPCLR 0xFE0A0008 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* TMU */ 133*4882a593Smuzhiyun #define TMU_BASE 0xFFD80000 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* SCI */ 136*4882a593Smuzhiyun #define SCSMR1 0xFFE00000 137*4882a593Smuzhiyun #define SCF0_BASE SCSMR1 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* SCIF */ 140*4882a593Smuzhiyun #define SCSMR2 0xFFE80000 141*4882a593Smuzhiyun #define SCIF1_BASE SCSMR2 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* H-UDI */ 144*4882a593Smuzhiyun #define SDIR 0xFFF00000 145*4882a593Smuzhiyun #define SDDR 0xFFF00008 146*4882a593Smuzhiyun #define SDINT 0xFFF00014 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #endif /* _ASM_CPU_SH7750_H_ */ 149