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/OK3568_Linux_fs/kernel/drivers/infiniband/hw/qib/
H A Dqib_7220_regs.h39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1
59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1
61 #define QIB_7220_Control_Reserved_RMASK 0x1
63 #define QIB_7220_Control_TxLatency_RMASK 0x1
65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1
67 #define QIB_7220_Control_LinkEn_RMASK 0x1
68 #define QIB_7220_Control_FreezeMode_LSB 0x1
69 #define QIB_7220_Control_FreezeMode_RMASK 0x1
[all …]
H A Dqib_6120_regs.h37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
53 #define QIB_6120_Control_TxLatency_RMASK 0x1
55 #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1
57 #define QIB_6120_Control_LinkEn_RMASK 0x1
58 #define QIB_6120_Control_FreezeMode_LSB 0x1
59 #define QIB_6120_Control_FreezeMode_RMASK 0x1
61 #define QIB_6120_Control_SyncReset_RMASK 0x1
81 #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1
83 #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1
85 #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1
[all …]
H A Dqib_7322_regs.h39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
66 #define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x1
69 #define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x1
72 #define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x1
75 #define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x1
76 #define QIB_7322_Control_FreezeMode_LSB 0x1
77 #define QIB_7322_Control_FreezeMode_MSB 0x1
78 #define QIB_7322_Control_FreezeMode_RMASK 0x1
81 #define QIB_7322_Control_SyncReset_RMASK 0x1
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
[all …]
H A Dmt6359.h140 #define RG_LDO_VAUD18_EN_MASK 0x1
141 #define RG_LDO_VAUD18_EN_MASK_SFT (0x1 << 0)
145 #define RG_VOW13M_CK_PDN_MASK 0x1
146 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
148 #define RG_VOW32K_CK_PDN_MASK 0x1
149 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
151 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
152 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
154 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
155 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
[all …]
H A Drt5616.h152 #define RT5616_L_MUTE (0x1 << 15)
154 #define RT5616_VOL_L_MUTE (0x1 << 14)
156 #define RT5616_R_MUTE (0x1 << 7)
158 #define RT5616_VOL_R_MUTE (0x1 << 6)
166 #define RT5616_EN_DFO (0x1 << 15)
174 #define RT5616_IN_DF1 (0x1 << 7)
176 #define RT5616_IN_DF2 (0x1 << 6)
182 #define RT5616_INR_SEL_MASK (0x1 << 7)
185 #define RT5616_INR_SEL_MONON (0x1 << 7)
208 #define RT5616_M_MONO_ADC_L (0x1 << 15)
[all …]
H A Drt5651.h176 #define RT5651_L_MUTE (0x1 << 15)
178 #define RT5651_VOL_L_MUTE (0x1 << 14)
180 #define RT5651_R_MUTE (0x1 << 7)
182 #define RT5651_VOL_R_MUTE (0x1 << 6)
190 #define RT5651_EN_DFO (0x1 << 15)
198 #define RT5651_IN_DF1 (0x1 << 7)
200 #define RT5651_IN_DF2 (0x1 << 6)
205 #define RT5651_INL_SEL_MASK (0x1 << 15)
208 #define RT5651_INL_SEL_MONOP (0x1 << 15)
211 #define RT5651_INR_SEL_MASK (0x1 << 7)
[all …]
H A Drt5645.h219 #define RT5645_L_MUTE (0x1 << 15)
221 #define RT5645_VOL_L_MUTE (0x1 << 14)
223 #define RT5645_R_MUTE (0x1 << 7)
225 #define RT5645_VOL_R_MUTE (0x1 << 6)
235 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
238 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
239 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
240 #define RT5645_CBJ_MIC_SW (0x1 << 4)
[all …]
H A Drt5640.h182 #define RT5640_L_MUTE (0x1 << 15)
184 #define RT5640_VOL_L_MUTE (0x1 << 14)
186 #define RT5640_R_MUTE (0x1 << 7)
188 #define RT5640_VOL_R_MUTE (0x1 << 6)
206 #define RT5640_IN_DF1 (0x1 << 7)
208 #define RT5640_IN_DF2 (0x1 << 6)
212 #define RT5640_INL_SEL_MASK (0x1 << 15)
215 #define RT5640_INL_SEL_MONOP (0x1 << 15)
218 #define RT5640_INR_SEL_MASK (0x1 << 7)
221 #define RT5640_INR_SEL_MONON (0x1 << 7)
[all …]
H A Drt5670.h213 #define RT5670_L_MUTE (0x1 << 15)
215 #define RT5670_VOL_L_MUTE (0x1 << 14)
217 #define RT5670_R_MUTE (0x1 << 7)
219 #define RT5670_VOL_R_MUTE (0x1 << 6)
229 #define RT5670_ID_5672 (0x1 << 1)
235 #define RT5670_CBJ_JD_HP_EN (0x1 << 9)
236 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8)
237 #define RT5670_CBJ_BST1_EN (0x1 << 2)
240 #define RT5670_CBJ_MN_JD (0x1 << 12)
241 #define RT5670_CAPLESS_EN (0x1 << 11)
[all …]
H A Drt5665.h431 #define RT5665_L_MUTE (0x1 << 15)
433 #define RT5665_VOL_L_MUTE (0x1 << 14)
435 #define RT5665_R_MUTE (0x1 << 7)
437 #define RT5665_VOL_R_MUTE (0x1 << 6)
455 #define RT5665_IN1_DF_MASK (0x1 << 15)
459 #define RT5665_IN2_DF_MASK (0x1 << 7)
465 #define RT5665_IN3_DF_MASK (0x1 << 15)
469 #define RT5665_IN4_DF_MASK (0x1 << 7)
481 #define RT5665_EMB_JD_EN (0x1 << 15)
483 #define RT5665_JD_MODE (0x1 << 13)
[all …]
H A Drt5631.h83 #define RT5631_L_MUTE (0x1 << 15)
85 #define RT5631_L_EN (0x1 << 14)
87 #define RT5631_R_MUTE (0x1 << 7)
89 #define RT5631_R_EN (0x1 << 6)
96 #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14)
98 #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14)
99 #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6)
101 #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6)
104 #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14)
106 #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 14)
[all …]
H A Drt5659.h539 #define RT5659_L_MUTE (0x1 << 15)
541 #define RT5659_VOL_L_MUTE (0x1 << 14)
543 #define RT5659_R_MUTE (0x1 << 7)
545 #define RT5659_VOL_R_MUTE (0x1 << 6)
559 #define RT5659_IN1_DF_MASK (0x1 << 15)
567 #define RT5659_IN3_DF_MASK (0x1 << 15)
571 #define RT5659_IN4_DF_MASK (0x1 << 7)
583 #define RT5659_EMB_JD_EN (0x1 << 15)
585 #define RT5659_JD_MODE (0x1 << 13)
587 #define RT5659_EXT_JD_EN (0x1 << 11)
[all …]
H A Drt5660.h133 #define RT5660_L_MUTE (0x1 << 15)
135 #define RT5660_VOL_L_MUTE (0x1 << 14)
137 #define RT5660_R_MUTE (0x1 << 7)
139 #define RT5660_VOL_R_MUTE (0x1 << 6)
147 #define RT5660_IN_DF1 (0x1 << 15)
151 #define RT5660_IN_DF2 (0x1 << 7)
157 #define RT5660_IN_DF3 (0x1 << 15)
161 #define RT5660_IN_DF4 (0x1 << 7)
185 #define RT5660_M_ADC_L1 (0x1 << 14)
187 #define RT5660_M_ADC_L2 (0x1 << 13)
[all …]
/OK3568_Linux_fs/kernel/sound/soc/mediatek/mt8183/
H A Dmt8183-reg.h418 #define BCK_INVERSE_MASK 0x1
419 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
423 #define AWB2_ON_MASK 0x1
424 #define AWB2_ON_MASK_SFT (0x1 << 29)
426 #define VUL2_ON_MASK 0x1
427 #define VUL2_ON_MASK_SFT (0x1 << 27)
429 #define MOD_DAI_DUP_WR_MASK 0x1
430 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
435 #define VUL12_R_MONO_MASK 0x1
436 #define VUL12_R_MONO_MASK_SFT (0x1 << 11)
[all …]
/OK3568_Linux_fs/kernel/sound/soc/mediatek/mt6797/
H A Dmt6797-reg.h263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 25)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_enum.h29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
47 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
51 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
55 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
59 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
63 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
67 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
[all …]
H A Ddce_11_0_enum.h29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
47 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
51 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
55 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
59 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
63 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
67 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/samsung/
H A Dexynos3250-pmu.c21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
26 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
27 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
28 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
29 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
30 { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
31 { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
32 { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
33 { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
34 { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
[all …]
H A Dexynos4-pmu.c24 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
25 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } },
26 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } },
27 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
28 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
29 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } },
30 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } },
31 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
32 { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } },
33 { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } },
[all …]
H A Dexynos5250-pmu.c21 { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
22 { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
23 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
29 { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
30 { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
31 { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
32 { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
33 { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
34 { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
35 { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dr100d.h69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)
72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)
73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)
75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2)
76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1)
78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)
79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)
81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)
82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)
[all …]
H A Drs600d.h33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18)
34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1)
36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19)
37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1)
39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
[all …]
/OK3568_Linux_fs/kernel/drivers/video/rockchip/rga3/include/
H A Drga3_reg_info.h66 #define m_RGA3_SYS_CTRL_FRMEND_AUTO_RSTN_EN (0x1 << 11)
68 #define m_RGA3_SYS_CTRL_RGA_RAM_CLK_ON (0x1 << 8)
69 #define m_RGA3_SYS_CTRL_CCLK_SRESET (0x1 << 4)
70 #define m_RGA3_SYS_CTRL_ACLK_SRESET (0x1 << 3)
71 #define m_RGA3_SYS_CTRL_RGA_LGC_CLK_ON (0x1 << 2)
72 #define m_RGA3_SYS_CTRL_CMD_MODE (0x1 << 1)
73 #define m_RGA3_SYS_CTRL_RGA_SART (0x1 << 0)
76 #define s_RGA3_SYS_CTRL_CCLK_SRESET(x) ((x & 0x1) << 4)
77 #define s_RGA3_SYS_CTRL_ACLK_SRESET(x) ((x & 0x1) << 3)
78 #define s_RGA3_SYS_CTRL_CMD_MODE(x) ((x & 0x1) << 1)
[all …]
H A Drga2_reg_info.h96 #define m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS (0x1 << 12)
97 #define m_RGA2_SYS_CTRL_DST_WR_OPT_DIS (0x1 << 11)
98 #define m_RGA2_SYS_CTRL_CMD_CONTINUE_P (0x1 << 10)
99 #define m_RGA2_SYS_CTRL_HOLD_MODE_EN (0x1 << 9)
100 #define m_RGA2_SYS_CTRL_RST_HANDSAVE_P (0x1 << 7)
101 #define m_RGA2_SYS_CTRL_RST_PROTECT_P (0x1 << 6)
102 #define m_RGA2_SYS_CTRL_AUTO_RST (0x1 << 5)
103 #define m_RGA2_SYS_CTRL_CCLK_SRESET_P (0x1 << 4)
104 #define m_RGA2_SYS_CTRL_ACLK_SRESET_P (0x1 << 3)
105 #define m_RGA2_SYS_CTRL_AUTO_CKG (0x1 << 2)
[all …]

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