1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt8183-reg.h -- Mediatek 8183 audio driver reg definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 6*4882a593Smuzhiyun * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MT8183_REG_H_ 10*4882a593Smuzhiyun #define _MT8183_REG_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AUDIO_TOP_CON0 0x0000 13*4882a593Smuzhiyun #define AUDIO_TOP_CON1 0x0004 14*4882a593Smuzhiyun #define AUDIO_TOP_CON3 0x000c 15*4882a593Smuzhiyun #define AFE_DAC_CON0 0x0010 16*4882a593Smuzhiyun #define AFE_DAC_CON1 0x0014 17*4882a593Smuzhiyun #define AFE_I2S_CON 0x0018 18*4882a593Smuzhiyun #define AFE_DAIBT_CON0 0x001c 19*4882a593Smuzhiyun #define AFE_CONN0 0x0020 20*4882a593Smuzhiyun #define AFE_CONN1 0x0024 21*4882a593Smuzhiyun #define AFE_CONN2 0x0028 22*4882a593Smuzhiyun #define AFE_CONN3 0x002c 23*4882a593Smuzhiyun #define AFE_CONN4 0x0030 24*4882a593Smuzhiyun #define AFE_I2S_CON1 0x0034 25*4882a593Smuzhiyun #define AFE_I2S_CON2 0x0038 26*4882a593Smuzhiyun #define AFE_MRGIF_CON 0x003c 27*4882a593Smuzhiyun #define AFE_DL1_BASE 0x0040 28*4882a593Smuzhiyun #define AFE_DL1_CUR 0x0044 29*4882a593Smuzhiyun #define AFE_DL1_END 0x0048 30*4882a593Smuzhiyun #define AFE_I2S_CON3 0x004c 31*4882a593Smuzhiyun #define AFE_DL2_BASE 0x0050 32*4882a593Smuzhiyun #define AFE_DL2_CUR 0x0054 33*4882a593Smuzhiyun #define AFE_DL2_END 0x0058 34*4882a593Smuzhiyun #define AFE_CONN5 0x005c 35*4882a593Smuzhiyun #define AFE_CONN_24BIT 0x006c 36*4882a593Smuzhiyun #define AFE_AWB_BASE 0x0070 37*4882a593Smuzhiyun #define AFE_AWB_END 0x0078 38*4882a593Smuzhiyun #define AFE_AWB_CUR 0x007c 39*4882a593Smuzhiyun #define AFE_VUL_BASE 0x0080 40*4882a593Smuzhiyun #define AFE_VUL_END 0x0088 41*4882a593Smuzhiyun #define AFE_VUL_CUR 0x008c 42*4882a593Smuzhiyun #define AFE_CONN6 0x00bc 43*4882a593Smuzhiyun #define AFE_MEMIF_MSB 0x00cc 44*4882a593Smuzhiyun #define AFE_MEMIF_MON0 0x00d0 45*4882a593Smuzhiyun #define AFE_MEMIF_MON1 0x00d4 46*4882a593Smuzhiyun #define AFE_MEMIF_MON2 0x00d8 47*4882a593Smuzhiyun #define AFE_MEMIF_MON3 0x00dc 48*4882a593Smuzhiyun #define AFE_MEMIF_MON4 0x00e0 49*4882a593Smuzhiyun #define AFE_MEMIF_MON5 0x00e4 50*4882a593Smuzhiyun #define AFE_MEMIF_MON6 0x00e8 51*4882a593Smuzhiyun #define AFE_MEMIF_MON7 0x00ec 52*4882a593Smuzhiyun #define AFE_MEMIF_MON8 0x00f0 53*4882a593Smuzhiyun #define AFE_MEMIF_MON9 0x00f4 54*4882a593Smuzhiyun #define AFE_ADDA_DL_SRC2_CON0 0x0108 55*4882a593Smuzhiyun #define AFE_ADDA_DL_SRC2_CON1 0x010c 56*4882a593Smuzhiyun #define AFE_ADDA_UL_SRC_CON0 0x0114 57*4882a593Smuzhiyun #define AFE_ADDA_UL_SRC_CON1 0x0118 58*4882a593Smuzhiyun #define AFE_ADDA_TOP_CON0 0x0120 59*4882a593Smuzhiyun #define AFE_ADDA_UL_DL_CON0 0x0124 60*4882a593Smuzhiyun #define AFE_ADDA_SRC_DEBUG 0x012c 61*4882a593Smuzhiyun #define AFE_ADDA_SRC_DEBUG_MON0 0x0130 62*4882a593Smuzhiyun #define AFE_ADDA_SRC_DEBUG_MON1 0x0134 63*4882a593Smuzhiyun #define AFE_ADDA_UL_SRC_MON0 0x0148 64*4882a593Smuzhiyun #define AFE_ADDA_UL_SRC_MON1 0x014c 65*4882a593Smuzhiyun #define AFE_SIDETONE_DEBUG 0x01d0 66*4882a593Smuzhiyun #define AFE_SIDETONE_MON 0x01d4 67*4882a593Smuzhiyun #define AFE_SINEGEN_CON2 0x01dc 68*4882a593Smuzhiyun #define AFE_SIDETONE_CON0 0x01e0 69*4882a593Smuzhiyun #define AFE_SIDETONE_COEFF 0x01e4 70*4882a593Smuzhiyun #define AFE_SIDETONE_CON1 0x01e8 71*4882a593Smuzhiyun #define AFE_SIDETONE_GAIN 0x01ec 72*4882a593Smuzhiyun #define AFE_SINEGEN_CON0 0x01f0 73*4882a593Smuzhiyun #define AFE_TOP_CON0 0x0200 74*4882a593Smuzhiyun #define AFE_BUS_CFG 0x0240 75*4882a593Smuzhiyun #define AFE_BUS_MON0 0x0244 76*4882a593Smuzhiyun #define AFE_ADDA_PREDIS_CON0 0x0260 77*4882a593Smuzhiyun #define AFE_ADDA_PREDIS_CON1 0x0264 78*4882a593Smuzhiyun #define AFE_MRGIF_MON0 0x0270 79*4882a593Smuzhiyun #define AFE_MRGIF_MON1 0x0274 80*4882a593Smuzhiyun #define AFE_MRGIF_MON2 0x0278 81*4882a593Smuzhiyun #define AFE_I2S_MON 0x027c 82*4882a593Smuzhiyun #define AFE_ADDA_IIR_COEF_02_01 0x0290 83*4882a593Smuzhiyun #define AFE_ADDA_IIR_COEF_04_03 0x0294 84*4882a593Smuzhiyun #define AFE_ADDA_IIR_COEF_06_05 0x0298 85*4882a593Smuzhiyun #define AFE_ADDA_IIR_COEF_08_07 0x029c 86*4882a593Smuzhiyun #define AFE_ADDA_IIR_COEF_10_09 0x02a0 87*4882a593Smuzhiyun #define AFE_DAC_CON2 0x02e0 88*4882a593Smuzhiyun #define AFE_IRQ_MCU_CON1 0x02e4 89*4882a593Smuzhiyun #define AFE_IRQ_MCU_CON2 0x02e8 90*4882a593Smuzhiyun #define AFE_DAC_MON 0x02ec 91*4882a593Smuzhiyun #define AFE_VUL2_BASE 0x02f0 92*4882a593Smuzhiyun #define AFE_VUL2_END 0x02f8 93*4882a593Smuzhiyun #define AFE_VUL2_CUR 0x02fc 94*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT0 0x0300 95*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT6 0x0304 96*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT8 0x0308 97*4882a593Smuzhiyun #define AFE_IRQ_MCU_EN1 0x030c 98*4882a593Smuzhiyun #define AFE_IRQ0_MCU_CNT_MON 0x0310 99*4882a593Smuzhiyun #define AFE_IRQ6_MCU_CNT_MON 0x0314 100*4882a593Smuzhiyun #define AFE_MOD_DAI_BASE 0x0330 101*4882a593Smuzhiyun #define AFE_MOD_DAI_END 0x0338 102*4882a593Smuzhiyun #define AFE_MOD_DAI_CUR 0x033c 103*4882a593Smuzhiyun #define AFE_VUL_D2_BASE 0x0350 104*4882a593Smuzhiyun #define AFE_VUL_D2_END 0x0358 105*4882a593Smuzhiyun #define AFE_VUL_D2_CUR 0x035c 106*4882a593Smuzhiyun #define AFE_DL3_BASE 0x0360 107*4882a593Smuzhiyun #define AFE_DL3_CUR 0x0364 108*4882a593Smuzhiyun #define AFE_DL3_END 0x0368 109*4882a593Smuzhiyun #define AFE_HDMI_OUT_CON0 0x0370 110*4882a593Smuzhiyun #define AFE_HDMI_OUT_BASE 0x0374 111*4882a593Smuzhiyun #define AFE_HDMI_OUT_CUR 0x0378 112*4882a593Smuzhiyun #define AFE_HDMI_OUT_END 0x037c 113*4882a593Smuzhiyun #define AFE_HDMI_CONN0 0x0390 114*4882a593Smuzhiyun #define AFE_IRQ3_MCU_CNT_MON 0x0398 115*4882a593Smuzhiyun #define AFE_IRQ4_MCU_CNT_MON 0x039c 116*4882a593Smuzhiyun #define AFE_IRQ_MCU_CON0 0x03a0 117*4882a593Smuzhiyun #define AFE_IRQ_MCU_STATUS 0x03a4 118*4882a593Smuzhiyun #define AFE_IRQ_MCU_CLR 0x03a8 119*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT1 0x03ac 120*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT2 0x03b0 121*4882a593Smuzhiyun #define AFE_IRQ_MCU_EN 0x03b4 122*4882a593Smuzhiyun #define AFE_IRQ_MCU_MON2 0x03b8 123*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT5 0x03bc 124*4882a593Smuzhiyun #define AFE_IRQ1_MCU_CNT_MON 0x03c0 125*4882a593Smuzhiyun #define AFE_IRQ2_MCU_CNT_MON 0x03c4 126*4882a593Smuzhiyun #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8 127*4882a593Smuzhiyun #define AFE_IRQ5_MCU_CNT_MON 0x03cc 128*4882a593Smuzhiyun #define AFE_MEMIF_MINLEN 0x03d0 129*4882a593Smuzhiyun #define AFE_MEMIF_MAXLEN 0x03d4 130*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE 0x03d8 131*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT7 0x03dc 132*4882a593Smuzhiyun #define AFE_IRQ7_MCU_CNT_MON 0x03e0 133*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT3 0x03e4 134*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT4 0x03e8 135*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT11 0x03ec 136*4882a593Smuzhiyun #define AFE_APLL1_TUNER_CFG 0x03f0 137*4882a593Smuzhiyun #define AFE_APLL2_TUNER_CFG 0x03f4 138*4882a593Smuzhiyun #define AFE_MEMIF_HD_MODE 0x03f8 139*4882a593Smuzhiyun #define AFE_MEMIF_HDALIGN 0x03fc 140*4882a593Smuzhiyun #define AFE_CONN33 0x0408 141*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT12 0x040c 142*4882a593Smuzhiyun #define AFE_GAIN1_CON0 0x0410 143*4882a593Smuzhiyun #define AFE_GAIN1_CON1 0x0414 144*4882a593Smuzhiyun #define AFE_GAIN1_CON2 0x0418 145*4882a593Smuzhiyun #define AFE_GAIN1_CON3 0x041c 146*4882a593Smuzhiyun #define AFE_CONN7 0x0420 147*4882a593Smuzhiyun #define AFE_GAIN1_CUR 0x0424 148*4882a593Smuzhiyun #define AFE_GAIN2_CON0 0x0428 149*4882a593Smuzhiyun #define AFE_GAIN2_CON1 0x042c 150*4882a593Smuzhiyun #define AFE_GAIN2_CON2 0x0430 151*4882a593Smuzhiyun #define AFE_GAIN2_CON3 0x0434 152*4882a593Smuzhiyun #define AFE_CONN8 0x0438 153*4882a593Smuzhiyun #define AFE_GAIN2_CUR 0x043c 154*4882a593Smuzhiyun #define AFE_CONN9 0x0440 155*4882a593Smuzhiyun #define AFE_CONN10 0x0444 156*4882a593Smuzhiyun #define AFE_CONN11 0x0448 157*4882a593Smuzhiyun #define AFE_CONN12 0x044c 158*4882a593Smuzhiyun #define AFE_CONN13 0x0450 159*4882a593Smuzhiyun #define AFE_CONN14 0x0454 160*4882a593Smuzhiyun #define AFE_CONN15 0x0458 161*4882a593Smuzhiyun #define AFE_CONN16 0x045c 162*4882a593Smuzhiyun #define AFE_CONN17 0x0460 163*4882a593Smuzhiyun #define AFE_CONN18 0x0464 164*4882a593Smuzhiyun #define AFE_CONN19 0x0468 165*4882a593Smuzhiyun #define AFE_CONN20 0x046c 166*4882a593Smuzhiyun #define AFE_CONN21 0x0470 167*4882a593Smuzhiyun #define AFE_CONN22 0x0474 168*4882a593Smuzhiyun #define AFE_CONN23 0x0478 169*4882a593Smuzhiyun #define AFE_CONN24 0x047c 170*4882a593Smuzhiyun #define AFE_CONN_RS 0x0494 171*4882a593Smuzhiyun #define AFE_CONN_DI 0x0498 172*4882a593Smuzhiyun #define AFE_CONN25 0x04b0 173*4882a593Smuzhiyun #define AFE_CONN26 0x04b4 174*4882a593Smuzhiyun #define AFE_CONN27 0x04b8 175*4882a593Smuzhiyun #define AFE_CONN28 0x04bc 176*4882a593Smuzhiyun #define AFE_CONN29 0x04c0 177*4882a593Smuzhiyun #define AFE_CONN30 0x04c4 178*4882a593Smuzhiyun #define AFE_CONN31 0x04c8 179*4882a593Smuzhiyun #define AFE_CONN32 0x04cc 180*4882a593Smuzhiyun #define AFE_SRAM_DELSEL_CON0 0x04f0 181*4882a593Smuzhiyun #define AFE_SRAM_DELSEL_CON2 0x04f8 182*4882a593Smuzhiyun #define AFE_SRAM_DELSEL_CON3 0x04fc 183*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON12 0x0528 184*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON13 0x052c 185*4882a593Smuzhiyun #define PCM_INTF_CON1 0x0530 186*4882a593Smuzhiyun #define PCM_INTF_CON2 0x0538 187*4882a593Smuzhiyun #define PCM2_INTF_CON 0x053c 188*4882a593Smuzhiyun #define AFE_TDM_CON1 0x0548 189*4882a593Smuzhiyun #define AFE_TDM_CON2 0x054c 190*4882a593Smuzhiyun #define AFE_CONN34 0x0580 191*4882a593Smuzhiyun #define FPGA_CFG0 0x05b0 192*4882a593Smuzhiyun #define FPGA_CFG1 0x05b4 193*4882a593Smuzhiyun #define FPGA_CFG2 0x05c0 194*4882a593Smuzhiyun #define FPGA_CFG3 0x05c4 195*4882a593Smuzhiyun #define AUDIO_TOP_DBG_CON 0x05c8 196*4882a593Smuzhiyun #define AUDIO_TOP_DBG_MON0 0x05cc 197*4882a593Smuzhiyun #define AUDIO_TOP_DBG_MON1 0x05d0 198*4882a593Smuzhiyun #define AFE_IRQ8_MCU_CNT_MON 0x05e4 199*4882a593Smuzhiyun #define AFE_IRQ11_MCU_CNT_MON 0x05e8 200*4882a593Smuzhiyun #define AFE_IRQ12_MCU_CNT_MON 0x05ec 201*4882a593Smuzhiyun #define AFE_GENERAL_REG0 0x0800 202*4882a593Smuzhiyun #define AFE_GENERAL_REG1 0x0804 203*4882a593Smuzhiyun #define AFE_GENERAL_REG2 0x0808 204*4882a593Smuzhiyun #define AFE_GENERAL_REG3 0x080c 205*4882a593Smuzhiyun #define AFE_GENERAL_REG4 0x0810 206*4882a593Smuzhiyun #define AFE_GENERAL_REG5 0x0814 207*4882a593Smuzhiyun #define AFE_GENERAL_REG6 0x0818 208*4882a593Smuzhiyun #define AFE_GENERAL_REG7 0x081c 209*4882a593Smuzhiyun #define AFE_GENERAL_REG8 0x0820 210*4882a593Smuzhiyun #define AFE_GENERAL_REG9 0x0824 211*4882a593Smuzhiyun #define AFE_GENERAL_REG10 0x0828 212*4882a593Smuzhiyun #define AFE_GENERAL_REG11 0x082c 213*4882a593Smuzhiyun #define AFE_GENERAL_REG12 0x0830 214*4882a593Smuzhiyun #define AFE_GENERAL_REG13 0x0834 215*4882a593Smuzhiyun #define AFE_GENERAL_REG14 0x0838 216*4882a593Smuzhiyun #define AFE_GENERAL_REG15 0x083c 217*4882a593Smuzhiyun #define AFE_CBIP_CFG0 0x0840 218*4882a593Smuzhiyun #define AFE_CBIP_MON0 0x0844 219*4882a593Smuzhiyun #define AFE_CBIP_SLV_MUX_MON0 0x0848 220*4882a593Smuzhiyun #define AFE_CBIP_SLV_DECODER_MON0 0x084c 221*4882a593Smuzhiyun #define AFE_CONN0_1 0x0900 222*4882a593Smuzhiyun #define AFE_CONN1_1 0x0904 223*4882a593Smuzhiyun #define AFE_CONN2_1 0x0908 224*4882a593Smuzhiyun #define AFE_CONN3_1 0x090c 225*4882a593Smuzhiyun #define AFE_CONN4_1 0x0910 226*4882a593Smuzhiyun #define AFE_CONN5_1 0x0914 227*4882a593Smuzhiyun #define AFE_CONN6_1 0x0918 228*4882a593Smuzhiyun #define AFE_CONN7_1 0x091c 229*4882a593Smuzhiyun #define AFE_CONN8_1 0x0920 230*4882a593Smuzhiyun #define AFE_CONN9_1 0x0924 231*4882a593Smuzhiyun #define AFE_CONN10_1 0x0928 232*4882a593Smuzhiyun #define AFE_CONN11_1 0x092c 233*4882a593Smuzhiyun #define AFE_CONN12_1 0x0930 234*4882a593Smuzhiyun #define AFE_CONN13_1 0x0934 235*4882a593Smuzhiyun #define AFE_CONN14_1 0x0938 236*4882a593Smuzhiyun #define AFE_CONN15_1 0x093c 237*4882a593Smuzhiyun #define AFE_CONN16_1 0x0940 238*4882a593Smuzhiyun #define AFE_CONN17_1 0x0944 239*4882a593Smuzhiyun #define AFE_CONN18_1 0x0948 240*4882a593Smuzhiyun #define AFE_CONN19_1 0x094c 241*4882a593Smuzhiyun #define AFE_CONN20_1 0x0950 242*4882a593Smuzhiyun #define AFE_CONN21_1 0x0954 243*4882a593Smuzhiyun #define AFE_CONN22_1 0x0958 244*4882a593Smuzhiyun #define AFE_CONN23_1 0x095c 245*4882a593Smuzhiyun #define AFE_CONN24_1 0x0960 246*4882a593Smuzhiyun #define AFE_CONN25_1 0x0964 247*4882a593Smuzhiyun #define AFE_CONN26_1 0x0968 248*4882a593Smuzhiyun #define AFE_CONN27_1 0x096c 249*4882a593Smuzhiyun #define AFE_CONN28_1 0x0970 250*4882a593Smuzhiyun #define AFE_CONN29_1 0x0974 251*4882a593Smuzhiyun #define AFE_CONN30_1 0x0978 252*4882a593Smuzhiyun #define AFE_CONN31_1 0x097c 253*4882a593Smuzhiyun #define AFE_CONN32_1 0x0980 254*4882a593Smuzhiyun #define AFE_CONN33_1 0x0984 255*4882a593Smuzhiyun #define AFE_CONN34_1 0x0988 256*4882a593Smuzhiyun #define AFE_CONN_RS_1 0x098c 257*4882a593Smuzhiyun #define AFE_CONN_DI_1 0x0990 258*4882a593Smuzhiyun #define AFE_CONN_24BIT_1 0x0994 259*4882a593Smuzhiyun #define AFE_CONN_REG 0x0998 260*4882a593Smuzhiyun #define AFE_CONN35 0x09a0 261*4882a593Smuzhiyun #define AFE_CONN36 0x09a4 262*4882a593Smuzhiyun #define AFE_CONN37 0x09a8 263*4882a593Smuzhiyun #define AFE_CONN38 0x09ac 264*4882a593Smuzhiyun #define AFE_CONN35_1 0x09b0 265*4882a593Smuzhiyun #define AFE_CONN36_1 0x09b4 266*4882a593Smuzhiyun #define AFE_CONN37_1 0x09b8 267*4882a593Smuzhiyun #define AFE_CONN38_1 0x09bc 268*4882a593Smuzhiyun #define AFE_CONN39 0x09c0 269*4882a593Smuzhiyun #define AFE_CONN40 0x09c4 270*4882a593Smuzhiyun #define AFE_CONN41 0x09c8 271*4882a593Smuzhiyun #define AFE_CONN42 0x09cc 272*4882a593Smuzhiyun #define AFE_CONN39_1 0x09e0 273*4882a593Smuzhiyun #define AFE_CONN40_1 0x09e4 274*4882a593Smuzhiyun #define AFE_CONN41_1 0x09e8 275*4882a593Smuzhiyun #define AFE_CONN42_1 0x09ec 276*4882a593Smuzhiyun #define AFE_I2S_CON4 0x09f8 277*4882a593Smuzhiyun #define AFE_ADDA6_TOP_CON0 0x0a80 278*4882a593Smuzhiyun #define AFE_ADDA6_UL_SRC_CON0 0x0a84 279*4882a593Smuzhiyun #define AFE_ADD6_UL_SRC_CON1 0x0a88 280*4882a593Smuzhiyun #define AFE_ADDA6_SRC_DEBUG 0x0a8c 281*4882a593Smuzhiyun #define AFE_ADDA6_SRC_DEBUG_MON0 0x0a90 282*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_02_01 0x0aa0 283*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_04_03 0x0aa4 284*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_06_05 0x0aa8 285*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_08_07 0x0aac 286*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_10_09 0x0ab0 287*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_12_11 0x0ab4 288*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_14_13 0x0ab8 289*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_16_15 0x0abc 290*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_18_17 0x0ac0 291*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_20_19 0x0ac4 292*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_22_21 0x0ac8 293*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_24_23 0x0acc 294*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_26_25 0x0ad0 295*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_28_27 0x0ad4 296*4882a593Smuzhiyun #define AFE_ADDA6_ULCF_CFG_30_29 0x0ad8 297*4882a593Smuzhiyun #define AFE_ADD6A_UL_SRC_MON0 0x0ae4 298*4882a593Smuzhiyun #define AFE_ADDA6_UL_SRC_MON1 0x0ae8 299*4882a593Smuzhiyun #define AFE_CONN43 0x0af8 300*4882a593Smuzhiyun #define AFE_CONN43_1 0x0afc 301*4882a593Smuzhiyun #define AFE_DL1_BASE_MSB 0x0b00 302*4882a593Smuzhiyun #define AFE_DL1_CUR_MSB 0x0b04 303*4882a593Smuzhiyun #define AFE_DL1_END_MSB 0x0b08 304*4882a593Smuzhiyun #define AFE_DL2_BASE_MSB 0x0b10 305*4882a593Smuzhiyun #define AFE_DL2_CUR_MSB 0x0b14 306*4882a593Smuzhiyun #define AFE_DL2_END_MSB 0x0b18 307*4882a593Smuzhiyun #define AFE_AWB_BASE_MSB 0x0b20 308*4882a593Smuzhiyun #define AFE_AWB_END_MSB 0x0b28 309*4882a593Smuzhiyun #define AFE_AWB_CUR_MSB 0x0b2c 310*4882a593Smuzhiyun #define AFE_VUL_BASE_MSB 0x0b30 311*4882a593Smuzhiyun #define AFE_VUL_END_MSB 0x0b38 312*4882a593Smuzhiyun #define AFE_VUL_CUR_MSB 0x0b3c 313*4882a593Smuzhiyun #define AFE_VUL2_BASE_MSB 0x0b50 314*4882a593Smuzhiyun #define AFE_VUL2_END_MSB 0x0b58 315*4882a593Smuzhiyun #define AFE_VUL2_CUR_MSB 0x0b5c 316*4882a593Smuzhiyun #define AFE_MOD_DAI_BASE_MSB 0x0b60 317*4882a593Smuzhiyun #define AFE_MOD_DAI_END_MSB 0x0b68 318*4882a593Smuzhiyun #define AFE_MOD_DAI_CUR_MSB 0x0b6c 319*4882a593Smuzhiyun #define AFE_VUL_D2_BASE_MSB 0x0b80 320*4882a593Smuzhiyun #define AFE_VUL_D2_END_MSB 0x0b88 321*4882a593Smuzhiyun #define AFE_VUL_D2_CUR_MSB 0x0b8c 322*4882a593Smuzhiyun #define AFE_DL3_BASE_MSB 0x0b90 323*4882a593Smuzhiyun #define AFE_DL3_CUR_MSB 0x0b94 324*4882a593Smuzhiyun #define AFE_DL3_END_MSB 0x0b98 325*4882a593Smuzhiyun #define AFE_HDMI_OUT_BASE_MSB 0x0ba4 326*4882a593Smuzhiyun #define AFE_HDMI_OUT_CUR_MSB 0x0ba8 327*4882a593Smuzhiyun #define AFE_HDMI_OUT_END_MSB 0x0bac 328*4882a593Smuzhiyun #define AFE_AWB2_BASE 0x0bd0 329*4882a593Smuzhiyun #define AFE_AWB2_END 0x0bd8 330*4882a593Smuzhiyun #define AFE_AWB2_CUR 0x0bdc 331*4882a593Smuzhiyun #define AFE_AWB2_BASE_MSB 0x0be0 332*4882a593Smuzhiyun #define AFE_AWB2_END_MSB 0x0be8 333*4882a593Smuzhiyun #define AFE_AWB2_CUR_MSB 0x0bec 334*4882a593Smuzhiyun #define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c50 335*4882a593Smuzhiyun #define AFE_ADDA_DL_SDM_TEST 0x0c54 336*4882a593Smuzhiyun #define AFE_ADDA_DL_DC_COMP_CFG0 0x0c58 337*4882a593Smuzhiyun #define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c 338*4882a593Smuzhiyun #define AFE_ADDA_DL_SDM_FIFO_MON 0x0c60 339*4882a593Smuzhiyun #define AFE_ADDA_DL_SRC_LCH_MON 0x0c64 340*4882a593Smuzhiyun #define AFE_ADDA_DL_SRC_RCH_MON 0x0c68 341*4882a593Smuzhiyun #define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c 342*4882a593Smuzhiyun #define AFE_CONNSYS_I2S_CON 0x0c78 343*4882a593Smuzhiyun #define AFE_CONNSYS_I2S_MON 0x0c7c 344*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON0 0x0c80 345*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON1 0x0c84 346*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON2 0x0c88 347*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON3 0x0c8c 348*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON4 0x0c90 349*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON5 0x0c94 350*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON6 0x0c98 351*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON7 0x0c9c 352*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON8 0x0ca0 353*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON9 0x0ca4 354*4882a593Smuzhiyun #define AFE_ASRC_2CH_CON10 0x0ca8 355*4882a593Smuzhiyun #define AFE_ADDA6_IIR_COEF_02_01 0x0ce0 356*4882a593Smuzhiyun #define AFE_ADDA6_IIR_COEF_04_03 0x0ce4 357*4882a593Smuzhiyun #define AFE_ADDA6_IIR_COEF_06_05 0x0ce8 358*4882a593Smuzhiyun #define AFE_ADDA6_IIR_COEF_08_07 0x0cec 359*4882a593Smuzhiyun #define AFE_ADDA6_IIR_COEF_10_09 0x0cf0 360*4882a593Smuzhiyun #define AFE_ADDA_PREDIS_CON2 0x0d40 361*4882a593Smuzhiyun #define AFE_ADDA_PREDIS_CON3 0x0d44 362*4882a593Smuzhiyun #define AFE_MEMIF_MON12 0x0d70 363*4882a593Smuzhiyun #define AFE_MEMIF_MON13 0x0d74 364*4882a593Smuzhiyun #define AFE_MEMIF_MON14 0x0d78 365*4882a593Smuzhiyun #define AFE_MEMIF_MON15 0x0d7c 366*4882a593Smuzhiyun #define AFE_MEMIF_MON16 0x0d80 367*4882a593Smuzhiyun #define AFE_MEMIF_MON17 0x0d84 368*4882a593Smuzhiyun #define AFE_MEMIF_MON18 0x0d88 369*4882a593Smuzhiyun #define AFE_MEMIF_MON19 0x0d8c 370*4882a593Smuzhiyun #define AFE_MEMIF_MON20 0x0d90 371*4882a593Smuzhiyun #define AFE_MEMIF_MON21 0x0d94 372*4882a593Smuzhiyun #define AFE_MEMIF_MON22 0x0d98 373*4882a593Smuzhiyun #define AFE_MEMIF_MON23 0x0d9c 374*4882a593Smuzhiyun #define AFE_MEMIF_MON24 0x0da0 375*4882a593Smuzhiyun #define AFE_HD_ENGEN_ENABLE 0x0dd0 376*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_CFG0 0x0e00 377*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_TX_CFG1 0x0e14 378*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_RX_CFG0 0x0e20 379*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_RX_CFG1 0x0e24 380*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_RX_CFG2 0x0e28 381*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_MON0 0x0e34 382*4882a593Smuzhiyun #define AFE_ADDA_MTKAIF_MON1 0x0e38 383*4882a593Smuzhiyun #define AFE_AUD_PAD_TOP 0x0e40 384*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON0 0x0e80 385*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON1 0x0e84 386*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON2 0x0e88 387*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c 388*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON4 0x0e90 389*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON5 0x0e94 390*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON6 0x0e98 391*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c 392*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea0 393*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea4 394*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea8 395*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb0 396*4882a593Smuzhiyun #define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb4 397*4882a593Smuzhiyun #define GENERAL_ASRC_MODE 0x0eb8 398*4882a593Smuzhiyun #define GENERAL_ASRC_EN_ON 0x0ebc 399*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON0 0x0f00 400*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON1 0x0f04 401*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON2 0x0f08 402*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c 403*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON4 0x0f10 404*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON5 0x0f14 405*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON6 0x0f18 406*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c 407*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON8 0x0f20 408*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON9 0x0f24 409*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON10 0x0f28 410*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON12 0x0f30 411*4882a593Smuzhiyun #define AFE_GENERAL2_ASRC_2CH_CON13 0x0f34 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #define AFE_MAX_REGISTER AFE_GENERAL2_ASRC_2CH_CON13 414*4882a593Smuzhiyun #define AFE_IRQ_STATUS_BITS 0x1fff 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun /* AUDIO_TOP_CON3 */ 417*4882a593Smuzhiyun #define BCK_INVERSE_SFT 3 418*4882a593Smuzhiyun #define BCK_INVERSE_MASK 0x1 419*4882a593Smuzhiyun #define BCK_INVERSE_MASK_SFT (0x1 << 3) 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun /* AFE_DAC_CON0 */ 422*4882a593Smuzhiyun #define AWB2_ON_SFT 29 423*4882a593Smuzhiyun #define AWB2_ON_MASK 0x1 424*4882a593Smuzhiyun #define AWB2_ON_MASK_SFT (0x1 << 29) 425*4882a593Smuzhiyun #define VUL2_ON_SFT 27 426*4882a593Smuzhiyun #define VUL2_ON_MASK 0x1 427*4882a593Smuzhiyun #define VUL2_ON_MASK_SFT (0x1 << 27) 428*4882a593Smuzhiyun #define MOD_DAI_DUP_WR_SFT 26 429*4882a593Smuzhiyun #define MOD_DAI_DUP_WR_MASK 0x1 430*4882a593Smuzhiyun #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26) 431*4882a593Smuzhiyun #define VUL12_MODE_SFT 20 432*4882a593Smuzhiyun #define VUL12_MODE_MASK 0xf 433*4882a593Smuzhiyun #define VUL12_MODE_MASK_SFT (0xf << 20) 434*4882a593Smuzhiyun #define VUL12_R_MONO_SFT 11 435*4882a593Smuzhiyun #define VUL12_R_MONO_MASK 0x1 436*4882a593Smuzhiyun #define VUL12_R_MONO_MASK_SFT (0x1 << 11) 437*4882a593Smuzhiyun #define VUL12_MONO_SFT 10 438*4882a593Smuzhiyun #define VUL12_MONO_MASK 0x1 439*4882a593Smuzhiyun #define VUL12_MONO_MASK_SFT (0x1 << 10) 440*4882a593Smuzhiyun #define VUL12_ON_SFT 9 441*4882a593Smuzhiyun #define VUL12_ON_MASK 0x1 442*4882a593Smuzhiyun #define VUL12_ON_MASK_SFT (0x1 << 9) 443*4882a593Smuzhiyun #define MOD_DAI_ON_SFT 7 444*4882a593Smuzhiyun #define MOD_DAI_ON_MASK 0x1 445*4882a593Smuzhiyun #define MOD_DAI_ON_MASK_SFT (0x1 << 7) 446*4882a593Smuzhiyun #define AWB_ON_SFT 6 447*4882a593Smuzhiyun #define AWB_ON_MASK 0x1 448*4882a593Smuzhiyun #define AWB_ON_MASK_SFT (0x1 << 6) 449*4882a593Smuzhiyun #define DL3_ON_SFT 5 450*4882a593Smuzhiyun #define DL3_ON_MASK 0x1 451*4882a593Smuzhiyun #define DL3_ON_MASK_SFT (0x1 << 5) 452*4882a593Smuzhiyun #define VUL_ON_SFT 3 453*4882a593Smuzhiyun #define VUL_ON_MASK 0x1 454*4882a593Smuzhiyun #define VUL_ON_MASK_SFT (0x1 << 3) 455*4882a593Smuzhiyun #define DL2_ON_SFT 2 456*4882a593Smuzhiyun #define DL2_ON_MASK 0x1 457*4882a593Smuzhiyun #define DL2_ON_MASK_SFT (0x1 << 2) 458*4882a593Smuzhiyun #define DL1_ON_SFT 1 459*4882a593Smuzhiyun #define DL1_ON_MASK 0x1 460*4882a593Smuzhiyun #define DL1_ON_MASK_SFT (0x1 << 1) 461*4882a593Smuzhiyun #define AFE_ON_SFT 0 462*4882a593Smuzhiyun #define AFE_ON_MASK 0x1 463*4882a593Smuzhiyun #define AFE_ON_MASK_SFT (0x1 << 0) 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun /* AFE_DAC_CON1 */ 466*4882a593Smuzhiyun #define MOD_DAI_MODE_SFT 30 467*4882a593Smuzhiyun #define MOD_DAI_MODE_MASK 0x3 468*4882a593Smuzhiyun #define MOD_DAI_MODE_MASK_SFT (0x3 << 30) 469*4882a593Smuzhiyun #define VUL_R_MONO_SFT 28 470*4882a593Smuzhiyun #define VUL_R_MONO_MASK 0x1 471*4882a593Smuzhiyun #define VUL_R_MONO_MASK_SFT (0x1 << 28) 472*4882a593Smuzhiyun #define VUL_DATA_SFT 27 473*4882a593Smuzhiyun #define VUL_DATA_MASK 0x1 474*4882a593Smuzhiyun #define VUL_DATA_MASK_SFT (0x1 << 27) 475*4882a593Smuzhiyun #define AWB_R_MONO_SFT 25 476*4882a593Smuzhiyun #define AWB_R_MONO_MASK 0x1 477*4882a593Smuzhiyun #define AWB_R_MONO_MASK_SFT (0x1 << 25) 478*4882a593Smuzhiyun #define AWB_DATA_SFT 24 479*4882a593Smuzhiyun #define AWB_DATA_MASK 0x1 480*4882a593Smuzhiyun #define AWB_DATA_MASK_SFT (0x1 << 24) 481*4882a593Smuzhiyun #define DL3_DATA_SFT 23 482*4882a593Smuzhiyun #define DL3_DATA_MASK 0x1 483*4882a593Smuzhiyun #define DL3_DATA_MASK_SFT (0x1 << 23) 484*4882a593Smuzhiyun #define DL2_DATA_SFT 22 485*4882a593Smuzhiyun #define DL2_DATA_MASK 0x1 486*4882a593Smuzhiyun #define DL2_DATA_MASK_SFT (0x1 << 22) 487*4882a593Smuzhiyun #define DL1_DATA_SFT 21 488*4882a593Smuzhiyun #define DL1_DATA_MASK 0x1 489*4882a593Smuzhiyun #define DL1_DATA_MASK_SFT (0x1 << 21) 490*4882a593Smuzhiyun #define VUL_MODE_SFT 16 491*4882a593Smuzhiyun #define VUL_MODE_MASK 0xf 492*4882a593Smuzhiyun #define VUL_MODE_MASK_SFT (0xf << 16) 493*4882a593Smuzhiyun #define AWB_MODE_SFT 12 494*4882a593Smuzhiyun #define AWB_MODE_MASK 0xf 495*4882a593Smuzhiyun #define AWB_MODE_MASK_SFT (0xf << 12) 496*4882a593Smuzhiyun #define I2S_MODE_SFT 8 497*4882a593Smuzhiyun #define I2S_MODE_MASK 0xf 498*4882a593Smuzhiyun #define I2S_MODE_MASK_SFT (0xf << 8) 499*4882a593Smuzhiyun #define DL2_MODE_SFT 4 500*4882a593Smuzhiyun #define DL2_MODE_MASK 0xf 501*4882a593Smuzhiyun #define DL2_MODE_MASK_SFT (0xf << 4) 502*4882a593Smuzhiyun #define DL1_MODE_SFT 0 503*4882a593Smuzhiyun #define DL1_MODE_MASK 0xf 504*4882a593Smuzhiyun #define DL1_MODE_MASK_SFT (0xf << 0) 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* AFE_DAC_CON2 */ 507*4882a593Smuzhiyun #define AWB2_R_MONO_SFT 21 508*4882a593Smuzhiyun #define AWB2_R_MONO_MASK 0x1 509*4882a593Smuzhiyun #define AWB2_R_MONO_MASK_SFT (0x1 << 21) 510*4882a593Smuzhiyun #define AWB2_DATA_SFT 20 511*4882a593Smuzhiyun #define AWB2_DATA_MASK 0x1 512*4882a593Smuzhiyun #define AWB2_DATA_MASK_SFT (0x1 << 20) 513*4882a593Smuzhiyun #define AWB2_MODE_SFT 16 514*4882a593Smuzhiyun #define AWB2_MODE_MASK 0xf 515*4882a593Smuzhiyun #define AWB2_MODE_MASK_SFT (0xf << 16) 516*4882a593Smuzhiyun #define DL3_MODE_SFT 8 517*4882a593Smuzhiyun #define DL3_MODE_MASK 0xf 518*4882a593Smuzhiyun #define DL3_MODE_MASK_SFT (0xf << 8) 519*4882a593Smuzhiyun #define VUL2_MODE_SFT 4 520*4882a593Smuzhiyun #define VUL2_MODE_MASK 0xf 521*4882a593Smuzhiyun #define VUL2_MODE_MASK_SFT (0xf << 4) 522*4882a593Smuzhiyun #define VUL2_R_MONO_SFT 1 523*4882a593Smuzhiyun #define VUL2_R_MONO_MASK 0x1 524*4882a593Smuzhiyun #define VUL2_R_MONO_MASK_SFT (0x1 << 1) 525*4882a593Smuzhiyun #define VUL2_DATA_SFT 0 526*4882a593Smuzhiyun #define VUL2_DATA_MASK 0x1 527*4882a593Smuzhiyun #define VUL2_DATA_MASK_SFT (0x1 << 0) 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun /* AFE_DAC_MON */ 530*4882a593Smuzhiyun #define AFE_ON_RETM_SFT 0 531*4882a593Smuzhiyun #define AFE_ON_RETM_MASK 0x1 532*4882a593Smuzhiyun #define AFE_ON_RETM_MASK_SFT (0x1 << 0) 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun /* AFE_I2S_CON */ 535*4882a593Smuzhiyun #define BCK_NEG_EG_LATCH_SFT 30 536*4882a593Smuzhiyun #define BCK_NEG_EG_LATCH_MASK 0x1 537*4882a593Smuzhiyun #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30) 538*4882a593Smuzhiyun #define BCK_INV_SFT 29 539*4882a593Smuzhiyun #define BCK_INV_MASK 0x1 540*4882a593Smuzhiyun #define BCK_INV_MASK_SFT (0x1 << 29) 541*4882a593Smuzhiyun #define I2SIN_PAD_SEL_SFT 28 542*4882a593Smuzhiyun #define I2SIN_PAD_SEL_MASK 0x1 543*4882a593Smuzhiyun #define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28) 544*4882a593Smuzhiyun #define I2S_LOOPBACK_SFT 20 545*4882a593Smuzhiyun #define I2S_LOOPBACK_MASK 0x1 546*4882a593Smuzhiyun #define I2S_LOOPBACK_MASK_SFT (0x1 << 20) 547*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 548*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 549*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 550*4882a593Smuzhiyun #define I2S1_HD_EN_SFT 12 551*4882a593Smuzhiyun #define I2S1_HD_EN_MASK 0x1 552*4882a593Smuzhiyun #define I2S1_HD_EN_MASK_SFT (0x1 << 12) 553*4882a593Smuzhiyun #define INV_PAD_CTRL_SFT 7 554*4882a593Smuzhiyun #define INV_PAD_CTRL_MASK 0x1 555*4882a593Smuzhiyun #define INV_PAD_CTRL_MASK_SFT (0x1 << 7) 556*4882a593Smuzhiyun #define I2S_BYPSRC_SFT 6 557*4882a593Smuzhiyun #define I2S_BYPSRC_MASK 0x1 558*4882a593Smuzhiyun #define I2S_BYPSRC_MASK_SFT (0x1 << 6) 559*4882a593Smuzhiyun #define INV_LRCK_SFT 5 560*4882a593Smuzhiyun #define INV_LRCK_MASK 0x1 561*4882a593Smuzhiyun #define INV_LRCK_MASK_SFT (0x1 << 5) 562*4882a593Smuzhiyun #define I2S_FMT_SFT 3 563*4882a593Smuzhiyun #define I2S_FMT_MASK 0x1 564*4882a593Smuzhiyun #define I2S_FMT_MASK_SFT (0x1 << 3) 565*4882a593Smuzhiyun #define I2S_SRC_SFT 2 566*4882a593Smuzhiyun #define I2S_SRC_MASK 0x1 567*4882a593Smuzhiyun #define I2S_SRC_MASK_SFT (0x1 << 2) 568*4882a593Smuzhiyun #define I2S_WLEN_SFT 1 569*4882a593Smuzhiyun #define I2S_WLEN_MASK 0x1 570*4882a593Smuzhiyun #define I2S_WLEN_MASK_SFT (0x1 << 1) 571*4882a593Smuzhiyun #define I2S_EN_SFT 0 572*4882a593Smuzhiyun #define I2S_EN_MASK 0x1 573*4882a593Smuzhiyun #define I2S_EN_MASK_SFT (0x1 << 0) 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun /* AFE_I2S_CON1 */ 576*4882a593Smuzhiyun #define I2S2_LR_SWAP_SFT 31 577*4882a593Smuzhiyun #define I2S2_LR_SWAP_MASK 0x1 578*4882a593Smuzhiyun #define I2S2_LR_SWAP_MASK_SFT (0x1 << 31) 579*4882a593Smuzhiyun #define I2S2_SEL_O19_O20_SFT 18 580*4882a593Smuzhiyun #define I2S2_SEL_O19_O20_MASK 0x1 581*4882a593Smuzhiyun #define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18) 582*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 583*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 584*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 585*4882a593Smuzhiyun #define I2S2_SEL_O03_O04_SFT 16 586*4882a593Smuzhiyun #define I2S2_SEL_O03_O04_MASK 0x1 587*4882a593Smuzhiyun #define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16) 588*4882a593Smuzhiyun #define I2S2_32BIT_EN_SFT 13 589*4882a593Smuzhiyun #define I2S2_32BIT_EN_MASK 0x1 590*4882a593Smuzhiyun #define I2S2_32BIT_EN_MASK_SFT (0x1 << 13) 591*4882a593Smuzhiyun #define I2S2_HD_EN_SFT 12 592*4882a593Smuzhiyun #define I2S2_HD_EN_MASK 0x1 593*4882a593Smuzhiyun #define I2S2_HD_EN_MASK_SFT (0x1 << 12) 594*4882a593Smuzhiyun #define I2S2_OUT_MODE_SFT 8 595*4882a593Smuzhiyun #define I2S2_OUT_MODE_MASK 0xf 596*4882a593Smuzhiyun #define I2S2_OUT_MODE_MASK_SFT (0xf << 8) 597*4882a593Smuzhiyun #define INV_LRCK_SFT 5 598*4882a593Smuzhiyun #define INV_LRCK_MASK 0x1 599*4882a593Smuzhiyun #define INV_LRCK_MASK_SFT (0x1 << 5) 600*4882a593Smuzhiyun #define I2S2_FMT_SFT 3 601*4882a593Smuzhiyun #define I2S2_FMT_MASK 0x1 602*4882a593Smuzhiyun #define I2S2_FMT_MASK_SFT (0x1 << 3) 603*4882a593Smuzhiyun #define I2S2_WLEN_SFT 1 604*4882a593Smuzhiyun #define I2S2_WLEN_MASK 0x1 605*4882a593Smuzhiyun #define I2S2_WLEN_MASK_SFT (0x1 << 1) 606*4882a593Smuzhiyun #define I2S2_EN_SFT 0 607*4882a593Smuzhiyun #define I2S2_EN_MASK 0x1 608*4882a593Smuzhiyun #define I2S2_EN_MASK_SFT (0x1 << 0) 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun /* AFE_I2S_CON2 */ 611*4882a593Smuzhiyun #define I2S3_LR_SWAP_SFT 31 612*4882a593Smuzhiyun #define I2S3_LR_SWAP_MASK 0x1 613*4882a593Smuzhiyun #define I2S3_LR_SWAP_MASK_SFT (0x1 << 31) 614*4882a593Smuzhiyun #define I2S3_UPDATE_WORD_SFT 24 615*4882a593Smuzhiyun #define I2S3_UPDATE_WORD_MASK 0x1f 616*4882a593Smuzhiyun #define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24) 617*4882a593Smuzhiyun #define I2S3_BCK_INV_SFT 23 618*4882a593Smuzhiyun #define I2S3_BCK_INV_MASK 0x1 619*4882a593Smuzhiyun #define I2S3_BCK_INV_MASK_SFT (0x1 << 23) 620*4882a593Smuzhiyun #define I2S3_FPGA_BIT_TEST_SFT 22 621*4882a593Smuzhiyun #define I2S3_FPGA_BIT_TEST_MASK 0x1 622*4882a593Smuzhiyun #define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22) 623*4882a593Smuzhiyun #define I2S3_FPGA_BIT_SFT 21 624*4882a593Smuzhiyun #define I2S3_FPGA_BIT_MASK 0x1 625*4882a593Smuzhiyun #define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21) 626*4882a593Smuzhiyun #define I2S3_LOOPBACK_SFT 20 627*4882a593Smuzhiyun #define I2S3_LOOPBACK_MASK 0x1 628*4882a593Smuzhiyun #define I2S3_LOOPBACK_MASK_SFT (0x1 << 20) 629*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 630*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 631*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 632*4882a593Smuzhiyun #define I2S3_HD_EN_SFT 12 633*4882a593Smuzhiyun #define I2S3_HD_EN_MASK 0x1 634*4882a593Smuzhiyun #define I2S3_HD_EN_MASK_SFT (0x1 << 12) 635*4882a593Smuzhiyun #define I2S3_OUT_MODE_SFT 8 636*4882a593Smuzhiyun #define I2S3_OUT_MODE_MASK 0xf 637*4882a593Smuzhiyun #define I2S3_OUT_MODE_MASK_SFT (0xf << 8) 638*4882a593Smuzhiyun #define I2S3_FMT_SFT 3 639*4882a593Smuzhiyun #define I2S3_FMT_MASK 0x1 640*4882a593Smuzhiyun #define I2S3_FMT_MASK_SFT (0x1 << 3) 641*4882a593Smuzhiyun #define I2S3_WLEN_SFT 1 642*4882a593Smuzhiyun #define I2S3_WLEN_MASK 0x1 643*4882a593Smuzhiyun #define I2S3_WLEN_MASK_SFT (0x1 << 1) 644*4882a593Smuzhiyun #define I2S3_EN_SFT 0 645*4882a593Smuzhiyun #define I2S3_EN_MASK 0x1 646*4882a593Smuzhiyun #define I2S3_EN_MASK_SFT (0x1 << 0) 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun /* AFE_I2S_CON3 */ 649*4882a593Smuzhiyun #define I2S4_LR_SWAP_SFT 31 650*4882a593Smuzhiyun #define I2S4_LR_SWAP_MASK 0x1 651*4882a593Smuzhiyun #define I2S4_LR_SWAP_MASK_SFT (0x1 << 31) 652*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 653*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 654*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 655*4882a593Smuzhiyun #define I2S4_32BIT_EN_SFT 13 656*4882a593Smuzhiyun #define I2S4_32BIT_EN_MASK 0x1 657*4882a593Smuzhiyun #define I2S4_32BIT_EN_MASK_SFT (0x1 << 13) 658*4882a593Smuzhiyun #define I2S4_HD_EN_SFT 12 659*4882a593Smuzhiyun #define I2S4_HD_EN_MASK 0x1 660*4882a593Smuzhiyun #define I2S4_HD_EN_MASK_SFT (0x1 << 12) 661*4882a593Smuzhiyun #define I2S4_OUT_MODE_SFT 8 662*4882a593Smuzhiyun #define I2S4_OUT_MODE_MASK 0xf 663*4882a593Smuzhiyun #define I2S4_OUT_MODE_MASK_SFT (0xf << 8) 664*4882a593Smuzhiyun #define INV_LRCK_SFT 5 665*4882a593Smuzhiyun #define INV_LRCK_MASK 0x1 666*4882a593Smuzhiyun #define INV_LRCK_MASK_SFT (0x1 << 5) 667*4882a593Smuzhiyun #define I2S4_FMT_SFT 3 668*4882a593Smuzhiyun #define I2S4_FMT_MASK 0x1 669*4882a593Smuzhiyun #define I2S4_FMT_MASK_SFT (0x1 << 3) 670*4882a593Smuzhiyun #define I2S4_WLEN_SFT 1 671*4882a593Smuzhiyun #define I2S4_WLEN_MASK 0x1 672*4882a593Smuzhiyun #define I2S4_WLEN_MASK_SFT (0x1 << 1) 673*4882a593Smuzhiyun #define I2S4_EN_SFT 0 674*4882a593Smuzhiyun #define I2S4_EN_MASK 0x1 675*4882a593Smuzhiyun #define I2S4_EN_MASK_SFT (0x1 << 0) 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun /* AFE_I2S_CON4 */ 678*4882a593Smuzhiyun #define I2S5_LR_SWAP_SFT 31 679*4882a593Smuzhiyun #define I2S5_LR_SWAP_MASK 0x1 680*4882a593Smuzhiyun #define I2S5_LR_SWAP_MASK_SFT (0x1 << 31) 681*4882a593Smuzhiyun #define I2S_LOOPBACK_SFT 20 682*4882a593Smuzhiyun #define I2S_LOOPBACK_MASK 0x1 683*4882a593Smuzhiyun #define I2S_LOOPBACK_MASK_SFT (0x1 << 20) 684*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17 685*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1 686*4882a593Smuzhiyun #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17) 687*4882a593Smuzhiyun #define I2S5_32BIT_EN_SFT 13 688*4882a593Smuzhiyun #define I2S5_32BIT_EN_MASK 0x1 689*4882a593Smuzhiyun #define I2S5_32BIT_EN_MASK_SFT (0x1 << 13) 690*4882a593Smuzhiyun #define I2S5_HD_EN_SFT 12 691*4882a593Smuzhiyun #define I2S5_HD_EN_MASK 0x1 692*4882a593Smuzhiyun #define I2S5_HD_EN_MASK_SFT (0x1 << 12) 693*4882a593Smuzhiyun #define I2S5_OUT_MODE_SFT 8 694*4882a593Smuzhiyun #define I2S5_OUT_MODE_MASK 0xf 695*4882a593Smuzhiyun #define I2S5_OUT_MODE_MASK_SFT (0xf << 8) 696*4882a593Smuzhiyun #define INV_LRCK_SFT 5 697*4882a593Smuzhiyun #define INV_LRCK_MASK 0x1 698*4882a593Smuzhiyun #define INV_LRCK_MASK_SFT (0x1 << 5) 699*4882a593Smuzhiyun #define I2S5_FMT_SFT 3 700*4882a593Smuzhiyun #define I2S5_FMT_MASK 0x1 701*4882a593Smuzhiyun #define I2S5_FMT_MASK_SFT (0x1 << 3) 702*4882a593Smuzhiyun #define I2S5_WLEN_SFT 1 703*4882a593Smuzhiyun #define I2S5_WLEN_MASK 0x1 704*4882a593Smuzhiyun #define I2S5_WLEN_MASK_SFT (0x1 << 1) 705*4882a593Smuzhiyun #define I2S5_EN_SFT 0 706*4882a593Smuzhiyun #define I2S5_EN_MASK 0x1 707*4882a593Smuzhiyun #define I2S5_EN_MASK_SFT (0x1 << 0) 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun /* AFE_GAIN1_CON0 */ 710*4882a593Smuzhiyun #define GAIN1_SAMPLE_PER_STEP_SFT 8 711*4882a593Smuzhiyun #define GAIN1_SAMPLE_PER_STEP_MASK 0xff 712*4882a593Smuzhiyun #define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8) 713*4882a593Smuzhiyun #define GAIN1_MODE_SFT 4 714*4882a593Smuzhiyun #define GAIN1_MODE_MASK 0xf 715*4882a593Smuzhiyun #define GAIN1_MODE_MASK_SFT (0xf << 4) 716*4882a593Smuzhiyun #define GAIN1_ON_SFT 0 717*4882a593Smuzhiyun #define GAIN1_ON_MASK 0x1 718*4882a593Smuzhiyun #define GAIN1_ON_MASK_SFT (0x1 << 0) 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun /* AFE_GAIN1_CON1 */ 721*4882a593Smuzhiyun #define GAIN1_TARGET_SFT 0 722*4882a593Smuzhiyun #define GAIN1_TARGET_MASK 0xfffff 723*4882a593Smuzhiyun #define GAIN1_TARGET_MASK_SFT (0xfffff << 0) 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun /* AFE_GAIN2_CON0 */ 726*4882a593Smuzhiyun #define GAIN2_SAMPLE_PER_STEP_SFT 8 727*4882a593Smuzhiyun #define GAIN2_SAMPLE_PER_STEP_MASK 0xff 728*4882a593Smuzhiyun #define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8) 729*4882a593Smuzhiyun #define GAIN2_MODE_SFT 4 730*4882a593Smuzhiyun #define GAIN2_MODE_MASK 0xf 731*4882a593Smuzhiyun #define GAIN2_MODE_MASK_SFT (0xf << 4) 732*4882a593Smuzhiyun #define GAIN2_ON_SFT 0 733*4882a593Smuzhiyun #define GAIN2_ON_MASK 0x1 734*4882a593Smuzhiyun #define GAIN2_ON_MASK_SFT (0x1 << 0) 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun /* AFE_GAIN2_CON1 */ 737*4882a593Smuzhiyun #define GAIN2_TARGET_SFT 0 738*4882a593Smuzhiyun #define GAIN2_TARGET_MASK 0xfffff 739*4882a593Smuzhiyun #define GAIN2_TARGET_MASK_SFT (0xfffff << 0) 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun /* AFE_GAIN1_CUR */ 742*4882a593Smuzhiyun #define AFE_GAIN1_CUR_SFT 0 743*4882a593Smuzhiyun #define AFE_GAIN1_CUR_MASK 0xfffff 744*4882a593Smuzhiyun #define AFE_GAIN1_CUR_MASK_SFT (0xfffff << 0) 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun /* AFE_GAIN2_CUR */ 747*4882a593Smuzhiyun #define AFE_GAIN2_CUR_SFT 0 748*4882a593Smuzhiyun #define AFE_GAIN2_CUR_MASK 0xfffff 749*4882a593Smuzhiyun #define AFE_GAIN2_CUR_MASK_SFT (0xfffff << 0) 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun /* AFE_MEMIF_HD_MODE */ 752*4882a593Smuzhiyun #define AWB2_HD_SFT 28 753*4882a593Smuzhiyun #define AWB2_HD_MASK 0x3 754*4882a593Smuzhiyun #define AWB2_HD_MASK_SFT (0x3 << 28) 755*4882a593Smuzhiyun #define HDMI_HD_SFT 20 756*4882a593Smuzhiyun #define HDMI_HD_MASK 0x3 757*4882a593Smuzhiyun #define HDMI_HD_MASK_SFT (0x3 << 20) 758*4882a593Smuzhiyun #define MOD_DAI_HD_SFT 18 759*4882a593Smuzhiyun #define MOD_DAI_HD_MASK 0x3 760*4882a593Smuzhiyun #define MOD_DAI_HD_MASK_SFT (0x3 << 18) 761*4882a593Smuzhiyun #define DAI_HD_SFT 16 762*4882a593Smuzhiyun #define DAI_HD_MASK 0x3 763*4882a593Smuzhiyun #define DAI_HD_MASK_SFT (0x3 << 16) 764*4882a593Smuzhiyun #define VUL2_HD_SFT 14 765*4882a593Smuzhiyun #define VUL2_HD_MASK 0x3 766*4882a593Smuzhiyun #define VUL2_HD_MASK_SFT (0x3 << 14) 767*4882a593Smuzhiyun #define VUL12_HD_SFT 12 768*4882a593Smuzhiyun #define VUL12_HD_MASK 0x3 769*4882a593Smuzhiyun #define VUL12_HD_MASK_SFT (0x3 << 12) 770*4882a593Smuzhiyun #define VUL_HD_SFT 10 771*4882a593Smuzhiyun #define VUL_HD_MASK 0x3 772*4882a593Smuzhiyun #define VUL_HD_MASK_SFT (0x3 << 10) 773*4882a593Smuzhiyun #define AWB_HD_SFT 8 774*4882a593Smuzhiyun #define AWB_HD_MASK 0x3 775*4882a593Smuzhiyun #define AWB_HD_MASK_SFT (0x3 << 8) 776*4882a593Smuzhiyun #define DL3_HD_SFT 6 777*4882a593Smuzhiyun #define DL3_HD_MASK 0x3 778*4882a593Smuzhiyun #define DL3_HD_MASK_SFT (0x3 << 6) 779*4882a593Smuzhiyun #define DL2_HD_SFT 4 780*4882a593Smuzhiyun #define DL2_HD_MASK 0x3 781*4882a593Smuzhiyun #define DL2_HD_MASK_SFT (0x3 << 4) 782*4882a593Smuzhiyun #define DL1_HD_SFT 0 783*4882a593Smuzhiyun #define DL1_HD_MASK 0x3 784*4882a593Smuzhiyun #define DL1_HD_MASK_SFT (0x3 << 0) 785*4882a593Smuzhiyun 786*4882a593Smuzhiyun /* AFE_MEMIF_HDALIGN */ 787*4882a593Smuzhiyun #define AWB2_NORMAL_MODE_SFT 30 788*4882a593Smuzhiyun #define AWB2_NORMAL_MODE_MASK 0x1 789*4882a593Smuzhiyun #define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 30) 790*4882a593Smuzhiyun #define HDMI_NORMAL_MODE_SFT 26 791*4882a593Smuzhiyun #define HDMI_NORMAL_MODE_MASK 0x1 792*4882a593Smuzhiyun #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26) 793*4882a593Smuzhiyun #define MOD_DAI_NORMAL_MODE_SFT 25 794*4882a593Smuzhiyun #define MOD_DAI_NORMAL_MODE_MASK 0x1 795*4882a593Smuzhiyun #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25) 796*4882a593Smuzhiyun #define DAI_NORMAL_MODE_SFT 24 797*4882a593Smuzhiyun #define DAI_NORMAL_MODE_MASK 0x1 798*4882a593Smuzhiyun #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24) 799*4882a593Smuzhiyun #define VUL2_NORMAL_MODE_SFT 23 800*4882a593Smuzhiyun #define VUL2_NORMAL_MODE_MASK 0x1 801*4882a593Smuzhiyun #define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 23) 802*4882a593Smuzhiyun #define VUL12_NORMAL_MODE_SFT 22 803*4882a593Smuzhiyun #define VUL12_NORMAL_MODE_MASK 0x1 804*4882a593Smuzhiyun #define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 22) 805*4882a593Smuzhiyun #define VUL_NORMAL_MODE_SFT 21 806*4882a593Smuzhiyun #define VUL_NORMAL_MODE_MASK 0x1 807*4882a593Smuzhiyun #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21) 808*4882a593Smuzhiyun #define AWB_NORMAL_MODE_SFT 20 809*4882a593Smuzhiyun #define AWB_NORMAL_MODE_MASK 0x1 810*4882a593Smuzhiyun #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20) 811*4882a593Smuzhiyun #define DL3_NORMAL_MODE_SFT 19 812*4882a593Smuzhiyun #define DL3_NORMAL_MODE_MASK 0x1 813*4882a593Smuzhiyun #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19) 814*4882a593Smuzhiyun #define DL2_NORMAL_MODE_SFT 18 815*4882a593Smuzhiyun #define DL2_NORMAL_MODE_MASK 0x1 816*4882a593Smuzhiyun #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18) 817*4882a593Smuzhiyun #define DL1_NORMAL_MODE_SFT 16 818*4882a593Smuzhiyun #define DL1_NORMAL_MODE_MASK 0x1 819*4882a593Smuzhiyun #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16) 820*4882a593Smuzhiyun #define RESERVED1_SFT 15 821*4882a593Smuzhiyun #define RESERVED1_MASK 0x1 822*4882a593Smuzhiyun #define RESERVED1_MASK_SFT (0x1 << 15) 823*4882a593Smuzhiyun #define AWB2_ALIGN_SFT 14 824*4882a593Smuzhiyun #define AWB2_ALIGN_MASK 0x1 825*4882a593Smuzhiyun #define AWB2_ALIGN_MASK_SFT (0x1 << 14) 826*4882a593Smuzhiyun #define HDMI_HD_ALIGN_SFT 10 827*4882a593Smuzhiyun #define HDMI_HD_ALIGN_MASK 0x1 828*4882a593Smuzhiyun #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10) 829*4882a593Smuzhiyun #define MOD_DAI_HD_ALIGN_SFT 9 830*4882a593Smuzhiyun #define MOD_DAI_HD_ALIGN_MASK 0x1 831*4882a593Smuzhiyun #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9) 832*4882a593Smuzhiyun #define VUL2_HD_ALIGN_SFT 7 833*4882a593Smuzhiyun #define VUL2_HD_ALIGN_MASK 0x1 834*4882a593Smuzhiyun #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7) 835*4882a593Smuzhiyun #define VUL12_HD_ALIGN_SFT 6 836*4882a593Smuzhiyun #define VUL12_HD_ALIGN_MASK 0x1 837*4882a593Smuzhiyun #define VUL12_HD_ALIGN_MASK_SFT (0x1 << 6) 838*4882a593Smuzhiyun #define VUL_HD_ALIGN_SFT 5 839*4882a593Smuzhiyun #define VUL_HD_ALIGN_MASK 0x1 840*4882a593Smuzhiyun #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5) 841*4882a593Smuzhiyun #define AWB_HD_ALIGN_SFT 4 842*4882a593Smuzhiyun #define AWB_HD_ALIGN_MASK 0x1 843*4882a593Smuzhiyun #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4) 844*4882a593Smuzhiyun #define DL3_HD_ALIGN_SFT 3 845*4882a593Smuzhiyun #define DL3_HD_ALIGN_MASK 0x1 846*4882a593Smuzhiyun #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3) 847*4882a593Smuzhiyun #define DL2_HD_ALIGN_SFT 2 848*4882a593Smuzhiyun #define DL2_HD_ALIGN_MASK 0x1 849*4882a593Smuzhiyun #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2) 850*4882a593Smuzhiyun #define DL1_HD_ALIGN_SFT 0 851*4882a593Smuzhiyun #define DL1_HD_ALIGN_MASK 0x1 852*4882a593Smuzhiyun #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0) 853*4882a593Smuzhiyun 854*4882a593Smuzhiyun /* PCM_INTF_CON1 */ 855*4882a593Smuzhiyun #define PCM_FIX_VALUE_SEL_SFT 31 856*4882a593Smuzhiyun #define PCM_FIX_VALUE_SEL_MASK 0x1 857*4882a593Smuzhiyun #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31) 858*4882a593Smuzhiyun #define PCM_BUFFER_LOOPBACK_SFT 30 859*4882a593Smuzhiyun #define PCM_BUFFER_LOOPBACK_MASK 0x1 860*4882a593Smuzhiyun #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30) 861*4882a593Smuzhiyun #define PCM_PARALLEL_LOOPBACK_SFT 29 862*4882a593Smuzhiyun #define PCM_PARALLEL_LOOPBACK_MASK 0x1 863*4882a593Smuzhiyun #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29) 864*4882a593Smuzhiyun #define PCM_SERIAL_LOOPBACK_SFT 28 865*4882a593Smuzhiyun #define PCM_SERIAL_LOOPBACK_MASK 0x1 866*4882a593Smuzhiyun #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28) 867*4882a593Smuzhiyun #define PCM_DAI_PCM_LOOPBACK_SFT 27 868*4882a593Smuzhiyun #define PCM_DAI_PCM_LOOPBACK_MASK 0x1 869*4882a593Smuzhiyun #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27) 870*4882a593Smuzhiyun #define PCM_I2S_PCM_LOOPBACK_SFT 26 871*4882a593Smuzhiyun #define PCM_I2S_PCM_LOOPBACK_MASK 0x1 872*4882a593Smuzhiyun #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26) 873*4882a593Smuzhiyun #define PCM_SYNC_DELSEL_SFT 25 874*4882a593Smuzhiyun #define PCM_SYNC_DELSEL_MASK 0x1 875*4882a593Smuzhiyun #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25) 876*4882a593Smuzhiyun #define PCM_TX_LR_SWAP_SFT 24 877*4882a593Smuzhiyun #define PCM_TX_LR_SWAP_MASK 0x1 878*4882a593Smuzhiyun #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24) 879*4882a593Smuzhiyun #define PCM_SYNC_OUT_INV_SFT 23 880*4882a593Smuzhiyun #define PCM_SYNC_OUT_INV_MASK 0x1 881*4882a593Smuzhiyun #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23) 882*4882a593Smuzhiyun #define PCM_BCLK_OUT_INV_SFT 22 883*4882a593Smuzhiyun #define PCM_BCLK_OUT_INV_MASK 0x1 884*4882a593Smuzhiyun #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22) 885*4882a593Smuzhiyun #define PCM_SYNC_IN_INV_SFT 21 886*4882a593Smuzhiyun #define PCM_SYNC_IN_INV_MASK 0x1 887*4882a593Smuzhiyun #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21) 888*4882a593Smuzhiyun #define PCM_BCLK_IN_INV_SFT 20 889*4882a593Smuzhiyun #define PCM_BCLK_IN_INV_MASK 0x1 890*4882a593Smuzhiyun #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20) 891*4882a593Smuzhiyun #define PCM_TX_LCH_RPT_SFT 19 892*4882a593Smuzhiyun #define PCM_TX_LCH_RPT_MASK 0x1 893*4882a593Smuzhiyun #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19) 894*4882a593Smuzhiyun #define PCM_VBT_16K_MODE_SFT 18 895*4882a593Smuzhiyun #define PCM_VBT_16K_MODE_MASK 0x1 896*4882a593Smuzhiyun #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18) 897*4882a593Smuzhiyun #define PCM_EXT_MODEM_SFT 17 898*4882a593Smuzhiyun #define PCM_EXT_MODEM_MASK 0x1 899*4882a593Smuzhiyun #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17) 900*4882a593Smuzhiyun #define PCM_24BIT_SFT 16 901*4882a593Smuzhiyun #define PCM_24BIT_MASK 0x1 902*4882a593Smuzhiyun #define PCM_24BIT_MASK_SFT (0x1 << 16) 903*4882a593Smuzhiyun #define PCM_WLEN_SFT 14 904*4882a593Smuzhiyun #define PCM_WLEN_MASK 0x3 905*4882a593Smuzhiyun #define PCM_WLEN_MASK_SFT (0x3 << 14) 906*4882a593Smuzhiyun #define PCM_SYNC_LENGTH_SFT 9 907*4882a593Smuzhiyun #define PCM_SYNC_LENGTH_MASK 0x1f 908*4882a593Smuzhiyun #define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9) 909*4882a593Smuzhiyun #define PCM_SYNC_TYPE_SFT 8 910*4882a593Smuzhiyun #define PCM_SYNC_TYPE_MASK 0x1 911*4882a593Smuzhiyun #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8) 912*4882a593Smuzhiyun #define PCM_BT_MODE_SFT 7 913*4882a593Smuzhiyun #define PCM_BT_MODE_MASK 0x1 914*4882a593Smuzhiyun #define PCM_BT_MODE_MASK_SFT (0x1 << 7) 915*4882a593Smuzhiyun #define PCM_BYP_ASRC_SFT 6 916*4882a593Smuzhiyun #define PCM_BYP_ASRC_MASK 0x1 917*4882a593Smuzhiyun #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6) 918*4882a593Smuzhiyun #define PCM_SLAVE_SFT 5 919*4882a593Smuzhiyun #define PCM_SLAVE_MASK 0x1 920*4882a593Smuzhiyun #define PCM_SLAVE_MASK_SFT (0x1 << 5) 921*4882a593Smuzhiyun #define PCM_MODE_SFT 3 922*4882a593Smuzhiyun #define PCM_MODE_MASK 0x3 923*4882a593Smuzhiyun #define PCM_MODE_MASK_SFT (0x3 << 3) 924*4882a593Smuzhiyun #define PCM_FMT_SFT 1 925*4882a593Smuzhiyun #define PCM_FMT_MASK 0x3 926*4882a593Smuzhiyun #define PCM_FMT_MASK_SFT (0x3 << 1) 927*4882a593Smuzhiyun #define PCM_EN_SFT 0 928*4882a593Smuzhiyun #define PCM_EN_MASK 0x1 929*4882a593Smuzhiyun #define PCM_EN_MASK_SFT (0x1 << 0) 930*4882a593Smuzhiyun 931*4882a593Smuzhiyun /* PCM_INTF_CON2 */ 932*4882a593Smuzhiyun #define PCM1_TX_FIFO_OV_SFT 31 933*4882a593Smuzhiyun #define PCM1_TX_FIFO_OV_MASK 0x1 934*4882a593Smuzhiyun #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31) 935*4882a593Smuzhiyun #define PCM1_RX_FIFO_OV_SFT 30 936*4882a593Smuzhiyun #define PCM1_RX_FIFO_OV_MASK 0x1 937*4882a593Smuzhiyun #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30) 938*4882a593Smuzhiyun #define PCM2_TX_FIFO_OV_SFT 29 939*4882a593Smuzhiyun #define PCM2_TX_FIFO_OV_MASK 0x1 940*4882a593Smuzhiyun #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29) 941*4882a593Smuzhiyun #define PCM2_RX_FIFO_OV_SFT 28 942*4882a593Smuzhiyun #define PCM2_RX_FIFO_OV_MASK 0x1 943*4882a593Smuzhiyun #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28) 944*4882a593Smuzhiyun #define PCM1_SYNC_GLITCH_SFT 27 945*4882a593Smuzhiyun #define PCM1_SYNC_GLITCH_MASK 0x1 946*4882a593Smuzhiyun #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27) 947*4882a593Smuzhiyun #define PCM2_SYNC_GLITCH_SFT 26 948*4882a593Smuzhiyun #define PCM2_SYNC_GLITCH_MASK 0x1 949*4882a593Smuzhiyun #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26) 950*4882a593Smuzhiyun #define TX3_RCH_DBG_MODE_SFT 17 951*4882a593Smuzhiyun #define TX3_RCH_DBG_MODE_MASK 0x1 952*4882a593Smuzhiyun #define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17) 953*4882a593Smuzhiyun #define PCM1_PCM2_LOOPBACK_SFT 16 954*4882a593Smuzhiyun #define PCM1_PCM2_LOOPBACK_MASK 0x1 955*4882a593Smuzhiyun #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16) 956*4882a593Smuzhiyun #define DAI_PCM_LOOPBACK_CH_SFT 14 957*4882a593Smuzhiyun #define DAI_PCM_LOOPBACK_CH_MASK 0x3 958*4882a593Smuzhiyun #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14) 959*4882a593Smuzhiyun #define I2S_PCM_LOOPBACK_CH_SFT 12 960*4882a593Smuzhiyun #define I2S_PCM_LOOPBACK_CH_MASK 0x3 961*4882a593Smuzhiyun #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12) 962*4882a593Smuzhiyun #define TX_FIX_VALUE_SFT 0 963*4882a593Smuzhiyun #define TX_FIX_VALUE_MASK 0xff 964*4882a593Smuzhiyun #define TX_FIX_VALUE_MASK_SFT (0xff << 0) 965*4882a593Smuzhiyun 966*4882a593Smuzhiyun /* PCM2_INTF_CON */ 967*4882a593Smuzhiyun #define PCM2_TX_FIX_VALUE_SFT 24 968*4882a593Smuzhiyun #define PCM2_TX_FIX_VALUE_MASK 0xff 969*4882a593Smuzhiyun #define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24) 970*4882a593Smuzhiyun #define PCM2_FIX_VALUE_SEL_SFT 23 971*4882a593Smuzhiyun #define PCM2_FIX_VALUE_SEL_MASK 0x1 972*4882a593Smuzhiyun #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23) 973*4882a593Smuzhiyun #define PCM2_BUFFER_LOOPBACK_SFT 22 974*4882a593Smuzhiyun #define PCM2_BUFFER_LOOPBACK_MASK 0x1 975*4882a593Smuzhiyun #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22) 976*4882a593Smuzhiyun #define PCM2_PARALLEL_LOOPBACK_SFT 21 977*4882a593Smuzhiyun #define PCM2_PARALLEL_LOOPBACK_MASK 0x1 978*4882a593Smuzhiyun #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21) 979*4882a593Smuzhiyun #define PCM2_SERIAL_LOOPBACK_SFT 20 980*4882a593Smuzhiyun #define PCM2_SERIAL_LOOPBACK_MASK 0x1 981*4882a593Smuzhiyun #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20) 982*4882a593Smuzhiyun #define PCM2_DAI_PCM_LOOPBACK_SFT 19 983*4882a593Smuzhiyun #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1 984*4882a593Smuzhiyun #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19) 985*4882a593Smuzhiyun #define PCM2_I2S_PCM_LOOPBACK_SFT 18 986*4882a593Smuzhiyun #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1 987*4882a593Smuzhiyun #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18) 988*4882a593Smuzhiyun #define PCM2_SYNC_DELSEL_SFT 17 989*4882a593Smuzhiyun #define PCM2_SYNC_DELSEL_MASK 0x1 990*4882a593Smuzhiyun #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17) 991*4882a593Smuzhiyun #define PCM2_TX_LR_SWAP_SFT 16 992*4882a593Smuzhiyun #define PCM2_TX_LR_SWAP_MASK 0x1 993*4882a593Smuzhiyun #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16) 994*4882a593Smuzhiyun #define PCM2_SYNC_IN_INV_SFT 15 995*4882a593Smuzhiyun #define PCM2_SYNC_IN_INV_MASK 0x1 996*4882a593Smuzhiyun #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15) 997*4882a593Smuzhiyun #define PCM2_BCLK_IN_INV_SFT 14 998*4882a593Smuzhiyun #define PCM2_BCLK_IN_INV_MASK 0x1 999*4882a593Smuzhiyun #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14) 1000*4882a593Smuzhiyun #define PCM2_TX_LCH_RPT_SFT 13 1001*4882a593Smuzhiyun #define PCM2_TX_LCH_RPT_MASK 0x1 1002*4882a593Smuzhiyun #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13) 1003*4882a593Smuzhiyun #define PCM2_VBT_16K_MODE_SFT 12 1004*4882a593Smuzhiyun #define PCM2_VBT_16K_MODE_MASK 0x1 1005*4882a593Smuzhiyun #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12) 1006*4882a593Smuzhiyun #define PCM2_LOOPBACK_CH_SEL_SFT 10 1007*4882a593Smuzhiyun #define PCM2_LOOPBACK_CH_SEL_MASK 0x3 1008*4882a593Smuzhiyun #define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10) 1009*4882a593Smuzhiyun #define PCM2_TX2_BT_MODE_SFT 8 1010*4882a593Smuzhiyun #define PCM2_TX2_BT_MODE_MASK 0x1 1011*4882a593Smuzhiyun #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8) 1012*4882a593Smuzhiyun #define PCM2_BT_MODE_SFT 7 1013*4882a593Smuzhiyun #define PCM2_BT_MODE_MASK 0x1 1014*4882a593Smuzhiyun #define PCM2_BT_MODE_MASK_SFT (0x1 << 7) 1015*4882a593Smuzhiyun #define PCM2_AFIFO_SFT 6 1016*4882a593Smuzhiyun #define PCM2_AFIFO_MASK 0x1 1017*4882a593Smuzhiyun #define PCM2_AFIFO_MASK_SFT (0x1 << 6) 1018*4882a593Smuzhiyun #define PCM2_WLEN_SFT 5 1019*4882a593Smuzhiyun #define PCM2_WLEN_MASK 0x1 1020*4882a593Smuzhiyun #define PCM2_WLEN_MASK_SFT (0x1 << 5) 1021*4882a593Smuzhiyun #define PCM2_MODE_SFT 3 1022*4882a593Smuzhiyun #define PCM2_MODE_MASK 0x3 1023*4882a593Smuzhiyun #define PCM2_MODE_MASK_SFT (0x3 << 3) 1024*4882a593Smuzhiyun #define PCM2_FMT_SFT 1 1025*4882a593Smuzhiyun #define PCM2_FMT_MASK 0x3 1026*4882a593Smuzhiyun #define PCM2_FMT_MASK_SFT (0x3 << 1) 1027*4882a593Smuzhiyun #define PCM2_EN_SFT 0 1028*4882a593Smuzhiyun #define PCM2_EN_MASK 0x1 1029*4882a593Smuzhiyun #define PCM2_EN_MASK_SFT (0x1 << 0) 1030*4882a593Smuzhiyun 1031*4882a593Smuzhiyun /* AFE_ADDA_MTKAIF_CFG0 */ 1032*4882a593Smuzhiyun #define MTKAIF_RXIF_CLKINV_ADC_SFT 31 1033*4882a593Smuzhiyun #define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1 1034*4882a593Smuzhiyun #define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31) 1035*4882a593Smuzhiyun #define MTKAIF_RXIF_BYPASS_SRC_SFT 17 1036*4882a593Smuzhiyun #define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1 1037*4882a593Smuzhiyun #define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17) 1038*4882a593Smuzhiyun #define MTKAIF_RXIF_PROTOCOL2_SFT 16 1039*4882a593Smuzhiyun #define MTKAIF_RXIF_PROTOCOL2_MASK 0x1 1040*4882a593Smuzhiyun #define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16) 1041*4882a593Smuzhiyun #define MTKAIF_TXIF_BYPASS_SRC_SFT 5 1042*4882a593Smuzhiyun #define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1 1043*4882a593Smuzhiyun #define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5) 1044*4882a593Smuzhiyun #define MTKAIF_TXIF_PROTOCOL2_SFT 4 1045*4882a593Smuzhiyun #define MTKAIF_TXIF_PROTOCOL2_MASK 0x1 1046*4882a593Smuzhiyun #define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4) 1047*4882a593Smuzhiyun #define MTKAIF_TXIF_8TO5_SFT 2 1048*4882a593Smuzhiyun #define MTKAIF_TXIF_8TO5_MASK 0x1 1049*4882a593Smuzhiyun #define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2) 1050*4882a593Smuzhiyun #define MTKAIF_RXIF_8TO5_SFT 1 1051*4882a593Smuzhiyun #define MTKAIF_RXIF_8TO5_MASK 0x1 1052*4882a593Smuzhiyun #define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1) 1053*4882a593Smuzhiyun #define MTKAIF_IF_LOOPBACK1_SFT 0 1054*4882a593Smuzhiyun #define MTKAIF_IF_LOOPBACK1_MASK 0x1 1055*4882a593Smuzhiyun #define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0) 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun /* AFE_ADDA_MTKAIF_RX_CFG2 */ 1058*4882a593Smuzhiyun #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16 1059*4882a593Smuzhiyun #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1 1060*4882a593Smuzhiyun #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16) 1061*4882a593Smuzhiyun #define MTKAIF_RXIF_DELAY_CYCLE_SFT 12 1062*4882a593Smuzhiyun #define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf 1063*4882a593Smuzhiyun #define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12) 1064*4882a593Smuzhiyun #define MTKAIF_RXIF_DELAY_DATA_SFT 8 1065*4882a593Smuzhiyun #define MTKAIF_RXIF_DELAY_DATA_MASK 0x1 1066*4882a593Smuzhiyun #define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8) 1067*4882a593Smuzhiyun #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4 1068*4882a593Smuzhiyun #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7 1069*4882a593Smuzhiyun #define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4) 1070*4882a593Smuzhiyun 1071*4882a593Smuzhiyun /* AFE_ADDA_DL_SRC2_CON0 */ 1072*4882a593Smuzhiyun #define DL_2_INPUT_MODE_CTL_SFT 28 1073*4882a593Smuzhiyun #define DL_2_INPUT_MODE_CTL_MASK 0xf 1074*4882a593Smuzhiyun #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28) 1075*4882a593Smuzhiyun #define DL_2_CH1_SATURATION_EN_CTL_SFT 27 1076*4882a593Smuzhiyun #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1 1077*4882a593Smuzhiyun #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27) 1078*4882a593Smuzhiyun #define DL_2_CH2_SATURATION_EN_CTL_SFT 26 1079*4882a593Smuzhiyun #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1 1080*4882a593Smuzhiyun #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26) 1081*4882a593Smuzhiyun #define DL_2_OUTPUT_SEL_CTL_SFT 24 1082*4882a593Smuzhiyun #define DL_2_OUTPUT_SEL_CTL_MASK 0x3 1083*4882a593Smuzhiyun #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24) 1084*4882a593Smuzhiyun #define DL_2_FADEIN_0START_EN_SFT 16 1085*4882a593Smuzhiyun #define DL_2_FADEIN_0START_EN_MASK 0x3 1086*4882a593Smuzhiyun #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16) 1087*4882a593Smuzhiyun #define DL_DISABLE_HW_CG_CTL_SFT 15 1088*4882a593Smuzhiyun #define DL_DISABLE_HW_CG_CTL_MASK 0x1 1089*4882a593Smuzhiyun #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15) 1090*4882a593Smuzhiyun #define C_DATA_EN_SEL_CTL_PRE_SFT 14 1091*4882a593Smuzhiyun #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1 1092*4882a593Smuzhiyun #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14) 1093*4882a593Smuzhiyun #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13 1094*4882a593Smuzhiyun #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1 1095*4882a593Smuzhiyun #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13) 1096*4882a593Smuzhiyun #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12 1097*4882a593Smuzhiyun #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 1098*4882a593Smuzhiyun #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12) 1099*4882a593Smuzhiyun #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11 1100*4882a593Smuzhiyun #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 1101*4882a593Smuzhiyun #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11) 1102*4882a593Smuzhiyun #define DL2_ARAMPSP_CTL_PRE_SFT 9 1103*4882a593Smuzhiyun #define DL2_ARAMPSP_CTL_PRE_MASK 0x3 1104*4882a593Smuzhiyun #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9) 1105*4882a593Smuzhiyun #define DL_2_IIRMODE_CTL_PRE_SFT 6 1106*4882a593Smuzhiyun #define DL_2_IIRMODE_CTL_PRE_MASK 0x7 1107*4882a593Smuzhiyun #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6) 1108*4882a593Smuzhiyun #define DL_2_VOICE_MODE_CTL_PRE_SFT 5 1109*4882a593Smuzhiyun #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1 1110*4882a593Smuzhiyun #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) 1111*4882a593Smuzhiyun #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4 1112*4882a593Smuzhiyun #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1 1113*4882a593Smuzhiyun #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) 1114*4882a593Smuzhiyun #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3 1115*4882a593Smuzhiyun #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1 1116*4882a593Smuzhiyun #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) 1117*4882a593Smuzhiyun #define DL_2_IIR_ON_CTL_PRE_SFT 2 1118*4882a593Smuzhiyun #define DL_2_IIR_ON_CTL_PRE_MASK 0x1 1119*4882a593Smuzhiyun #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2) 1120*4882a593Smuzhiyun #define DL_2_GAIN_ON_CTL_PRE_SFT 1 1121*4882a593Smuzhiyun #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1 1122*4882a593Smuzhiyun #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) 1123*4882a593Smuzhiyun #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 1124*4882a593Smuzhiyun #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1 1125*4882a593Smuzhiyun #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) 1126*4882a593Smuzhiyun 1127*4882a593Smuzhiyun /* AFE_ADDA_DL_SRC2_CON1 */ 1128*4882a593Smuzhiyun #define DL_2_GAIN_CTL_PRE_SFT 16 1129*4882a593Smuzhiyun #define DL_2_GAIN_CTL_PRE_MASK 0xffff 1130*4882a593Smuzhiyun #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16) 1131*4882a593Smuzhiyun #define DL_2_GAIN_MODE_CTL_SFT 0 1132*4882a593Smuzhiyun #define DL_2_GAIN_MODE_CTL_MASK 0x1 1133*4882a593Smuzhiyun #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) 1134*4882a593Smuzhiyun 1135*4882a593Smuzhiyun /* AFE_ADDA_UL_SRC_CON0 */ 1136*4882a593Smuzhiyun #define ULCF_CFG_EN_CTL_SFT 31 1137*4882a593Smuzhiyun #define ULCF_CFG_EN_CTL_MASK 0x1 1138*4882a593Smuzhiyun #define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31) 1139*4882a593Smuzhiyun #define UL_MODE_3P25M_CH2_CTL_SFT 22 1140*4882a593Smuzhiyun #define UL_MODE_3P25M_CH2_CTL_MASK 0x1 1141*4882a593Smuzhiyun #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) 1142*4882a593Smuzhiyun #define UL_MODE_3P25M_CH1_CTL_SFT 21 1143*4882a593Smuzhiyun #define UL_MODE_3P25M_CH1_CTL_MASK 0x1 1144*4882a593Smuzhiyun #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) 1145*4882a593Smuzhiyun #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 1146*4882a593Smuzhiyun #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 1147*4882a593Smuzhiyun #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) 1148*4882a593Smuzhiyun #define DMIC_LOW_POWER_MODE_CTL_SFT 14 1149*4882a593Smuzhiyun #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 1150*4882a593Smuzhiyun #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) 1151*4882a593Smuzhiyun #define UL_DISABLE_HW_CG_CTL_SFT 12 1152*4882a593Smuzhiyun #define UL_DISABLE_HW_CG_CTL_MASK 0x1 1153*4882a593Smuzhiyun #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) 1154*4882a593Smuzhiyun #define UL_IIR_ON_TMP_CTL_SFT 10 1155*4882a593Smuzhiyun #define UL_IIR_ON_TMP_CTL_MASK 0x1 1156*4882a593Smuzhiyun #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) 1157*4882a593Smuzhiyun #define UL_IIRMODE_CTL_SFT 7 1158*4882a593Smuzhiyun #define UL_IIRMODE_CTL_MASK 0x7 1159*4882a593Smuzhiyun #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) 1160*4882a593Smuzhiyun #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 1161*4882a593Smuzhiyun #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 1162*4882a593Smuzhiyun #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) 1163*4882a593Smuzhiyun #define UL_LOOP_BACK_MODE_CTL_SFT 2 1164*4882a593Smuzhiyun #define UL_LOOP_BACK_MODE_CTL_MASK 0x1 1165*4882a593Smuzhiyun #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) 1166*4882a593Smuzhiyun #define UL_SDM_3_LEVEL_CTL_SFT 1 1167*4882a593Smuzhiyun #define UL_SDM_3_LEVEL_CTL_MASK 0x1 1168*4882a593Smuzhiyun #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) 1169*4882a593Smuzhiyun #define UL_SRC_ON_TMP_CTL_SFT 0 1170*4882a593Smuzhiyun #define UL_SRC_ON_TMP_CTL_MASK 0x1 1171*4882a593Smuzhiyun #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) 1172*4882a593Smuzhiyun 1173*4882a593Smuzhiyun /* AFE_ADDA_UL_SRC_CON1 */ 1174*4882a593Smuzhiyun #define C_DAC_EN_CTL_SFT 27 1175*4882a593Smuzhiyun #define C_DAC_EN_CTL_MASK 0x1 1176*4882a593Smuzhiyun #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) 1177*4882a593Smuzhiyun #define C_MUTE_SW_CTL_SFT 26 1178*4882a593Smuzhiyun #define C_MUTE_SW_CTL_MASK 0x1 1179*4882a593Smuzhiyun #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) 1180*4882a593Smuzhiyun #define ASDM_SRC_SEL_CTL_SFT 25 1181*4882a593Smuzhiyun #define ASDM_SRC_SEL_CTL_MASK 0x1 1182*4882a593Smuzhiyun #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25) 1183*4882a593Smuzhiyun #define C_AMP_DIV_CH2_CTL_SFT 21 1184*4882a593Smuzhiyun #define C_AMP_DIV_CH2_CTL_MASK 0x7 1185*4882a593Smuzhiyun #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) 1186*4882a593Smuzhiyun #define C_FREQ_DIV_CH2_CTL_SFT 16 1187*4882a593Smuzhiyun #define C_FREQ_DIV_CH2_CTL_MASK 0x1f 1188*4882a593Smuzhiyun #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) 1189*4882a593Smuzhiyun #define C_SINE_MODE_CH2_CTL_SFT 12 1190*4882a593Smuzhiyun #define C_SINE_MODE_CH2_CTL_MASK 0xf 1191*4882a593Smuzhiyun #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) 1192*4882a593Smuzhiyun #define C_AMP_DIV_CH1_CTL_SFT 9 1193*4882a593Smuzhiyun #define C_AMP_DIV_CH1_CTL_MASK 0x7 1194*4882a593Smuzhiyun #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) 1195*4882a593Smuzhiyun #define C_FREQ_DIV_CH1_CTL_SFT 4 1196*4882a593Smuzhiyun #define C_FREQ_DIV_CH1_CTL_MASK 0x1f 1197*4882a593Smuzhiyun #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) 1198*4882a593Smuzhiyun #define C_SINE_MODE_CH1_CTL_SFT 0 1199*4882a593Smuzhiyun #define C_SINE_MODE_CH1_CTL_MASK 0xf 1200*4882a593Smuzhiyun #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) 1201*4882a593Smuzhiyun 1202*4882a593Smuzhiyun /* AFE_ADDA_TOP_CON0 */ 1203*4882a593Smuzhiyun #define C_LOOP_BACK_MODE_CTL_SFT 12 1204*4882a593Smuzhiyun #define C_LOOP_BACK_MODE_CTL_MASK 0xf 1205*4882a593Smuzhiyun #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12) 1206*4882a593Smuzhiyun #define C_EXT_ADC_CTL_SFT 0 1207*4882a593Smuzhiyun #define C_EXT_ADC_CTL_MASK 0x1 1208*4882a593Smuzhiyun #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0) 1209*4882a593Smuzhiyun 1210*4882a593Smuzhiyun /* AFE_ADDA_UL_DL_CON0 */ 1211*4882a593Smuzhiyun #define AFE_ADDA6_UL_LR_SWAP_SFT 15 1212*4882a593Smuzhiyun #define AFE_ADDA6_UL_LR_SWAP_MASK 0x1 1213*4882a593Smuzhiyun #define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15) 1214*4882a593Smuzhiyun #define AFE_ADDA6_CKDIV_RST_SFT 14 1215*4882a593Smuzhiyun #define AFE_ADDA6_CKDIV_RST_MASK 0x1 1216*4882a593Smuzhiyun #define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14) 1217*4882a593Smuzhiyun #define AFE_ADDA6_FIFO_AUTO_RST_SFT 13 1218*4882a593Smuzhiyun #define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1 1219*4882a593Smuzhiyun #define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13) 1220*4882a593Smuzhiyun #define UL_FIFO_DIGMIC_TESTIN_SFT 5 1221*4882a593Smuzhiyun #define UL_FIFO_DIGMIC_TESTIN_MASK 0x3 1222*4882a593Smuzhiyun #define UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5) 1223*4882a593Smuzhiyun #define UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4 1224*4882a593Smuzhiyun #define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1 1225*4882a593Smuzhiyun #define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4) 1226*4882a593Smuzhiyun #define ADDA_AFE_ON_SFT 0 1227*4882a593Smuzhiyun #define ADDA_AFE_ON_MASK 0x1 1228*4882a593Smuzhiyun #define ADDA_AFE_ON_MASK_SFT (0x1 << 0) 1229*4882a593Smuzhiyun 1230*4882a593Smuzhiyun /* AFE_SIDETONE_CON0 */ 1231*4882a593Smuzhiyun #define R_RDY_SFT 30 1232*4882a593Smuzhiyun #define R_RDY_MASK 0x1 1233*4882a593Smuzhiyun #define R_RDY_MASK_SFT (0x1 << 30) 1234*4882a593Smuzhiyun #define W_RDY_SFT 29 1235*4882a593Smuzhiyun #define W_RDY_MASK 0x1 1236*4882a593Smuzhiyun #define W_RDY_MASK_SFT (0x1 << 29) 1237*4882a593Smuzhiyun #define R_W_EN_SFT 25 1238*4882a593Smuzhiyun #define R_W_EN_MASK 0x1 1239*4882a593Smuzhiyun #define R_W_EN_MASK_SFT (0x1 << 25) 1240*4882a593Smuzhiyun #define R_W_SEL_SFT 24 1241*4882a593Smuzhiyun #define R_W_SEL_MASK 0x1 1242*4882a593Smuzhiyun #define R_W_SEL_MASK_SFT (0x1 << 24) 1243*4882a593Smuzhiyun #define SEL_CH2_SFT 23 1244*4882a593Smuzhiyun #define SEL_CH2_MASK 0x1 1245*4882a593Smuzhiyun #define SEL_CH2_MASK_SFT (0x1 << 23) 1246*4882a593Smuzhiyun #define SIDE_TONE_COEFFICIENT_ADDR_SFT 16 1247*4882a593Smuzhiyun #define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f 1248*4882a593Smuzhiyun #define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16) 1249*4882a593Smuzhiyun #define SIDE_TONE_COEFFICIENT_SFT 0 1250*4882a593Smuzhiyun #define SIDE_TONE_COEFFICIENT_MASK 0xffff 1251*4882a593Smuzhiyun #define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0) 1252*4882a593Smuzhiyun 1253*4882a593Smuzhiyun /* AFE_SIDETONE_COEFF */ 1254*4882a593Smuzhiyun #define SIDE_TONE_COEFF_SFT 0 1255*4882a593Smuzhiyun #define SIDE_TONE_COEFF_MASK 0xffff 1256*4882a593Smuzhiyun #define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0) 1257*4882a593Smuzhiyun 1258*4882a593Smuzhiyun /* AFE_SIDETONE_CON1 */ 1259*4882a593Smuzhiyun #define STF_BYPASS_MODE_SFT 31 1260*4882a593Smuzhiyun #define STF_BYPASS_MODE_MASK 0x1 1261*4882a593Smuzhiyun #define STF_BYPASS_MODE_MASK_SFT (0x1 << 31) 1262*4882a593Smuzhiyun #define STF_BYPASS_MODE_O28_O29_SFT 30 1263*4882a593Smuzhiyun #define STF_BYPASS_MODE_O28_O29_MASK 0x1 1264*4882a593Smuzhiyun #define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30) 1265*4882a593Smuzhiyun #define STF_BYPASS_MODE_I2S4_SFT 29 1266*4882a593Smuzhiyun #define STF_BYPASS_MODE_I2S4_MASK 0x1 1267*4882a593Smuzhiyun #define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29) 1268*4882a593Smuzhiyun #define STF_BYPASS_MODE_I2S5_SFT 28 1269*4882a593Smuzhiyun #define STF_BYPASS_MODE_I2S5_MASK 0x1 1270*4882a593Smuzhiyun #define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28) 1271*4882a593Smuzhiyun #define STF_INPUT_EN_SEL_SFT 13 1272*4882a593Smuzhiyun #define STF_INPUT_EN_SEL_MASK 0x1 1273*4882a593Smuzhiyun #define STF_INPUT_EN_SEL_MASK_SFT (0x1 << 13) 1274*4882a593Smuzhiyun #define STF_SOURCE_FROM_O19O20_SFT 12 1275*4882a593Smuzhiyun #define STF_SOURCE_FROM_O19O20_MASK 0x1 1276*4882a593Smuzhiyun #define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12) 1277*4882a593Smuzhiyun #define SIDE_TONE_ON_SFT 8 1278*4882a593Smuzhiyun #define SIDE_TONE_ON_MASK 0x1 1279*4882a593Smuzhiyun #define SIDE_TONE_ON_MASK_SFT (0x1 << 8) 1280*4882a593Smuzhiyun #define SIDE_TONE_HALF_TAP_NUM_SFT 0 1281*4882a593Smuzhiyun #define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f 1282*4882a593Smuzhiyun #define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0) 1283*4882a593Smuzhiyun 1284*4882a593Smuzhiyun /* AFE_SIDETONE_GAIN */ 1285*4882a593Smuzhiyun #define POSITIVE_GAIN_SFT 16 1286*4882a593Smuzhiyun #define POSITIVE_GAIN_MASK 0x7 1287*4882a593Smuzhiyun #define POSITIVE_GAIN_MASK_SFT (0x7 << 16) 1288*4882a593Smuzhiyun #define SIDE_TONE_GAIN_SFT 0 1289*4882a593Smuzhiyun #define SIDE_TONE_GAIN_MASK 0xffff 1290*4882a593Smuzhiyun #define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0) 1291*4882a593Smuzhiyun 1292*4882a593Smuzhiyun /* AFE_ADDA_DL_SDM_DCCOMP_CON */ 1293*4882a593Smuzhiyun #define AUD_DC_COMP_EN_SFT 8 1294*4882a593Smuzhiyun #define AUD_DC_COMP_EN_MASK 0x1 1295*4882a593Smuzhiyun #define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8) 1296*4882a593Smuzhiyun #define ATTGAIN_CTL_SFT 0 1297*4882a593Smuzhiyun #define ATTGAIN_CTL_MASK 0x3f 1298*4882a593Smuzhiyun #define ATTGAIN_CTL_MASK_SFT (0x3f << 0) 1299*4882a593Smuzhiyun 1300*4882a593Smuzhiyun /* AFE_SINEGEN_CON0 */ 1301*4882a593Smuzhiyun #define DAC_EN_SFT 26 1302*4882a593Smuzhiyun #define DAC_EN_MASK 0x1 1303*4882a593Smuzhiyun #define DAC_EN_MASK_SFT (0x1 << 26) 1304*4882a593Smuzhiyun #define MUTE_SW_CH2_SFT 25 1305*4882a593Smuzhiyun #define MUTE_SW_CH2_MASK 0x1 1306*4882a593Smuzhiyun #define MUTE_SW_CH2_MASK_SFT (0x1 << 25) 1307*4882a593Smuzhiyun #define MUTE_SW_CH1_SFT 24 1308*4882a593Smuzhiyun #define MUTE_SW_CH1_MASK 0x1 1309*4882a593Smuzhiyun #define MUTE_SW_CH1_MASK_SFT (0x1 << 24) 1310*4882a593Smuzhiyun #define SINE_MODE_CH2_SFT 20 1311*4882a593Smuzhiyun #define SINE_MODE_CH2_MASK 0xf 1312*4882a593Smuzhiyun #define SINE_MODE_CH2_MASK_SFT (0xf << 20) 1313*4882a593Smuzhiyun #define AMP_DIV_CH2_SFT 17 1314*4882a593Smuzhiyun #define AMP_DIV_CH2_MASK 0x7 1315*4882a593Smuzhiyun #define AMP_DIV_CH2_MASK_SFT (0x7 << 17) 1316*4882a593Smuzhiyun #define FREQ_DIV_CH2_SFT 12 1317*4882a593Smuzhiyun #define FREQ_DIV_CH2_MASK 0x1f 1318*4882a593Smuzhiyun #define FREQ_DIV_CH2_MASK_SFT (0x1f << 12) 1319*4882a593Smuzhiyun #define SINE_MODE_CH1_SFT 8 1320*4882a593Smuzhiyun #define SINE_MODE_CH1_MASK 0xf 1321*4882a593Smuzhiyun #define SINE_MODE_CH1_MASK_SFT (0xf << 8) 1322*4882a593Smuzhiyun #define AMP_DIV_CH1_SFT 5 1323*4882a593Smuzhiyun #define AMP_DIV_CH1_MASK 0x7 1324*4882a593Smuzhiyun #define AMP_DIV_CH1_MASK_SFT (0x7 << 5) 1325*4882a593Smuzhiyun #define FREQ_DIV_CH1_SFT 0 1326*4882a593Smuzhiyun #define FREQ_DIV_CH1_MASK 0x1f 1327*4882a593Smuzhiyun #define FREQ_DIV_CH1_MASK_SFT (0x1f << 0) 1328*4882a593Smuzhiyun 1329*4882a593Smuzhiyun /* AFE_SINEGEN_CON2 */ 1330*4882a593Smuzhiyun #define INNER_LOOP_BACK_MODE_SFT 0 1331*4882a593Smuzhiyun #define INNER_LOOP_BACK_MODE_MASK 0x3f 1332*4882a593Smuzhiyun #define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0) 1333*4882a593Smuzhiyun 1334*4882a593Smuzhiyun /* AFE_MEMIF_MINLEN */ 1335*4882a593Smuzhiyun #define HDMI_MINLEN_SFT 24 1336*4882a593Smuzhiyun #define HDMI_MINLEN_MASK 0xf 1337*4882a593Smuzhiyun #define HDMI_MINLEN_MASK_SFT (0xf << 24) 1338*4882a593Smuzhiyun #define DL3_MINLEN_SFT 12 1339*4882a593Smuzhiyun #define DL3_MINLEN_MASK 0xf 1340*4882a593Smuzhiyun #define DL3_MINLEN_MASK_SFT (0xf << 12) 1341*4882a593Smuzhiyun #define DL2_MINLEN_SFT 8 1342*4882a593Smuzhiyun #define DL2_MINLEN_MASK 0xf 1343*4882a593Smuzhiyun #define DL2_MINLEN_MASK_SFT (0xf << 8) 1344*4882a593Smuzhiyun #define DL1_DATA2_MINLEN_SFT 4 1345*4882a593Smuzhiyun #define DL1_DATA2_MINLEN_MASK 0xf 1346*4882a593Smuzhiyun #define DL1_DATA2_MINLEN_MASK_SFT (0xf << 4) 1347*4882a593Smuzhiyun #define DL1_MINLEN_SFT 0 1348*4882a593Smuzhiyun #define DL1_MINLEN_MASK 0xf 1349*4882a593Smuzhiyun #define DL1_MINLEN_MASK_SFT (0xf << 0) 1350*4882a593Smuzhiyun 1351*4882a593Smuzhiyun /* AFE_MEMIF_MAXLEN */ 1352*4882a593Smuzhiyun #define HDMI_MAXLEN_SFT 24 1353*4882a593Smuzhiyun #define HDMI_MAXLEN_MASK 0xf 1354*4882a593Smuzhiyun #define HDMI_MAXLEN_MASK_SFT (0xf << 24) 1355*4882a593Smuzhiyun #define DL3_MAXLEN_SFT 8 1356*4882a593Smuzhiyun #define DL3_MAXLEN_MASK 0xf 1357*4882a593Smuzhiyun #define DL3_MAXLEN_MASK_SFT (0xf << 8) 1358*4882a593Smuzhiyun #define DL2_MAXLEN_SFT 4 1359*4882a593Smuzhiyun #define DL2_MAXLEN_MASK 0xf 1360*4882a593Smuzhiyun #define DL2_MAXLEN_MASK_SFT (0xf << 4) 1361*4882a593Smuzhiyun #define DL1_MAXLEN_SFT 0 1362*4882a593Smuzhiyun #define DL1_MAXLEN_MASK 0x3 1363*4882a593Smuzhiyun #define DL1_MAXLEN_MASK_SFT (0x3 << 0) 1364*4882a593Smuzhiyun 1365*4882a593Smuzhiyun /* AFE_MEMIF_PBUF_SIZE */ 1366*4882a593Smuzhiyun #define VUL12_4CH_SFT 17 1367*4882a593Smuzhiyun #define VUL12_4CH_MASK 0x1 1368*4882a593Smuzhiyun #define VUL12_4CH_MASK_SFT (0x1 << 17) 1369*4882a593Smuzhiyun #define DL3_PBUF_SIZE_SFT 10 1370*4882a593Smuzhiyun #define DL3_PBUF_SIZE_MASK 0x3 1371*4882a593Smuzhiyun #define DL3_PBUF_SIZE_MASK_SFT (0x3 << 10) 1372*4882a593Smuzhiyun #define HDMI_PBUF_SIZE_SFT 4 1373*4882a593Smuzhiyun #define HDMI_PBUF_SIZE_MASK 0x3 1374*4882a593Smuzhiyun #define HDMI_PBUF_SIZE_MASK_SFT (0x3 << 4) 1375*4882a593Smuzhiyun #define DL2_PBUF_SIZE_SFT 2 1376*4882a593Smuzhiyun #define DL2_PBUF_SIZE_MASK 0x3 1377*4882a593Smuzhiyun #define DL2_PBUF_SIZE_MASK_SFT (0x3 << 2) 1378*4882a593Smuzhiyun #define DL1_PBUF_SIZE_SFT 0 1379*4882a593Smuzhiyun #define DL1_PBUF_SIZE_MASK 0x3 1380*4882a593Smuzhiyun #define DL1_PBUF_SIZE_MASK_SFT (0x3 << 0) 1381*4882a593Smuzhiyun 1382*4882a593Smuzhiyun /* AFE_HD_ENGEN_ENABLE */ 1383*4882a593Smuzhiyun #define AFE_24M_ON_SFT 1 1384*4882a593Smuzhiyun #define AFE_24M_ON_MASK 0x1 1385*4882a593Smuzhiyun #define AFE_24M_ON_MASK_SFT (0x1 << 1) 1386*4882a593Smuzhiyun #define AFE_22M_ON_SFT 0 1387*4882a593Smuzhiyun #define AFE_22M_ON_MASK 0x1 1388*4882a593Smuzhiyun #define AFE_22M_ON_MASK_SFT (0x1 << 0) 1389*4882a593Smuzhiyun 1390*4882a593Smuzhiyun /* AFE_IRQ_MCU_CON0 */ 1391*4882a593Smuzhiyun #define IRQ12_MCU_ON_SFT 12 1392*4882a593Smuzhiyun #define IRQ12_MCU_ON_MASK 0x1 1393*4882a593Smuzhiyun #define IRQ12_MCU_ON_MASK_SFT (0x1 << 12) 1394*4882a593Smuzhiyun #define IRQ11_MCU_ON_SFT 11 1395*4882a593Smuzhiyun #define IRQ11_MCU_ON_MASK 0x1 1396*4882a593Smuzhiyun #define IRQ11_MCU_ON_MASK_SFT (0x1 << 11) 1397*4882a593Smuzhiyun #define IRQ10_MCU_ON_SFT 10 1398*4882a593Smuzhiyun #define IRQ10_MCU_ON_MASK 0x1 1399*4882a593Smuzhiyun #define IRQ10_MCU_ON_MASK_SFT (0x1 << 10) 1400*4882a593Smuzhiyun #define IRQ9_MCU_ON_SFT 9 1401*4882a593Smuzhiyun #define IRQ9_MCU_ON_MASK 0x1 1402*4882a593Smuzhiyun #define IRQ9_MCU_ON_MASK_SFT (0x1 << 9) 1403*4882a593Smuzhiyun #define IRQ8_MCU_ON_SFT 8 1404*4882a593Smuzhiyun #define IRQ8_MCU_ON_MASK 0x1 1405*4882a593Smuzhiyun #define IRQ8_MCU_ON_MASK_SFT (0x1 << 8) 1406*4882a593Smuzhiyun #define IRQ7_MCU_ON_SFT 7 1407*4882a593Smuzhiyun #define IRQ7_MCU_ON_MASK 0x1 1408*4882a593Smuzhiyun #define IRQ7_MCU_ON_MASK_SFT (0x1 << 7) 1409*4882a593Smuzhiyun #define IRQ6_MCU_ON_SFT 6 1410*4882a593Smuzhiyun #define IRQ6_MCU_ON_MASK 0x1 1411*4882a593Smuzhiyun #define IRQ6_MCU_ON_MASK_SFT (0x1 << 6) 1412*4882a593Smuzhiyun #define IRQ5_MCU_ON_SFT 5 1413*4882a593Smuzhiyun #define IRQ5_MCU_ON_MASK 0x1 1414*4882a593Smuzhiyun #define IRQ5_MCU_ON_MASK_SFT (0x1 << 5) 1415*4882a593Smuzhiyun #define IRQ4_MCU_ON_SFT 4 1416*4882a593Smuzhiyun #define IRQ4_MCU_ON_MASK 0x1 1417*4882a593Smuzhiyun #define IRQ4_MCU_ON_MASK_SFT (0x1 << 4) 1418*4882a593Smuzhiyun #define IRQ3_MCU_ON_SFT 3 1419*4882a593Smuzhiyun #define IRQ3_MCU_ON_MASK 0x1 1420*4882a593Smuzhiyun #define IRQ3_MCU_ON_MASK_SFT (0x1 << 3) 1421*4882a593Smuzhiyun #define IRQ2_MCU_ON_SFT 2 1422*4882a593Smuzhiyun #define IRQ2_MCU_ON_MASK 0x1 1423*4882a593Smuzhiyun #define IRQ2_MCU_ON_MASK_SFT (0x1 << 2) 1424*4882a593Smuzhiyun #define IRQ1_MCU_ON_SFT 1 1425*4882a593Smuzhiyun #define IRQ1_MCU_ON_MASK 0x1 1426*4882a593Smuzhiyun #define IRQ1_MCU_ON_MASK_SFT (0x1 << 1) 1427*4882a593Smuzhiyun #define IRQ0_MCU_ON_SFT 0 1428*4882a593Smuzhiyun #define IRQ0_MCU_ON_MASK 0x1 1429*4882a593Smuzhiyun #define IRQ0_MCU_ON_MASK_SFT (0x1 << 0) 1430*4882a593Smuzhiyun 1431*4882a593Smuzhiyun /* AFE_IRQ_MCU_CON1 */ 1432*4882a593Smuzhiyun #define IRQ7_MCU_MODE_SFT 28 1433*4882a593Smuzhiyun #define IRQ7_MCU_MODE_MASK 0xf 1434*4882a593Smuzhiyun #define IRQ7_MCU_MODE_MASK_SFT (0xf << 28) 1435*4882a593Smuzhiyun #define IRQ6_MCU_MODE_SFT 24 1436*4882a593Smuzhiyun #define IRQ6_MCU_MODE_MASK 0xf 1437*4882a593Smuzhiyun #define IRQ6_MCU_MODE_MASK_SFT (0xf << 24) 1438*4882a593Smuzhiyun #define IRQ5_MCU_MODE_SFT 20 1439*4882a593Smuzhiyun #define IRQ5_MCU_MODE_MASK 0xf 1440*4882a593Smuzhiyun #define IRQ5_MCU_MODE_MASK_SFT (0xf << 20) 1441*4882a593Smuzhiyun #define IRQ4_MCU_MODE_SFT 16 1442*4882a593Smuzhiyun #define IRQ4_MCU_MODE_MASK 0xf 1443*4882a593Smuzhiyun #define IRQ4_MCU_MODE_MASK_SFT (0xf << 16) 1444*4882a593Smuzhiyun #define IRQ3_MCU_MODE_SFT 12 1445*4882a593Smuzhiyun #define IRQ3_MCU_MODE_MASK 0xf 1446*4882a593Smuzhiyun #define IRQ3_MCU_MODE_MASK_SFT (0xf << 12) 1447*4882a593Smuzhiyun #define IRQ2_MCU_MODE_SFT 8 1448*4882a593Smuzhiyun #define IRQ2_MCU_MODE_MASK 0xf 1449*4882a593Smuzhiyun #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8) 1450*4882a593Smuzhiyun #define IRQ1_MCU_MODE_SFT 4 1451*4882a593Smuzhiyun #define IRQ1_MCU_MODE_MASK 0xf 1452*4882a593Smuzhiyun #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4) 1453*4882a593Smuzhiyun #define IRQ0_MCU_MODE_SFT 0 1454*4882a593Smuzhiyun #define IRQ0_MCU_MODE_MASK 0xf 1455*4882a593Smuzhiyun #define IRQ0_MCU_MODE_MASK_SFT (0xf << 0) 1456*4882a593Smuzhiyun 1457*4882a593Smuzhiyun /* AFE_IRQ_MCU_CON2 */ 1458*4882a593Smuzhiyun #define IRQ12_MCU_MODE_SFT 4 1459*4882a593Smuzhiyun #define IRQ12_MCU_MODE_MASK 0xf 1460*4882a593Smuzhiyun #define IRQ12_MCU_MODE_MASK_SFT (0xf << 4) 1461*4882a593Smuzhiyun #define IRQ11_MCU_MODE_SFT 0 1462*4882a593Smuzhiyun #define IRQ11_MCU_MODE_MASK 0xf 1463*4882a593Smuzhiyun #define IRQ11_MCU_MODE_MASK_SFT (0xf << 0) 1464*4882a593Smuzhiyun 1465*4882a593Smuzhiyun /* AFE_IRQ_MCU_CLR */ 1466*4882a593Smuzhiyun #define IRQ12_MCU_MISS_CNT_CLR_SFT 28 1467*4882a593Smuzhiyun #define IRQ12_MCU_MISS_CNT_CLR_MASK 0x1 1468*4882a593Smuzhiyun #define IRQ12_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 28) 1469*4882a593Smuzhiyun #define IRQ11_MCU_MISS_CNT_CLR_SFT 27 1470*4882a593Smuzhiyun #define IRQ11_MCU_MISS_CNT_CLR_MASK 0x1 1471*4882a593Smuzhiyun #define IRQ11_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 27) 1472*4882a593Smuzhiyun #define IRQ10_MCU_MISS_CLR_SFT 26 1473*4882a593Smuzhiyun #define IRQ10_MCU_MISS_CLR_MASK 0x1 1474*4882a593Smuzhiyun #define IRQ10_MCU_MISS_CLR_MASK_SFT (0x1 << 26) 1475*4882a593Smuzhiyun #define IRQ9_MCU_MISS_CLR_SFT 25 1476*4882a593Smuzhiyun #define IRQ9_MCU_MISS_CLR_MASK 0x1 1477*4882a593Smuzhiyun #define IRQ9_MCU_MISS_CLR_MASK_SFT (0x1 << 25) 1478*4882a593Smuzhiyun #define IRQ8_MCU_MISS_CLR_SFT 24 1479*4882a593Smuzhiyun #define IRQ8_MCU_MISS_CLR_MASK 0x1 1480*4882a593Smuzhiyun #define IRQ8_MCU_MISS_CLR_MASK_SFT (0x1 << 24) 1481*4882a593Smuzhiyun #define IRQ7_MCU_MISS_CLR_SFT 23 1482*4882a593Smuzhiyun #define IRQ7_MCU_MISS_CLR_MASK 0x1 1483*4882a593Smuzhiyun #define IRQ7_MCU_MISS_CLR_MASK_SFT (0x1 << 23) 1484*4882a593Smuzhiyun #define IRQ6_MCU_MISS_CLR_SFT 22 1485*4882a593Smuzhiyun #define IRQ6_MCU_MISS_CLR_MASK 0x1 1486*4882a593Smuzhiyun #define IRQ6_MCU_MISS_CLR_MASK_SFT (0x1 << 22) 1487*4882a593Smuzhiyun #define IRQ5_MCU_MISS_CLR_SFT 21 1488*4882a593Smuzhiyun #define IRQ5_MCU_MISS_CLR_MASK 0x1 1489*4882a593Smuzhiyun #define IRQ5_MCU_MISS_CLR_MASK_SFT (0x1 << 21) 1490*4882a593Smuzhiyun #define IRQ4_MCU_MISS_CLR_SFT 20 1491*4882a593Smuzhiyun #define IRQ4_MCU_MISS_CLR_MASK 0x1 1492*4882a593Smuzhiyun #define IRQ4_MCU_MISS_CLR_MASK_SFT (0x1 << 20) 1493*4882a593Smuzhiyun #define IRQ3_MCU_MISS_CLR_SFT 19 1494*4882a593Smuzhiyun #define IRQ3_MCU_MISS_CLR_MASK 0x1 1495*4882a593Smuzhiyun #define IRQ3_MCU_MISS_CLR_MASK_SFT (0x1 << 19) 1496*4882a593Smuzhiyun #define IRQ2_MCU_MISS_CLR_SFT 18 1497*4882a593Smuzhiyun #define IRQ2_MCU_MISS_CLR_MASK 0x1 1498*4882a593Smuzhiyun #define IRQ2_MCU_MISS_CLR_MASK_SFT (0x1 << 18) 1499*4882a593Smuzhiyun #define IRQ1_MCU_MISS_CLR_SFT 17 1500*4882a593Smuzhiyun #define IRQ1_MCU_MISS_CLR_MASK 0x1 1501*4882a593Smuzhiyun #define IRQ1_MCU_MISS_CLR_MASK_SFT (0x1 << 17) 1502*4882a593Smuzhiyun #define IRQ0_MCU_MISS_CLR_SFT 16 1503*4882a593Smuzhiyun #define IRQ0_MCU_MISS_CLR_MASK 0x1 1504*4882a593Smuzhiyun #define IRQ0_MCU_MISS_CLR_MASK_SFT (0x1 << 16) 1505*4882a593Smuzhiyun #define IRQ12_MCU_CLR_SFT 12 1506*4882a593Smuzhiyun #define IRQ12_MCU_CLR_MASK 0x1 1507*4882a593Smuzhiyun #define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12) 1508*4882a593Smuzhiyun #define IRQ11_MCU_CLR_SFT 11 1509*4882a593Smuzhiyun #define IRQ11_MCU_CLR_MASK 0x1 1510*4882a593Smuzhiyun #define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11) 1511*4882a593Smuzhiyun #define IRQ10_MCU_CLR_SFT 10 1512*4882a593Smuzhiyun #define IRQ10_MCU_CLR_MASK 0x1 1513*4882a593Smuzhiyun #define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10) 1514*4882a593Smuzhiyun #define IRQ9_MCU_CLR_SFT 9 1515*4882a593Smuzhiyun #define IRQ9_MCU_CLR_MASK 0x1 1516*4882a593Smuzhiyun #define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9) 1517*4882a593Smuzhiyun #define IRQ8_MCU_CLR_SFT 8 1518*4882a593Smuzhiyun #define IRQ8_MCU_CLR_MASK 0x1 1519*4882a593Smuzhiyun #define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8) 1520*4882a593Smuzhiyun #define IRQ7_MCU_CLR_SFT 7 1521*4882a593Smuzhiyun #define IRQ7_MCU_CLR_MASK 0x1 1522*4882a593Smuzhiyun #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7) 1523*4882a593Smuzhiyun #define IRQ6_MCU_CLR_SFT 6 1524*4882a593Smuzhiyun #define IRQ6_MCU_CLR_MASK 0x1 1525*4882a593Smuzhiyun #define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6) 1526*4882a593Smuzhiyun #define IRQ5_MCU_CLR_SFT 5 1527*4882a593Smuzhiyun #define IRQ5_MCU_CLR_MASK 0x1 1528*4882a593Smuzhiyun #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5) 1529*4882a593Smuzhiyun #define IRQ4_MCU_CLR_SFT 4 1530*4882a593Smuzhiyun #define IRQ4_MCU_CLR_MASK 0x1 1531*4882a593Smuzhiyun #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4) 1532*4882a593Smuzhiyun #define IRQ3_MCU_CLR_SFT 3 1533*4882a593Smuzhiyun #define IRQ3_MCU_CLR_MASK 0x1 1534*4882a593Smuzhiyun #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3) 1535*4882a593Smuzhiyun #define IRQ2_MCU_CLR_SFT 2 1536*4882a593Smuzhiyun #define IRQ2_MCU_CLR_MASK 0x1 1537*4882a593Smuzhiyun #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2) 1538*4882a593Smuzhiyun #define IRQ1_MCU_CLR_SFT 1 1539*4882a593Smuzhiyun #define IRQ1_MCU_CLR_MASK 0x1 1540*4882a593Smuzhiyun #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1) 1541*4882a593Smuzhiyun #define IRQ0_MCU_CLR_SFT 0 1542*4882a593Smuzhiyun #define IRQ0_MCU_CLR_MASK 0x1 1543*4882a593Smuzhiyun #define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0) 1544*4882a593Smuzhiyun 1545*4882a593Smuzhiyun /* AFE_MEMIF_MSB */ 1546*4882a593Smuzhiyun #define CPU_COMPACT_MODE_SFT 29 1547*4882a593Smuzhiyun #define CPU_COMPACT_MODE_MASK 0x1 1548*4882a593Smuzhiyun #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 29) 1549*4882a593Smuzhiyun #define CPU_HD_ALIGN_SFT 28 1550*4882a593Smuzhiyun #define CPU_HD_ALIGN_MASK 0x1 1551*4882a593Smuzhiyun #define CPU_HD_ALIGN_MASK_SFT (0x1 << 28) 1552*4882a593Smuzhiyun #define AWB2_AXI_WR_SIGN_SFT 24 1553*4882a593Smuzhiyun #define AWB2_AXI_WR_SIGN_MASK 0x1 1554*4882a593Smuzhiyun #define AWB2_AXI_WR_SIGN_MASK_SFT (0x1 << 24) 1555*4882a593Smuzhiyun #define VUL2_AXI_WR_SIGN_SFT 22 1556*4882a593Smuzhiyun #define VUL2_AXI_WR_SIGN_MASK 0x1 1557*4882a593Smuzhiyun #define VUL2_AXI_WR_SIGN_MASK_SFT (0x1 << 22) 1558*4882a593Smuzhiyun #define VUL12_AXI_WR_SIGN_SFT 21 1559*4882a593Smuzhiyun #define VUL12_AXI_WR_SIGN_MASK 0x1 1560*4882a593Smuzhiyun #define VUL12_AXI_WR_SIGN_MASK_SFT (0x1 << 21) 1561*4882a593Smuzhiyun #define VUL_AXI_WR_SIGN_SFT 20 1562*4882a593Smuzhiyun #define VUL_AXI_WR_SIGN_MASK 0x1 1563*4882a593Smuzhiyun #define VUL_AXI_WR_SIGN_MASK_SFT (0x1 << 20) 1564*4882a593Smuzhiyun #define MOD_DAI_AXI_WR_SIGN_SFT 18 1565*4882a593Smuzhiyun #define MOD_DAI_AXI_WR_SIGN_MASK 0x1 1566*4882a593Smuzhiyun #define MOD_DAI_AXI_WR_SIGN_MASK_SFT (0x1 << 18) 1567*4882a593Smuzhiyun #define AWB_MSTR_SIGN_SFT 17 1568*4882a593Smuzhiyun #define AWB_MSTR_SIGN_MASK 0x1 1569*4882a593Smuzhiyun #define AWB_MSTR_SIGN_MASK_SFT (0x1 << 17) 1570*4882a593Smuzhiyun #define SYSRAM_SIGN_SFT 16 1571*4882a593Smuzhiyun #define SYSRAM_SIGN_MASK 0x1 1572*4882a593Smuzhiyun #define SYSRAM_SIGN_MASK_SFT (0x1 << 16) 1573*4882a593Smuzhiyun 1574*4882a593Smuzhiyun /* AFE_HDMI_CONN0 */ 1575*4882a593Smuzhiyun #define HDMI_O_7_SFT 21 1576*4882a593Smuzhiyun #define HDMI_O_7_MASK 0x7 1577*4882a593Smuzhiyun #define HDMI_O_7_MASK_SFT (0x7 << 21) 1578*4882a593Smuzhiyun #define HDMI_O_6_SFT 18 1579*4882a593Smuzhiyun #define HDMI_O_6_MASK 0x7 1580*4882a593Smuzhiyun #define HDMI_O_6_MASK_SFT (0x7 << 18) 1581*4882a593Smuzhiyun #define HDMI_O_5_SFT 15 1582*4882a593Smuzhiyun #define HDMI_O_5_MASK 0x7 1583*4882a593Smuzhiyun #define HDMI_O_5_MASK_SFT (0x7 << 15) 1584*4882a593Smuzhiyun #define HDMI_O_4_SFT 12 1585*4882a593Smuzhiyun #define HDMI_O_4_MASK 0x7 1586*4882a593Smuzhiyun #define HDMI_O_4_MASK_SFT (0x7 << 12) 1587*4882a593Smuzhiyun #define HDMI_O_3_SFT 9 1588*4882a593Smuzhiyun #define HDMI_O_3_MASK 0x7 1589*4882a593Smuzhiyun #define HDMI_O_3_MASK_SFT (0x7 << 9) 1590*4882a593Smuzhiyun #define HDMI_O_2_SFT 6 1591*4882a593Smuzhiyun #define HDMI_O_2_MASK 0x7 1592*4882a593Smuzhiyun #define HDMI_O_2_MASK_SFT (0x7 << 6) 1593*4882a593Smuzhiyun #define HDMI_O_1_SFT 3 1594*4882a593Smuzhiyun #define HDMI_O_1_MASK 0x7 1595*4882a593Smuzhiyun #define HDMI_O_1_MASK_SFT (0x7 << 3) 1596*4882a593Smuzhiyun #define HDMI_O_0_SFT 0 1597*4882a593Smuzhiyun #define HDMI_O_0_MASK 0x7 1598*4882a593Smuzhiyun #define HDMI_O_0_MASK_SFT (0x7 << 0) 1599*4882a593Smuzhiyun 1600*4882a593Smuzhiyun /* AFE_TDM_CON1 */ 1601*4882a593Smuzhiyun #define TDM_EN_SFT 0 1602*4882a593Smuzhiyun #define TDM_EN_MASK 0x1 1603*4882a593Smuzhiyun #define TDM_EN_MASK_SFT (0x1 << 0) 1604*4882a593Smuzhiyun #define LRCK_INVERSE_SFT 2 1605*4882a593Smuzhiyun #define LRCK_INVERSE_MASK 0x1 1606*4882a593Smuzhiyun #define LRCK_INVERSE_MASK_SFT (0x1 << 2) 1607*4882a593Smuzhiyun #define DELAY_DATA_SFT 3 1608*4882a593Smuzhiyun #define DELAY_DATA_MASK 0x1 1609*4882a593Smuzhiyun #define DELAY_DATA_MASK_SFT (0x1 << 3) 1610*4882a593Smuzhiyun #define LEFT_ALIGN_SFT 4 1611*4882a593Smuzhiyun #define LEFT_ALIGN_MASK 0x1 1612*4882a593Smuzhiyun #define LEFT_ALIGN_MASK_SFT (0x1 << 4) 1613*4882a593Smuzhiyun #define WLEN_SFT 8 1614*4882a593Smuzhiyun #define WLEN_MASK 0x3 1615*4882a593Smuzhiyun #define WLEN_MASK_SFT (0x3 << 8) 1616*4882a593Smuzhiyun #define CHANNEL_NUM_SFT 10 1617*4882a593Smuzhiyun #define CHANNEL_NUM_MASK 0x3 1618*4882a593Smuzhiyun #define CHANNEL_NUM_MASK_SFT (0x3 << 10) 1619*4882a593Smuzhiyun #define CHANNEL_BCK_CYCLES_SFT 12 1620*4882a593Smuzhiyun #define CHANNEL_BCK_CYCLES_MASK 0x3 1621*4882a593Smuzhiyun #define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12) 1622*4882a593Smuzhiyun #define DAC_BIT_NUM_SFT 16 1623*4882a593Smuzhiyun #define DAC_BIT_NUM_MASK 0x1f 1624*4882a593Smuzhiyun #define DAC_BIT_NUM_MASK_SFT (0x1f << 16) 1625*4882a593Smuzhiyun #define LRCK_TDM_WIDTH_SFT 24 1626*4882a593Smuzhiyun #define LRCK_TDM_WIDTH_MASK 0xff 1627*4882a593Smuzhiyun #define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24) 1628*4882a593Smuzhiyun 1629*4882a593Smuzhiyun /* AFE_TDM_CON2 */ 1630*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT0_SFT 0 1631*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT0_MASK 0x7 1632*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0) 1633*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT1_SFT 4 1634*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT1_MASK 0x7 1635*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4) 1636*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT2_SFT 8 1637*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT2_MASK 0x7 1638*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8) 1639*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT3_SFT 12 1640*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT3_MASK 0x7 1641*4882a593Smuzhiyun #define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12) 1642*4882a593Smuzhiyun #define TDM_FIX_VALUE_SEL_SFT 16 1643*4882a593Smuzhiyun #define TDM_FIX_VALUE_SEL_MASK 0x1 1644*4882a593Smuzhiyun #define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16) 1645*4882a593Smuzhiyun #define TDM_I2S_LOOPBACK_SFT 20 1646*4882a593Smuzhiyun #define TDM_I2S_LOOPBACK_MASK 0x1 1647*4882a593Smuzhiyun #define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20) 1648*4882a593Smuzhiyun #define TDM_I2S_LOOPBACK_CH_SFT 21 1649*4882a593Smuzhiyun #define TDM_I2S_LOOPBACK_CH_MASK 0x3 1650*4882a593Smuzhiyun #define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21) 1651*4882a593Smuzhiyun #define TDM_FIX_VALUE_SFT 24 1652*4882a593Smuzhiyun #define TDM_FIX_VALUE_MASK 0xff 1653*4882a593Smuzhiyun #define TDM_FIX_VALUE_MASK_SFT (0xff << 24) 1654*4882a593Smuzhiyun 1655*4882a593Smuzhiyun /* AFE_HDMI_OUT_CON0 */ 1656*4882a593Smuzhiyun #define AFE_HDMI_OUT_ON_RETM_SFT 8 1657*4882a593Smuzhiyun #define AFE_HDMI_OUT_ON_RETM_MASK 0x1 1658*4882a593Smuzhiyun #define AFE_HDMI_OUT_ON_RETM_MASK_SFT (0x1 << 8) 1659*4882a593Smuzhiyun #define AFE_HDMI_OUT_CH_NUM_SFT 4 1660*4882a593Smuzhiyun #define AFE_HDMI_OUT_CH_NUM_MASK 0xf 1661*4882a593Smuzhiyun #define AFE_HDMI_OUT_CH_NUM_MASK_SFT (0xf << 4) 1662*4882a593Smuzhiyun #define AFE_HDMI_OUT_BIT_WIDTH_SFT 1 1663*4882a593Smuzhiyun #define AFE_HDMI_OUT_BIT_WIDTH_MASK 0x1 1664*4882a593Smuzhiyun #define AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT (0x1 << 1) 1665*4882a593Smuzhiyun #define AFE_HDMI_OUT_ON_SFT 0 1666*4882a593Smuzhiyun #define AFE_HDMI_OUT_ON_MASK 0x1 1667*4882a593Smuzhiyun #define AFE_HDMI_OUT_ON_MASK_SFT (0x1 << 0) 1668*4882a593Smuzhiyun #endif 1669