1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __REG2_INFO_H__ 3 #define __REG2_INFO_H__ 4 5 #include "rga_drv.h" 6 7 #define RGA2_SYS_REG_BASE 0x000 8 #define RGA2_CSC_REG_BASE 0x060 9 #define RGA2_CMD_REG_BASE 0x100 10 11 /* sys reg */ 12 #define RGA2_SYS_CTRL 0x000 13 #define RGA2_CMD_CTRL 0x004 14 #define RGA2_CMD_BASE 0x008 15 #define RGA2_STATUS1 0x00c 16 #define RGA2_INT 0x010 17 #define RGA2_MMU_CTRL0 0x014 18 #define RGA2_MMU_CMD_BASE 0x018 19 #define RGA2_STATUS2 0x01c 20 #define RGA2_VERSION_NUM 0x028 21 #define RGA2_READ_LINE_CNT 0x030 22 #define RGA2_WRITE_LINE_CNT 0x034 23 #define RGA2_LINE_CNT 0x038 24 #define RGA2_PERF_CTRL0 0x040 25 26 /* full csc reg */ 27 #define RGA2_DST_CSC_00 0x060 28 #define RGA2_DST_CSC_01 0x064 29 #define RGA2_DST_CSC_02 0x068 30 #define RGA2_DST_CSC_OFF0 0x06c 31 #define RGA2_DST_CSC_10 0x070 32 #define RGA2_DST_CSC_11 0x074 33 #define RGA2_DST_CSC_12 0x078 34 #define RGA2_DST_CSC_OFF1 0x07c 35 #define RGA2_DST_CSC_20 0x080 36 #define RGA2_DST_CSC_21 0x084 37 #define RGA2_DST_CSC_22 0x088 38 #define RGA2_DST_CSC_OFF2 0x08c 39 40 /* osd read-back reg */ 41 #define RGA2_OSD_CUR_FLAGS0 0x090 42 #define RGA2_OSD_CUR_FLAGS1 0x09c 43 44 /* mode ctrl */ 45 #define RGA2_MODE_CTRL_OFFSET 0x000 46 #define RGA2_SRC_INFO_OFFSET 0x004 47 #define RGA2_SRC_BASE0_OFFSET 0x008 48 #define RGA2_SRC_BASE1_OFFSET 0x00c 49 #define RGA2_SRC_BASE2_OFFSET 0x010 50 #define RGA2_SRC_BASE3_OFFSET 0x014 51 #define RGA2_SRC_VIR_INFO_OFFSET 0x018 52 #define RGA2_SRC_ACT_INFO_OFFSET 0x01c 53 #define RGA2_SRC_X_FACTOR_OFFSET 0x020 54 #define RGA2_OSD_CTRL0_OFFSET 0x020 // repeat 55 #define RGA2_SRC_Y_FACTOR_OFFSET 0x024 56 #define RGA2_OSD_CTRL1_OFFSET 0x024 // repeat 57 #define RGA2_SRC_BG_COLOR_OFFSET 0x028 58 #define RGA2_OSD_COLOR0_OFFSET 0x028 // repeat 59 #define RGA2_SRC_FG_COLOR_OFFSET 0x02c 60 #define RGA2_OSD_COLOR1_OFFSET 0x02c // repeat 61 #define RGA2_SRC_TR_COLOR0_OFFSET 0x030 62 #define RGA2_CF_GR_A_OFFSET 0x030 // repeat 63 #define RGA2_OSD_LAST_FLAGS0_OFFSET 0x030 // repeat 64 #define RGA2_MOSAIC_MODE_OFFSET 0x030 // repeat 65 #define RGA2_SRC_TR_COLOR1_OFFSET 0x034 66 #define RGA2_CF_GR_B_OFFSET 0x034 // repeat 67 #define RGA2_OSD_LAST_FLAGS1_OFFSET 0x034 // repeat 68 #define RGA2_DST_INFO_OFFSET 0x038 69 #define RGA2_DST_BASE0_OFFSET 0x03c 70 #define RGA2_DST_BASE1_OFFSET 0x040 71 #define RGA2_DST_BASE2_OFFSET 0x044 72 #define RGA2_DST_VIR_INFO_OFFSET 0x048 73 #define RGA2_DST_ACT_INFO_OFFSET 0x04c 74 #define RGA2_ALPHA_CTRL0_OFFSET 0x050 75 #define RGA2_ALPHA_CTRL1_OFFSET 0x054 76 #define RGA2_FADING_CTRL_OFFSET 0x058 77 #define RGA2_PAT_CON_OFFSET 0x05c 78 #define RGA2_ROP_CTRL0_OFFSET 0x060 79 #define RGA2_CF_GR_G_OFFSET 0x060 // repeat 80 #define RGA2_DST_Y4MAP_LUT0_OFFSET 0x060 // repeat 81 #define RGA2_DST_QUANTIZE_SCALE_OFFSET 0x060 // repeat 82 #define RGA2_OSD_INVERTSION_CAL0_OFFSET 0x060 // repeat 83 #define RGA2_ROP_CTRL1_OFFSET 0x064 84 #define RGA2_CF_GR_R_OFFSET 0x064 // repeat 85 #define RGA2_DST_Y4MAP_LUT1_OFFSET 0x064 // repeat 86 #define RGA2_DST_QUANTIZE_OFFSET_OFFSET 0x064 // repeat 87 #define RGA2_OSD_INVERTSION_CAL1_OFFSET 0x064 // repeat 88 #define RGA2_MASK_BASE_OFFSET 0x068 89 #define RGA2_MMU_CTRL1_OFFSET 0x06c 90 #define RGA2_MMU_SRC_BASE_OFFSET 0x070 91 #define RGA2_MMU_SRC1_BASE_OFFSET 0x074 92 #define RGA2_MMU_DST_BASE_OFFSET 0x078 93 #define RGA2_MMU_ELS_BASE_OFFSET 0x07c 94 95 /*RGA_SYS*/ 96 #define m_RGA2_SYS_CTRL_SRC0YUV420SP_RD_OPT_DIS (0x1 << 12) 97 #define m_RGA2_SYS_CTRL_DST_WR_OPT_DIS (0x1 << 11) 98 #define m_RGA2_SYS_CTRL_CMD_CONTINUE_P (0x1 << 10) 99 #define m_RGA2_SYS_CTRL_HOLD_MODE_EN (0x1 << 9) 100 #define m_RGA2_SYS_CTRL_RST_HANDSAVE_P (0x1 << 7) 101 #define m_RGA2_SYS_CTRL_RST_PROTECT_P (0x1 << 6) 102 #define m_RGA2_SYS_CTRL_AUTO_RST (0x1 << 5) 103 #define m_RGA2_SYS_CTRL_CCLK_SRESET_P (0x1 << 4) 104 #define m_RGA2_SYS_CTRL_ACLK_SRESET_P (0x1 << 3) 105 #define m_RGA2_SYS_CTRL_AUTO_CKG (0x1 << 2) 106 #define m_RGA2_SYS_CTRL_CMD_MODE (0x1 << 1) 107 #define m_RGA2_SYS_CTRL_CMD_OP_ST_P (0x1 << 0) 108 109 #define s_RGA2_SYS_CTRL_CMD_CONTINUE(x) ((x & 0x1) << 10) 110 #define s_RGA2_SYS_CTRL_HOLD_MODE_EN(x) ((x & 0x1) << 9) 111 #define s_RGA2_SYS_CTRL_CMD_MODE(x) ((x & 0x1) << 1) 112 113 /* RGA_CMD_CTRL */ 114 #define m_RGA2_CMD_CTRL_INCR_NUM (0x3ff << 3) 115 #define m_RGA2_CMD_CTRL_STOP (0x1 << 2) 116 #define m_RGA2_CMD_CTRL_INCR_VALID_P (0x1 << 1) 117 #define m_RGA2_CMD_CTRL_CMD_LINE_ST_P (0x1 << 0) 118 119 /* RGA_STATUS1 */ 120 #define m_RGA2_STATUS1_SW_CMD_TOTAL_NUM (0xfff << 8) 121 #define m_RGA2_STATUS1_SW_CMD_CUR_NUM (0xfff << 8) 122 #define m_RGA2_STATUS1_SW_RGA_STA (0x1 << 0) 123 124 /*RGA_INT*/ 125 #define m_RGA2_INT_LINE_WR_CLEAR (1 << 16) 126 #define m_RGA2_INT_LINE_RD_CLEAR (1 << 15) 127 #define m_RGA2_INT_LINE_WR_EN (1 << 14) 128 #define m_RGA2_INT_LINE_RD_EN (1 << 13) 129 #define m_RGA2_INT_WRITE_CNT_FLAG (1 << 12) 130 #define m_RGA2_INT_READ_CNT_FLAG (1 << 11) 131 #define m_RGA2_INT_ALL_CMD_DONE_INT_EN (1 << 10) 132 #define m_RGA2_INT_MMU_INT_EN (1 << 9) 133 #define m_RGA2_INT_ERROR_INT_EN (1 << 8) 134 #define m_RGA2_INT_NOW_CMD_DONE_INT_CLEAR (1 << 7) 135 #define m_RGA2_INT_ALL_CMD_DONE_INT_CLEAR (1 << 6) 136 #define m_RGA2_INT_MMU_INT_CLEAR (1 << 5) 137 #define m_RGA2_INT_ERROR_INT_CLEAR (1 << 4) 138 #define m_RGA2_INT_CUR_CMD_DONE_INT_FLAG (1 << 3) 139 #define m_RGA2_INT_ALL_CMD_DONE_INT_FLAG (1 << 2) 140 #define m_RGA2_INT_MMU_INT_FLAG (1 << 1) 141 #define m_RGA2_INT_ERROR_INT_FLAG (1 << 0) 142 143 #define m_RGA2_INT_ERROR_FLAG_MASK \ 144 ( \ 145 m_RGA2_INT_MMU_INT_FLAG | \ 146 m_RGA2_INT_ERROR_INT_FLAG \ 147 ) 148 #define m_RGA2_INT_ERROR_CLEAR_MASK \ 149 ( \ 150 m_RGA2_INT_MMU_INT_CLEAR | \ 151 m_RGA2_INT_ERROR_INT_CLEAR \ 152 ) 153 #define m_RGA2_INT_ERROR_ENABLE_MASK \ 154 ( \ 155 m_RGA2_INT_MMU_INT_EN | \ 156 m_RGA2_INT_ERROR_INT_EN \ 157 ) 158 159 #define s_RGA2_INT_LINE_WR_CLEAR(x) ((x & 0x1) << 16) 160 #define s_RGA2_INT_LINE_RD_CLEAR(x) ((x & 0x1) << 15) 161 #define s_RGA2_INT_LINE_WR_EN(x) ((x & 0x1) << 14) 162 #define s_RGA2_INT_LINE_RD_EN(x) ((x & 0x1) << 13) 163 #define s_RGA2_INT_ALL_CMD_DONE_INT_EN(x) ((x & 0x1) << 10) 164 #define s_RGA2_INT_MMU_INT_EN(x) ((x & 0x1) << 9) 165 #define s_RGA2_INT_ERROR_INT_EN(x) ((x & 0x1) << 8) 166 #define s_RGA2_INT_NOW_CMD_DONE_INT_CLEAR(x) ((x & 0x1) << 7) 167 #define s_RGA2_INT_ALL_CMD_DONE_INT_CLEAR(x) ((x & 0x1) << 6) 168 #define s_RGA2_INT_MMU_INT_CLEAR(x) ((x & 0x1) << 5) 169 #define s_RGA2_INT_ERROR_INT_CLEAR(x) ((x & 0x1) << 4) 170 171 /* RGA_STATUS2 hardware status */ 172 #define m_RGA2_STATUS2_RPP_MKRAM_RREADY (0x2 << 11) 173 #define m_RGA2_STATUS2_DSTRPP_OUTBUF_RREADY (0x1f << 6) 174 #define m_RGA2_STATUS2_SRCRPP_OUTBUF_RREADY (0xf << 2) 175 #define m_RGA2_STATUS2_BUS_ERROR (0x1 << 1) 176 #define m_RGA2_STATUS2_RPP_ERROR (0x1 << 0) 177 178 /* RGA_READ_LINE_CNT_TH */ 179 #define m_RGA2_READ_LINE_SW_INTR_LINE_RD_TH (0x1fff << 0) 180 181 #define s_RGA2_READ_LINE_SW_INTR_LINE_RD_TH(x) ((x & 0x1fff) << 0) 182 183 /* RGA_WRITE_LINE_CNT_TN */ 184 #define m_RGA2_WRITE_LINE_SW_INTR_LINE_WR_START (0x1fff << 0) 185 #define m_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP (0x1fff << 16) 186 187 #define s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_START(x) ((x & 0x1fff) << 0) 188 #define s_RGA2_WRITE_LINE_SW_INTR_LINE_WR_STEP(x) ((x & 0x1fff) << 16) 189 190 /* RGA_MODE_CTRL */ 191 #define m_RGA2_MODE_CTRL_SW_RENDER_MODE (0x7 << 0) 192 #define m_RGA2_MODE_CTRL_SW_BITBLT_MODE (0x1 << 3) 193 #define m_RGA2_MODE_CTRL_SW_CF_ROP4_PAT (0x1 << 4) 194 #define m_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET (0x1 << 5) 195 #define m_RGA2_MODE_CTRL_SW_GRADIENT_SAT (0x1 << 6) 196 #define m_RGA2_MODE_CTRL_SW_INTR_CF_E (0x1 << 7) 197 #define m_RGA2_MODE_CTRL_SW_OSD_E (0x1<<8) 198 #define m_RGA2_MODE_CTRL_SW_MOSAIC_EN (0x1<<9) 199 #define m_RGA2_MODE_CTRL_SW_YIN_YOUT_EN (0x1<<10) 200 201 #define s_RGA2_MODE_CTRL_SW_RENDER_MODE(x) ((x & 0x7) << 0) 202 #define s_RGA2_MODE_CTRL_SW_BITBLT_MODE(x) ((x & 0x1) << 3) 203 #define s_RGA2_MODE_CTRL_SW_CF_ROP4_PAT(x) ((x & 0x1) << 4) 204 #define s_RGA2_MODE_CTRL_SW_ALPHA_ZERO_KET(x) ((x & 0x1) << 5) 205 #define s_RGA2_MODE_CTRL_SW_GRADIENT_SAT(x) ((x & 0x1) << 6) 206 #define s_RGA2_MODE_CTRL_SW_INTR_CF_E(x) ((x & 0x1) << 7) 207 #define s_RGA2_MODE_CTRL_SW_OSD_E(x) ((x & 0x1) << 8) 208 #define s_RGA2_MODE_CTRL_SW_MOSAIC_EN(x) ((x & 0x1) << 9) 209 #define s_RGA2_MODE_CTRL_SW_YIN_YOUT_EN(x) ((x & 0x1) << 10) 210 /* RGA_SRC_INFO */ 211 #define m_RGA2_SRC_INFO_SW_SRC_FMT (0xf << 0) 212 #define m_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP (0x1 << 4) 213 #define m_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP (0x1 << 5) 214 #define m_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP (0x1 << 6) 215 #define m_RGA2_SRC_INFO_SW_SW_CP_ENDIAN (0x1 << 7) 216 #define m_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE (0x3 << 8) 217 #define m_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE (0x3 << 10) 218 #define m_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE (0x3 << 12) 219 #define m_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE (0x3 << 14) 220 #define m_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE (0x3 << 16) 221 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE (0x1 << 18) 222 #define m_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E (0xf << 19) 223 #define m_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E (0x1 << 23) 224 #define m_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER (0x3 << 24) 225 #define m_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL (0x1 << 26) 226 #define m_RGA2_SRC_INFO_SW_SW_YUV10_E (0x1 << 27) 227 #define m_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E (0x1 << 28) 228 229 230 #define s_RGA2_SRC_INFO_SW_SRC_FMT(x) ((x & 0xf) << 0) 231 #define s_RGA2_SRC_INFO_SW_SW_SRC_RB_SWAP(x) ((x & 0x1) << 4) 232 #define s_RGA2_SRC_INFO_SW_SW_SRC_ALPHA_SWAP(x) ((x & 0x1) << 5) 233 #define s_RGA2_SRC_INFO_SW_SW_SRC_UV_SWAP(x) ((x & 0x1) << 6) 234 #define s_RGA2_SRC_INFO_SW_SW_CP_ENDAIN(x) ((x & 0x1) << 7) 235 #define s_RGA2_SRC_INFO_SW_SW_SRC_CSC_MODE(x) ((x & 0x3) << 8) 236 #define s_RGA2_SRC_INFO_SW_SW_SRC_ROT_MODE(x) ((x & 0x3) << 10) 237 #define s_RGA2_SRC_INFO_SW_SW_SRC_MIR_MODE(x) ((x & 0x3) << 12) 238 #define s_RGA2_SRC_INFO_SW_SW_SRC_HSCL_MODE(x) ((x & 0x3) << 14) 239 #define s_RGA2_SRC_INFO_SW_SW_SRC_VSCL_MODE(x) ((x & 0x3) << 16) 240 241 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_MODE(x) ((x & 0x1) << 18) 242 #define s_RGA2_SRC_INFO_SW_SW_SRC_TRANS_E(x) ((x & 0xf) << 19) 243 #define s_RGA2_SRC_INFO_SW_SW_SRC_DITHER_UP_E(x) ((x & 0x1) << 23) 244 #define s_RGA2_SRC_INFO_SW_SW_SRC_SCL_FILTER(x) ((x & 0x3) << 24) 245 #define s_RGA2_SRC_INFO_SW_SW_VSP_MODE_SEL(x) ((x & 0x1) << 26) 246 #define s_RGA2_SRC_INFO_SW_SW_YUV10_E(x) ((x & 0x1) << 27) 247 #define s_RGA2_SRC_INFO_SW_SW_YUV10_ROUND_E(x) ((x & 0x1) << 28) 248 249 /* RGA_SRC_VIR_INFO */ 250 #define m_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE (0x7fff << 0) 251 #define m_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE (0x3ff << 16) 252 253 #define s_RGA2_SRC_VIR_INFO_SW_SRC_VIR_STRIDE(x) ((x & 0x7fff) << 0) 254 #define s_RGA2_SRC_VIR_INFO_SW_MASK_VIR_STRIDE(x) ((x & 0x3ff) << 16) 255 256 257 /* RGA_SRC_ACT_INFO */ 258 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH (0x1fff << 0) 259 #define m_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT (0x1fff << 16) 260 261 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_WIDTH(x) ((x & 0x1fff) << 0) 262 #define s_RGA2_SRC_ACT_INFO_SW_SRC_ACT_HEIGHT(x) ((x & 0x1fff) << 16) 263 264 /* RGA2_OSD_CTRL0 */ 265 #define m_RGA2_OSD_CTRL0_SW_OSD_MODE (0x3 << 0) 266 #define m_RGA2_OSD_CTRL0_SW_OSD_VER_MODE (0x1 << 2) 267 #define m_RGA2_OSD_CTRL0_SW_OSD_WIDTH_MODE (0x1 << 3) 268 #define m_RGA2_OSD_CTRL0_SW_OSD_BLK_NUM (0x1f << 4) 269 #define m_RGA2_OSD_CTRL0_SW_OSD_FLAGS_INDEX (0x3f << 10) 270 #define m_RGA2_OSD_CTRL0_SW_OSD_FIX_WIDTH (0x3f << 20) 271 #define m_RGA2_OSD_CTRL0_SW_OSD_2BPP_MODE (0x1 << 30) 272 273 #define s_RGA2_OSD_CTRL0_SW_OSD_MODE(x) ((x & 0x3) << 0) 274 #define s_RGA2_OSD_CTRL0_SW_OSD_VER_MODE(x) ((x & 0x1) << 2) 275 #define s_RGA2_OSD_CTRL0_SW_OSD_WIDTH_MODE(x) ((x & 0x1) << 3) 276 #define s_RGA2_OSD_CTRL0_SW_OSD_BLK_NUM(x) ((x & 0x1f) << 4) 277 #define s_RGA2_OSD_CTRL0_SW_OSD_FLAGS_INDEX(x) ((x & 0x3ff) << 10) 278 #define s_RGA2_OSD_CTRL0_SW_OSD_FIX_WIDTH(x) ((x & 0x3ff) << 20) 279 #define s_RGA2_OSD_CTRL0_SW_OSD_2BPP_MODE(x) ((x & 0x1) << 30) 280 281 /* RGA2_OSD_CTRL1 */ 282 #define m_RGA2_OSD_CTRL1_SW_OSD_COLOR_SEL (0x1 << 0) 283 #define m_RGA2_OSD_CTRL1_SW_OSD_FLAG_SEL (0x1 << 1) 284 #define m_RGA2_OSD_CTRL1_SW_OSD_DEFAULT_COLOR (0x1 << 2) 285 #define m_RGA2_OSD_CTRL1_SW_OSD_AUTO_INVERST_MODE (0x1 << 3) 286 #define m_RGA2_OSD_CTRL1_SW_OSD_THRESH (0xff << 4) 287 #define m_RGA2_OSD_CTRL1_SW_OSD_INVERT_A_EN (0x1 << 12) 288 #define m_RGA2_OSD_CTRL1_SW_OSD_INVERT_Y_DIS (0x1 << 13) 289 #define m_RGA2_OSD_CTRL1_SW_OSD_INVERT_C_DIS (0x1 << 14) 290 #define m_RGA2_OSD_CTRL1_SW_OSD_UNFIX_INDEX (0xf << 16) 291 292 #define s_RGA2_OSD_CTRL1_SW_OSD_COLOR_SEL(x) ((x & 0x1) << 0) 293 #define s_RGA2_OSD_CTRL1_SW_OSD_FLAG_SEL(x) ((x & 0x1) << 1) 294 #define s_RGA2_OSD_CTRL1_SW_OSD_DEFAULT_COLOR(x) ((x & 0x1) << 2) 295 #define s_RGA2_OSD_CTRL1_SW_OSD_AUTO_INVERST_MODE(x) ((x & 0x1) << 3) 296 #define s_RGA2_OSD_CTRL1_SW_OSD_THRESH(x) ((x & 0xff) << 4) 297 #define s_RGA2_OSD_CTRL1_SW_OSD_INVERT_A_EN(x) ((x & 0x1) << 12) 298 #define s_RGA2_OSD_CTRL1_SW_OSD_INVERT_Y_DIS(x) ((x & 0x1) << 13) 299 #define s_RGA2_OSD_CTRL1_SW_OSD_INVERT_C_DIS(x) ((x & 0x1) << 14) 300 #define s_RGA2_OSD_CTRL1_SW_OSD_UNFIX_INDEX(x) ((x & 0xf) << 16) 301 302 /* RGA_DST_INFO */ 303 #define m_RGA2_DST_INFO_SW_DST_FMT (0xf << 0) 304 #define m_RGA2_DST_INFO_SW_DST_RB_SWAP (0x1 << 4) 305 #define m_RGA2_DST_INFO_SW_ALPHA_SWAP (0x1 << 5) 306 #define m_RGA2_DST_INFO_SW_DST_UV_SWAP (0x1 << 6) 307 #define m_RGA2_DST_INFO_SW_SRC1_FMT (0x7 << 7) 308 #define m_RGA2_DST_INFO_SW_SRC1_RB_SWP (0x1 << 10) 309 #define m_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP (0x1 << 11) 310 #define m_RGA2_DST_INFO_SW_DITHER_UP_E (0x1 << 12) 311 #define m_RGA2_DST_INFO_SW_DITHER_DOWN_E (0x1 << 13) 312 #define m_RGA2_DST_INFO_SW_DITHER_MODE (0x3 << 14) 313 #define m_RGA2_DST_INFO_SW_DST_CSC_MODE (0x3 << 16) 314 #define m_RGA2_DST_INFO_SW_CSC_CLIP_MODE (0x1 << 18) 315 #define m_RGA2_DST_INFO_SW_DST_CSC_MODE_2 (0x1 << 19) 316 #define m_RGA2_DST_INFO_SW_SRC1_CSC_MODE (0x3 << 20) 317 #define m_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE (0x1 << 22) 318 #define m_RGA2_DST_INFO_SW_DST_UVHDS_MODE (0x1 << 23) 319 #define m_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN (0x1 << 24) 320 #define m_RGA2_DST_INFO_SW_DST_FMT_Y4_EN (0x1 << 25) 321 #define m_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN (0x1 << 26) 322 #define m_RGA2_DST_INFO_SW_DST_UVVDS_MODE (0x1 << 27) 323 324 #define s_RGA2_DST_INFO_SW_DST_FMT(x) ((x & 0xf) << 0) 325 #define s_RGA2_DST_INFO_SW_DST_RB_SWAP(x) ((x & 0x1) << 4) 326 #define s_RGA2_DST_INFO_SW_ALPHA_SWAP(x) ((x & 0x1) << 5) 327 #define s_RGA2_DST_INFO_SW_DST_UV_SWAP(x) ((x & 0x1) << 6) 328 #define s_RGA2_DST_INFO_SW_SRC1_FMT(x) ((x & 0x7) << 7) 329 #define s_RGA2_DST_INFO_SW_SRC1_RB_SWP(x) ((x & 0x1) << 10) 330 #define s_RGA2_DST_INFO_SW_SRC1_ALPHA_SWP(x) ((x & 0x1) << 11) 331 #define s_RGA2_DST_INFO_SW_DITHER_UP_E(x) ((x & 0x1) << 12) 332 #define s_RGA2_DST_INFO_SW_DITHER_DOWN_E(x) ((x & 0x1) << 13) 333 #define s_RGA2_DST_INFO_SW_DITHER_MODE(x) ((x & 0x3) << 14) 334 #define s_RGA2_DST_INFO_SW_DST_CSC_MODE(x) ((x & 0x3) << 16) 335 #define s_RGA2_DST_INFO_SW_CSC_CLIP_MODE(x) ((x & 0x1) << 18) 336 #define s_RGA2_DST_INFO_SW_DST_CSC_MODE_2(x) ((x & 0x1) << 19) 337 #define s_RGA2_DST_INFO_SW_SRC1_CSC_MODE(x) ((x & 0x3) << 20) 338 #define s_RGA2_DST_INFO_SW_SRC1_CSC_CLIP_MODE(x) ((x & 0x1) << 22) 339 #define s_RGA2_DST_INFO_SW_DST_UVHDS_MODE(x) ((x & 0x1) << 23) 340 #define s_RGA2_DST_INFO_SW_DST_FMT_YUV400_EN(x) ((x & 0x1) << 24) 341 #define s_RGA2_DST_INFO_SW_DST_FMT_Y4_EN(x) ((x & 0x1) << 25) 342 #define s_RGA2_DST_INFO_SW_DST_NN_QUANTIZE_EN(x) ((x & 0x1) << 26) 343 #define s_RGA2_DST_INFO_SW_DST_UVVDS_MODE(x) ((x & 0x1) << 27) 344 345 346 /* RGA_ALPHA_CTRL0 */ 347 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0 (0x1 << 0) 348 #define m_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL (0x1 << 1) 349 #define m_RGA2_ALPHA_CTRL0_SW_ROP_MODE (0x3 << 2) 350 #define m_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA (0xff << 4) 351 #define m_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA (0xff << 12) 352 #define m_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN (0x1 << 20) 353 354 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_0(x) ((x & 0x1) << 0) 355 #define s_RGA2_ALPHA_CTRL0_SW_ALPHA_ROP_SEL(x) ((x & 0x1) << 1) 356 #define s_RGA2_ALPHA_CTRL0_SW_ROP_MODE(x) ((x & 0x3) << 2) 357 #define s_RGA2_ALPHA_CTRL0_SW_SRC_GLOBAL_ALPHA(x) ((x & 0xff) << 4) 358 #define s_RGA2_ALPHA_CTRL0_SW_DST_GLOBAL_ALPHA(x) ((x & 0xff) << 12) 359 #define s_RGA2_ALPHA_CTRLO_SW_MASK_ENDIAN(x) ((x & 0x1) << 20) 360 361 362 363 /* RGA_ALPHA_CTRL1 */ 364 #define m_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0 (0x1 << 0) 365 #define m_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0 (0x1 << 1) 366 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0 (0x7 << 2) 367 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0 (0x7 << 5) 368 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0 (0x1 << 8) 369 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0 (0x1 << 9) 370 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0 (0x3 << 10) 371 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0 (0x3 << 12) 372 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0 (0x1 << 14) 373 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0 (0x1 << 15) 374 #define m_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1 (0x7 << 16) 375 #define m_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1 (0x7 << 19) 376 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1 (0x1 << 22) 377 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1 (0x1 << 23) 378 #define m_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1 (0x3 << 24) 379 #define m_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1 (0x3 << 26) 380 #define m_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1 (0x1 << 28) 381 #define m_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1 (0x1 << 29) 382 383 #define s_RGA2_ALPHA_CTRL1_SW_DST_COLOR_M0(x) ((x & 0x1) << 0) 384 #define s_RGA2_ALPHA_CTRL1_SW_SRC_COLOR_M0(x) ((x & 0x1) << 1) 385 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M0(x) ((x & 0x7) << 2) 386 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M0(x) ((x & 0x7) << 5) 387 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M0(x) ((x & 0x1) << 8) 388 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M0(x) ((x & 0x1) << 9) 389 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M0(x) ((x & 0x3) << 10) 390 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M0(x) ((x & 0x3) << 12) 391 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M0(x) ((x & 0x1) << 14) 392 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M0(x) ((x & 0x1) << 15) 393 #define s_RGA2_ALPHA_CTRL1_SW_DST_FACTOR_M1(x) ((x & 0x7) << 16) 394 #define s_RGA2_ALPHA_CTRL1_SW_SRC_FACTOR_M1(x) ((x & 0x7) << 19) 395 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_CAL_M1(x) ((x & 0x1) << 22) 396 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_CAL_M1(x) ((x & 0x1) << 23) 397 #define s_RGA2_ALPHA_CTRL1_SW_DST_BLEND_M1(x) ((x & 0x3) << 24) 398 #define s_RGA2_ALPHA_CTRL1_SW_SRC_BLEND_M1(x) ((x & 0x3) << 26) 399 #define s_RGA2_ALPHA_CTRL1_SW_DST_ALPHA_M1(x) ((x & 0x1) << 28) 400 #define s_RGA2_ALPHA_CTRL1_SW_SRC_ALPHA_M1(x) ((x & 0x1) << 29) 401 402 403 404 /* RGA_MMU_CTRL1 */ 405 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_EN (0x1 << 0) 406 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH (0x1 << 1) 407 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN (0x1 << 2) 408 #define m_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR (0x1 << 3) 409 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN (0x1 << 4) 410 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH (0x1 << 5) 411 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN (0x1 << 6) 412 #define m_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR (0x1 << 7) 413 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_EN (0x1 << 8) 414 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH (0x1 << 9) 415 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN (0x1 << 10) 416 #define m_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR (0x1 << 11) 417 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_EN (0x1 << 12) 418 #define m_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH (0x1 << 13) 419 420 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_EN(x) ((x & 0x1) << 0) 421 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_FLUSH(x) ((x & 0x1) << 1) 422 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_EN(x) ((x & 0x1) << 2) 423 #define s_RGA2_MMU_CTRL1_SW_SRC_MMU_PREFETCH_DIR(x) ((x & 0x1) << 3) 424 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_EN(x) ((x & 0x1) << 4) 425 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_FLUSH(x) ((x & 0x1) << 5) 426 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_EN(x) ((x & 0x1) << 6) 427 #define s_RGA2_MMU_CTRL1_SW_SRC1_MMU_PREFETCH_DIR(x) ((x & 0x1) << 7) 428 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_EN(x) ((x & 0x1) << 8) 429 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_FLUSH(x) ((x & 0x1) << 9) 430 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_EN(x) ((x & 0x1) << 10) 431 #define s_RGA2_MMU_CTRL1_SW_DST_MMU_PREFETCH_DIR(x) ((x & 0x1) << 11) 432 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_EN(x) ((x & 0x1) << 12) 433 #define s_RGA2_MMU_CTRL1_SW_ELS_MMU_FLUSH(x) ((x & 0x1) << 13) 434 435 #define RGA2_VSP_BICUBIC_LIMIT 1996 436 437 union rga2_color_ctrl { 438 uint32_t value; 439 struct { 440 uint32_t dst_color_mode:1; 441 uint32_t src_color_mode:1; 442 443 uint32_t dst_factor_mode:3; 444 uint32_t src_factor_mode:3; 445 446 uint32_t dst_alpha_cal_mode:1; 447 uint32_t src_alpha_cal_mode:1; 448 449 uint32_t dst_blend_mode:2; 450 uint32_t src_blend_mode:2; 451 452 uint32_t dst_alpha_mode:1; 453 uint32_t src_alpha_mode:1; 454 } bits; 455 }; 456 457 union rga2_alpha_ctrl { 458 uint32_t value; 459 struct { 460 uint32_t dst_factor_mode:3; 461 uint32_t src_factor_mode:3; 462 463 uint32_t dst_alpha_cal_mode:1; 464 uint32_t src_alpha_cal_mode:1; 465 466 uint32_t dst_blend_mode:2; 467 uint32_t src_blend_mode:2; 468 469 uint32_t dst_alpha_mode:1; 470 uint32_t src_alpha_mode:1; 471 } bits; 472 }; 473 474 extern const struct rga_backend_ops rga2_ops; 475 476 #endif 477 478