1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc. 4*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 7*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 8*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 9*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 11*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 14*4882a593Smuzhiyun * all copies or substantial portions of the Software. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Authors: Dave Airlie 25*4882a593Smuzhiyun * Alex Deucher 26*4882a593Smuzhiyun * Jerome Glisse 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #ifndef __R100D_H__ 29*4882a593Smuzhiyun #define __R100D_H__ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define CP_PACKET0 0x00000000 32*4882a593Smuzhiyun #define PACKET0_BASE_INDEX_SHIFT 0 33*4882a593Smuzhiyun #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) 34*4882a593Smuzhiyun #define PACKET0_COUNT_SHIFT 16 35*4882a593Smuzhiyun #define PACKET0_COUNT_MASK (0x3fff << 16) 36*4882a593Smuzhiyun #define CP_PACKET1 0x40000000 37*4882a593Smuzhiyun #define CP_PACKET2 0x80000000 38*4882a593Smuzhiyun #define PACKET2_PAD_SHIFT 0 39*4882a593Smuzhiyun #define PACKET2_PAD_MASK (0x3fffffff << 0) 40*4882a593Smuzhiyun #define CP_PACKET3 0xC0000000 41*4882a593Smuzhiyun #define PACKET3_IT_OPCODE_SHIFT 8 42*4882a593Smuzhiyun #define PACKET3_IT_OPCODE_MASK (0xff << 8) 43*4882a593Smuzhiyun #define PACKET3_COUNT_SHIFT 16 44*4882a593Smuzhiyun #define PACKET3_COUNT_MASK (0x3fff << 16) 45*4882a593Smuzhiyun /* PACKET3 op code */ 46*4882a593Smuzhiyun #define PACKET3_NOP 0x10 47*4882a593Smuzhiyun #define PACKET3_3D_DRAW_VBUF 0x28 48*4882a593Smuzhiyun #define PACKET3_3D_DRAW_IMMD 0x29 49*4882a593Smuzhiyun #define PACKET3_3D_DRAW_INDX 0x2A 50*4882a593Smuzhiyun #define PACKET3_3D_LOAD_VBPNTR 0x2F 51*4882a593Smuzhiyun #define PACKET3_3D_CLEAR_ZMASK 0x32 52*4882a593Smuzhiyun #define PACKET3_INDX_BUFFER 0x33 53*4882a593Smuzhiyun #define PACKET3_3D_DRAW_VBUF_2 0x34 54*4882a593Smuzhiyun #define PACKET3_3D_DRAW_IMMD_2 0x35 55*4882a593Smuzhiyun #define PACKET3_3D_DRAW_INDX_2 0x36 56*4882a593Smuzhiyun #define PACKET3_3D_CLEAR_HIZ 0x37 57*4882a593Smuzhiyun #define PACKET3_BITBLT_MULTI 0x9B 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define PACKET0(reg, n) (CP_PACKET0 | \ 60*4882a593Smuzhiyun REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ 61*4882a593Smuzhiyun REG_SET(PACKET0_COUNT, (n))) 62*4882a593Smuzhiyun #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 63*4882a593Smuzhiyun #define PACKET3(op, n) (CP_PACKET3 | \ 64*4882a593Smuzhiyun REG_SET(PACKET3_IT_OPCODE, (op)) | \ 65*4882a593Smuzhiyun REG_SET(PACKET3_COUNT, (n))) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Registers */ 68*4882a593Smuzhiyun #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 69*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 70*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 71*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 72*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 73*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 74*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 75*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 76*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 77*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB 78*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 79*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 80*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 81*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 82*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 83*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 84*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 85*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 86*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 87*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 88*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 89*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 90*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 91*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 92*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 93*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 94*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 95*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 96*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 97*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 98*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 99*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 100*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 101*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 102*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 103*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 104*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 105*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 106*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 107*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 108*4882a593Smuzhiyun #define R_000030_BUS_CNTL 0x000030 109*4882a593Smuzhiyun #define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0) 110*4882a593Smuzhiyun #define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1) 111*4882a593Smuzhiyun #define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE 112*4882a593Smuzhiyun #define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1) 113*4882a593Smuzhiyun #define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1) 114*4882a593Smuzhiyun #define C_000030_BUS_MSTR_RESET 0xFFFFFFFD 115*4882a593Smuzhiyun #define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2) 116*4882a593Smuzhiyun #define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1) 117*4882a593Smuzhiyun #define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB 118*4882a593Smuzhiyun #define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3) 119*4882a593Smuzhiyun #define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1) 120*4882a593Smuzhiyun #define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7 121*4882a593Smuzhiyun #define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4) 122*4882a593Smuzhiyun #define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1) 123*4882a593Smuzhiyun #define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF 124*4882a593Smuzhiyun #define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5) 125*4882a593Smuzhiyun #define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1) 126*4882a593Smuzhiyun #define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF 127*4882a593Smuzhiyun #define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6) 128*4882a593Smuzhiyun #define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1) 129*4882a593Smuzhiyun #define C_000030_BUS_MASTER_DIS 0xFFFFFFBF 130*4882a593Smuzhiyun #define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7) 131*4882a593Smuzhiyun #define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1) 132*4882a593Smuzhiyun #define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F 133*4882a593Smuzhiyun #define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8) 134*4882a593Smuzhiyun #define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1) 135*4882a593Smuzhiyun #define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF 136*4882a593Smuzhiyun #define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9) 137*4882a593Smuzhiyun #define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1) 138*4882a593Smuzhiyun #define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF 139*4882a593Smuzhiyun #define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10) 140*4882a593Smuzhiyun #define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1) 141*4882a593Smuzhiyun #define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF 142*4882a593Smuzhiyun #define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11) 143*4882a593Smuzhiyun #define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1) 144*4882a593Smuzhiyun #define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF 145*4882a593Smuzhiyun #define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12) 146*4882a593Smuzhiyun #define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1) 147*4882a593Smuzhiyun #define C_000030_BIOS_DIS_ROM 0xFFFFEFFF 148*4882a593Smuzhiyun #define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13) 149*4882a593Smuzhiyun #define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1) 150*4882a593Smuzhiyun #define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF 151*4882a593Smuzhiyun #define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14) 152*4882a593Smuzhiyun #define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1) 153*4882a593Smuzhiyun #define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF 154*4882a593Smuzhiyun #define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15) 155*4882a593Smuzhiyun #define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1) 156*4882a593Smuzhiyun #define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF 157*4882a593Smuzhiyun #define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16) 158*4882a593Smuzhiyun #define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF) 159*4882a593Smuzhiyun #define C_000030_BUS_RETRY_WS 0xFFF0FFFF 160*4882a593Smuzhiyun #define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20) 161*4882a593Smuzhiyun #define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1) 162*4882a593Smuzhiyun #define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF 163*4882a593Smuzhiyun #define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21) 164*4882a593Smuzhiyun #define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1) 165*4882a593Smuzhiyun #define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF 166*4882a593Smuzhiyun #define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22) 167*4882a593Smuzhiyun #define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1) 168*4882a593Smuzhiyun #define C_000030_BUS_SUSPEND 0xFFBFFFFF 169*4882a593Smuzhiyun #define S_000030_LAT_16X(x) (((x) & 0x1) << 23) 170*4882a593Smuzhiyun #define G_000030_LAT_16X(x) (((x) >> 23) & 0x1) 171*4882a593Smuzhiyun #define C_000030_LAT_16X 0xFF7FFFFF 172*4882a593Smuzhiyun #define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24) 173*4882a593Smuzhiyun #define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1) 174*4882a593Smuzhiyun #define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF 175*4882a593Smuzhiyun #define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25) 176*4882a593Smuzhiyun #define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1) 177*4882a593Smuzhiyun #define C_000030_ENFRCWRDY 0xFDFFFFFF 178*4882a593Smuzhiyun #define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26) 179*4882a593Smuzhiyun #define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1) 180*4882a593Smuzhiyun #define C_000030_BUS_MSTR_WS 0xFBFFFFFF 181*4882a593Smuzhiyun #define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27) 182*4882a593Smuzhiyun #define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1) 183*4882a593Smuzhiyun #define C_000030_BUS_PARKING_DIS 0xF7FFFFFF 184*4882a593Smuzhiyun #define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28) 185*4882a593Smuzhiyun #define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1) 186*4882a593Smuzhiyun #define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF 187*4882a593Smuzhiyun #define S_000030_SERR_EN(x) (((x) & 0x1) << 29) 188*4882a593Smuzhiyun #define G_000030_SERR_EN(x) (((x) >> 29) & 0x1) 189*4882a593Smuzhiyun #define C_000030_SERR_EN 0xDFFFFFFF 190*4882a593Smuzhiyun #define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30) 191*4882a593Smuzhiyun #define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1) 192*4882a593Smuzhiyun #define C_000030_BUS_READ_BURST 0xBFFFFFFF 193*4882a593Smuzhiyun #define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31) 194*4882a593Smuzhiyun #define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1) 195*4882a593Smuzhiyun #define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF 196*4882a593Smuzhiyun #define R_000040_GEN_INT_CNTL 0x000040 197*4882a593Smuzhiyun #define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0) 198*4882a593Smuzhiyun #define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1) 199*4882a593Smuzhiyun #define C_000040_CRTC_VBLANK 0xFFFFFFFE 200*4882a593Smuzhiyun #define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1) 201*4882a593Smuzhiyun #define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1) 202*4882a593Smuzhiyun #define C_000040_CRTC_VLINE 0xFFFFFFFD 203*4882a593Smuzhiyun #define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2) 204*4882a593Smuzhiyun #define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1) 205*4882a593Smuzhiyun #define C_000040_CRTC_VSYNC 0xFFFFFFFB 206*4882a593Smuzhiyun #define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3) 207*4882a593Smuzhiyun #define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1) 208*4882a593Smuzhiyun #define C_000040_SNAPSHOT 0xFFFFFFF7 209*4882a593Smuzhiyun #define S_000040_FP_DETECT(x) (((x) & 0x1) << 4) 210*4882a593Smuzhiyun #define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1) 211*4882a593Smuzhiyun #define C_000040_FP_DETECT 0xFFFFFFEF 212*4882a593Smuzhiyun #define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5) 213*4882a593Smuzhiyun #define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1) 214*4882a593Smuzhiyun #define C_000040_CRTC2_VLINE 0xFFFFFFDF 215*4882a593Smuzhiyun #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12) 216*4882a593Smuzhiyun #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1) 217*4882a593Smuzhiyun #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF 218*4882a593Smuzhiyun #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6) 219*4882a593Smuzhiyun #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1) 220*4882a593Smuzhiyun #define C_000040_CRTC2_VSYNC 0xFFFFFFBF 221*4882a593Smuzhiyun #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7) 222*4882a593Smuzhiyun #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1) 223*4882a593Smuzhiyun #define C_000040_SNAPSHOT2 0xFFFFFF7F 224*4882a593Smuzhiyun #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9) 225*4882a593Smuzhiyun #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1) 226*4882a593Smuzhiyun #define C_000040_CRTC2_VBLANK 0xFFFFFDFF 227*4882a593Smuzhiyun #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10) 228*4882a593Smuzhiyun #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1) 229*4882a593Smuzhiyun #define C_000040_FP2_DETECT 0xFFFFFBFF 230*4882a593Smuzhiyun #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11) 231*4882a593Smuzhiyun #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1) 232*4882a593Smuzhiyun #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF 233*4882a593Smuzhiyun #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 234*4882a593Smuzhiyun #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 235*4882a593Smuzhiyun #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 236*4882a593Smuzhiyun #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 237*4882a593Smuzhiyun #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 238*4882a593Smuzhiyun #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 239*4882a593Smuzhiyun #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 240*4882a593Smuzhiyun #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 241*4882a593Smuzhiyun #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 242*4882a593Smuzhiyun #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 243*4882a593Smuzhiyun #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 244*4882a593Smuzhiyun #define C_000040_I2C_INT_EN 0xFFFDFFFF 245*4882a593Smuzhiyun #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 246*4882a593Smuzhiyun #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 247*4882a593Smuzhiyun #define C_000040_GUI_IDLE 0xFFF7FFFF 248*4882a593Smuzhiyun #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 249*4882a593Smuzhiyun #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 250*4882a593Smuzhiyun #define C_000040_VIPH_INT_EN 0xFEFFFFFF 251*4882a593Smuzhiyun #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 252*4882a593Smuzhiyun #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 253*4882a593Smuzhiyun #define C_000040_SW_INT_EN 0xFDFFFFFF 254*4882a593Smuzhiyun #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 255*4882a593Smuzhiyun #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 256*4882a593Smuzhiyun #define C_000040_GEYSERVILLE 0xF7FFFFFF 257*4882a593Smuzhiyun #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 258*4882a593Smuzhiyun #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 259*4882a593Smuzhiyun #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 260*4882a593Smuzhiyun #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 261*4882a593Smuzhiyun #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 262*4882a593Smuzhiyun #define C_000040_DVI_I2C_INT 0xDFFFFFFF 263*4882a593Smuzhiyun #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 264*4882a593Smuzhiyun #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 265*4882a593Smuzhiyun #define C_000040_GUIDMA 0xBFFFFFFF 266*4882a593Smuzhiyun #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 267*4882a593Smuzhiyun #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 268*4882a593Smuzhiyun #define C_000040_VIDDMA 0x7FFFFFFF 269*4882a593Smuzhiyun #define R_000044_GEN_INT_STATUS 0x000044 270*4882a593Smuzhiyun #define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0) 271*4882a593Smuzhiyun #define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1) 272*4882a593Smuzhiyun #define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE 273*4882a593Smuzhiyun #define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0) 274*4882a593Smuzhiyun #define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1) 275*4882a593Smuzhiyun #define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE 276*4882a593Smuzhiyun #define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1) 277*4882a593Smuzhiyun #define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1) 278*4882a593Smuzhiyun #define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD 279*4882a593Smuzhiyun #define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1) 280*4882a593Smuzhiyun #define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1) 281*4882a593Smuzhiyun #define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD 282*4882a593Smuzhiyun #define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2) 283*4882a593Smuzhiyun #define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1) 284*4882a593Smuzhiyun #define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB 285*4882a593Smuzhiyun #define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2) 286*4882a593Smuzhiyun #define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1) 287*4882a593Smuzhiyun #define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB 288*4882a593Smuzhiyun #define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3) 289*4882a593Smuzhiyun #define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1) 290*4882a593Smuzhiyun #define C_000044_SNAPSHOT_STAT 0xFFFFFFF7 291*4882a593Smuzhiyun #define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3) 292*4882a593Smuzhiyun #define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1) 293*4882a593Smuzhiyun #define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7 294*4882a593Smuzhiyun #define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4) 295*4882a593Smuzhiyun #define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1) 296*4882a593Smuzhiyun #define C_000044_FP_DETECT_STAT 0xFFFFFFEF 297*4882a593Smuzhiyun #define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4) 298*4882a593Smuzhiyun #define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1) 299*4882a593Smuzhiyun #define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF 300*4882a593Smuzhiyun #define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5) 301*4882a593Smuzhiyun #define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1) 302*4882a593Smuzhiyun #define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF 303*4882a593Smuzhiyun #define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5) 304*4882a593Smuzhiyun #define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1) 305*4882a593Smuzhiyun #define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF 306*4882a593Smuzhiyun #define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6) 307*4882a593Smuzhiyun #define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1) 308*4882a593Smuzhiyun #define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF 309*4882a593Smuzhiyun #define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6) 310*4882a593Smuzhiyun #define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1) 311*4882a593Smuzhiyun #define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF 312*4882a593Smuzhiyun #define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7) 313*4882a593Smuzhiyun #define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1) 314*4882a593Smuzhiyun #define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F 315*4882a593Smuzhiyun #define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7) 316*4882a593Smuzhiyun #define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1) 317*4882a593Smuzhiyun #define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F 318*4882a593Smuzhiyun #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 319*4882a593Smuzhiyun #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 320*4882a593Smuzhiyun #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 321*4882a593Smuzhiyun #define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9) 322*4882a593Smuzhiyun #define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1) 323*4882a593Smuzhiyun #define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF 324*4882a593Smuzhiyun #define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9) 325*4882a593Smuzhiyun #define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1) 326*4882a593Smuzhiyun #define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF 327*4882a593Smuzhiyun #define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10) 328*4882a593Smuzhiyun #define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1) 329*4882a593Smuzhiyun #define C_000044_FP2_DETECT_STAT 0xFFFFFBFF 330*4882a593Smuzhiyun #define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10) 331*4882a593Smuzhiyun #define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1) 332*4882a593Smuzhiyun #define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF 333*4882a593Smuzhiyun #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11) 334*4882a593Smuzhiyun #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1) 335*4882a593Smuzhiyun #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF 336*4882a593Smuzhiyun #define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11) 337*4882a593Smuzhiyun #define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1) 338*4882a593Smuzhiyun #define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF 339*4882a593Smuzhiyun #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 340*4882a593Smuzhiyun #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 341*4882a593Smuzhiyun #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 342*4882a593Smuzhiyun #define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12) 343*4882a593Smuzhiyun #define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1) 344*4882a593Smuzhiyun #define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF 345*4882a593Smuzhiyun #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 346*4882a593Smuzhiyun #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 347*4882a593Smuzhiyun #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 348*4882a593Smuzhiyun #define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13) 349*4882a593Smuzhiyun #define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1) 350*4882a593Smuzhiyun #define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF 351*4882a593Smuzhiyun #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 352*4882a593Smuzhiyun #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 353*4882a593Smuzhiyun #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 354*4882a593Smuzhiyun #define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14) 355*4882a593Smuzhiyun #define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1) 356*4882a593Smuzhiyun #define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF 357*4882a593Smuzhiyun #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 358*4882a593Smuzhiyun #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 359*4882a593Smuzhiyun #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 360*4882a593Smuzhiyun #define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15) 361*4882a593Smuzhiyun #define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1) 362*4882a593Smuzhiyun #define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF 363*4882a593Smuzhiyun #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 364*4882a593Smuzhiyun #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 365*4882a593Smuzhiyun #define C_000044_I2C_INT 0xFFFDFFFF 366*4882a593Smuzhiyun #define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17) 367*4882a593Smuzhiyun #define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1) 368*4882a593Smuzhiyun #define C_000044_I2C_INT_AK 0xFFFDFFFF 369*4882a593Smuzhiyun #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 370*4882a593Smuzhiyun #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 371*4882a593Smuzhiyun #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 372*4882a593Smuzhiyun #define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19) 373*4882a593Smuzhiyun #define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1) 374*4882a593Smuzhiyun #define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF 375*4882a593Smuzhiyun #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 376*4882a593Smuzhiyun #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 377*4882a593Smuzhiyun #define C_000044_VIPH_INT 0xFEFFFFFF 378*4882a593Smuzhiyun #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 379*4882a593Smuzhiyun #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 380*4882a593Smuzhiyun #define C_000044_SW_INT 0xFDFFFFFF 381*4882a593Smuzhiyun #define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25) 382*4882a593Smuzhiyun #define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1) 383*4882a593Smuzhiyun #define C_000044_SW_INT_AK 0xFDFFFFFF 384*4882a593Smuzhiyun #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 385*4882a593Smuzhiyun #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 386*4882a593Smuzhiyun #define C_000044_SW_INT_SET 0xFBFFFFFF 387*4882a593Smuzhiyun #define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27) 388*4882a593Smuzhiyun #define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1) 389*4882a593Smuzhiyun #define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF 390*4882a593Smuzhiyun #define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27) 391*4882a593Smuzhiyun #define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1) 392*4882a593Smuzhiyun #define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF 393*4882a593Smuzhiyun #define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28) 394*4882a593Smuzhiyun #define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1) 395*4882a593Smuzhiyun #define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF 396*4882a593Smuzhiyun #define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28) 397*4882a593Smuzhiyun #define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1) 398*4882a593Smuzhiyun #define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF 399*4882a593Smuzhiyun #define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29) 400*4882a593Smuzhiyun #define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1) 401*4882a593Smuzhiyun #define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF 402*4882a593Smuzhiyun #define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29) 403*4882a593Smuzhiyun #define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1) 404*4882a593Smuzhiyun #define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF 405*4882a593Smuzhiyun #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 406*4882a593Smuzhiyun #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 407*4882a593Smuzhiyun #define C_000044_GUIDMA_STAT 0xBFFFFFFF 408*4882a593Smuzhiyun #define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30) 409*4882a593Smuzhiyun #define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1) 410*4882a593Smuzhiyun #define C_000044_GUIDMA_AK 0xBFFFFFFF 411*4882a593Smuzhiyun #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 412*4882a593Smuzhiyun #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 413*4882a593Smuzhiyun #define C_000044_VIDDMA_STAT 0x7FFFFFFF 414*4882a593Smuzhiyun #define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31) 415*4882a593Smuzhiyun #define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1) 416*4882a593Smuzhiyun #define C_000044_VIDDMA_AK 0x7FFFFFFF 417*4882a593Smuzhiyun #define R_000050_CRTC_GEN_CNTL 0x000050 418*4882a593Smuzhiyun #define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 419*4882a593Smuzhiyun #define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 420*4882a593Smuzhiyun #define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE 421*4882a593Smuzhiyun #define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1) 422*4882a593Smuzhiyun #define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1) 423*4882a593Smuzhiyun #define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD 424*4882a593Smuzhiyun #define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4) 425*4882a593Smuzhiyun #define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1) 426*4882a593Smuzhiyun #define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF 427*4882a593Smuzhiyun #define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8) 428*4882a593Smuzhiyun #define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF) 429*4882a593Smuzhiyun #define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF 430*4882a593Smuzhiyun #define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15) 431*4882a593Smuzhiyun #define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1) 432*4882a593Smuzhiyun #define C_000050_CRTC_ICON_EN 0xFFFF7FFF 433*4882a593Smuzhiyun #define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16) 434*4882a593Smuzhiyun #define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1) 435*4882a593Smuzhiyun #define C_000050_CRTC_CUR_EN 0xFFFEFFFF 436*4882a593Smuzhiyun #define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17) 437*4882a593Smuzhiyun #define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3) 438*4882a593Smuzhiyun #define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF 439*4882a593Smuzhiyun #define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20) 440*4882a593Smuzhiyun #define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7) 441*4882a593Smuzhiyun #define C_000050_CRTC_CUR_MODE 0xFF8FFFFF 442*4882a593Smuzhiyun #define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24) 443*4882a593Smuzhiyun #define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1) 444*4882a593Smuzhiyun #define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF 445*4882a593Smuzhiyun #define S_000050_CRTC_EN(x) (((x) & 0x1) << 25) 446*4882a593Smuzhiyun #define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1) 447*4882a593Smuzhiyun #define C_000050_CRTC_EN 0xFDFFFFFF 448*4882a593Smuzhiyun #define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 449*4882a593Smuzhiyun #define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 450*4882a593Smuzhiyun #define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF 451*4882a593Smuzhiyun #define R_000054_CRTC_EXT_CNTL 0x000054 452*4882a593Smuzhiyun #define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0) 453*4882a593Smuzhiyun #define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1) 454*4882a593Smuzhiyun #define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE 455*4882a593Smuzhiyun #define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1) 456*4882a593Smuzhiyun #define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3) 457*4882a593Smuzhiyun #define C_000054_VGA_BLINK_RATE 0xFFFFFFF9 458*4882a593Smuzhiyun #define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3) 459*4882a593Smuzhiyun #define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1) 460*4882a593Smuzhiyun #define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7 461*4882a593Smuzhiyun #define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4) 462*4882a593Smuzhiyun #define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1) 463*4882a593Smuzhiyun #define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF 464*4882a593Smuzhiyun #define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5) 465*4882a593Smuzhiyun #define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1) 466*4882a593Smuzhiyun #define C_000054_VGA_TEXT_132 0xFFFFFFDF 467*4882a593Smuzhiyun #define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6) 468*4882a593Smuzhiyun #define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1) 469*4882a593Smuzhiyun #define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF 470*4882a593Smuzhiyun #define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8) 471*4882a593Smuzhiyun #define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1) 472*4882a593Smuzhiyun #define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF 473*4882a593Smuzhiyun #define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9) 474*4882a593Smuzhiyun #define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1) 475*4882a593Smuzhiyun #define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF 476*4882a593Smuzhiyun #define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10) 477*4882a593Smuzhiyun #define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1) 478*4882a593Smuzhiyun #define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF 479*4882a593Smuzhiyun #define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11) 480*4882a593Smuzhiyun #define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1) 481*4882a593Smuzhiyun #define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF 482*4882a593Smuzhiyun #define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12) 483*4882a593Smuzhiyun #define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1) 484*4882a593Smuzhiyun #define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF 485*4882a593Smuzhiyun #define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13) 486*4882a593Smuzhiyun #define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1) 487*4882a593Smuzhiyun #define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF 488*4882a593Smuzhiyun #define S_000054_CRT_ON(x) (((x) & 0x1) << 15) 489*4882a593Smuzhiyun #define G_000054_CRT_ON(x) (((x) >> 15) & 0x1) 490*4882a593Smuzhiyun #define C_000054_CRT_ON 0xFFFF7FFF 491*4882a593Smuzhiyun #define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17) 492*4882a593Smuzhiyun #define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1) 493*4882a593Smuzhiyun #define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF 494*4882a593Smuzhiyun #define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18) 495*4882a593Smuzhiyun #define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1) 496*4882a593Smuzhiyun #define C_000054_VGA_PACK_DIS 0xFFFBFFFF 497*4882a593Smuzhiyun #define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19) 498*4882a593Smuzhiyun #define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1) 499*4882a593Smuzhiyun #define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF 500*4882a593Smuzhiyun #define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24) 501*4882a593Smuzhiyun #define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F) 502*4882a593Smuzhiyun #define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF 503*4882a593Smuzhiyun #define R_000148_MC_FB_LOCATION 0x000148 504*4882a593Smuzhiyun #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 505*4882a593Smuzhiyun #define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 506*4882a593Smuzhiyun #define C_000148_MC_FB_START 0xFFFF0000 507*4882a593Smuzhiyun #define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 508*4882a593Smuzhiyun #define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 509*4882a593Smuzhiyun #define C_000148_MC_FB_TOP 0x0000FFFF 510*4882a593Smuzhiyun #define R_00014C_MC_AGP_LOCATION 0x00014C 511*4882a593Smuzhiyun #define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 512*4882a593Smuzhiyun #define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 513*4882a593Smuzhiyun #define C_00014C_MC_AGP_START 0xFFFF0000 514*4882a593Smuzhiyun #define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 515*4882a593Smuzhiyun #define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 516*4882a593Smuzhiyun #define C_00014C_MC_AGP_TOP 0x0000FFFF 517*4882a593Smuzhiyun #define R_000170_AGP_BASE 0x000170 518*4882a593Smuzhiyun #define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 519*4882a593Smuzhiyun #define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 520*4882a593Smuzhiyun #define C_000170_AGP_BASE_ADDR 0x00000000 521*4882a593Smuzhiyun #define R_00023C_DISPLAY_BASE_ADDR 0x00023C 522*4882a593Smuzhiyun #define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 523*4882a593Smuzhiyun #define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 524*4882a593Smuzhiyun #define C_00023C_DISPLAY_BASE_ADDR 0x00000000 525*4882a593Smuzhiyun #define R_000260_CUR_OFFSET 0x000260 526*4882a593Smuzhiyun #define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 527*4882a593Smuzhiyun #define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 528*4882a593Smuzhiyun #define C_000260_CUR_OFFSET 0xF8000000 529*4882a593Smuzhiyun #define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31) 530*4882a593Smuzhiyun #define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1) 531*4882a593Smuzhiyun #define C_000260_CUR_LOCK 0x7FFFFFFF 532*4882a593Smuzhiyun #define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C 533*4882a593Smuzhiyun #define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 534*4882a593Smuzhiyun #define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 535*4882a593Smuzhiyun #define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000 536*4882a593Smuzhiyun #define R_000360_CUR2_OFFSET 0x000360 537*4882a593Smuzhiyun #define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0) 538*4882a593Smuzhiyun #define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF) 539*4882a593Smuzhiyun #define C_000360_CUR2_OFFSET 0xF8000000 540*4882a593Smuzhiyun #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) 541*4882a593Smuzhiyun #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) 542*4882a593Smuzhiyun #define C_000360_CUR2_LOCK 0x7FFFFFFF 543*4882a593Smuzhiyun #define R_0003C2_GENMO_WT 0x0003C2 544*4882a593Smuzhiyun #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) 545*4882a593Smuzhiyun #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) 546*4882a593Smuzhiyun #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE 547*4882a593Smuzhiyun #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) 548*4882a593Smuzhiyun #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) 549*4882a593Smuzhiyun #define C_0003C2_VGA_RAM_EN 0xFD 550*4882a593Smuzhiyun #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) 551*4882a593Smuzhiyun #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) 552*4882a593Smuzhiyun #define C_0003C2_VGA_CKSEL 0xF3 553*4882a593Smuzhiyun #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) 554*4882a593Smuzhiyun #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) 555*4882a593Smuzhiyun #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF 556*4882a593Smuzhiyun #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) 557*4882a593Smuzhiyun #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) 558*4882a593Smuzhiyun #define C_0003C2_VGA_HSYNC_POL 0xBF 559*4882a593Smuzhiyun #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) 560*4882a593Smuzhiyun #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) 561*4882a593Smuzhiyun #define C_0003C2_VGA_VSYNC_POL 0x7F 562*4882a593Smuzhiyun #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 563*4882a593Smuzhiyun #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) 564*4882a593Smuzhiyun #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) 565*4882a593Smuzhiyun #define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE 566*4882a593Smuzhiyun #define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1) 567*4882a593Smuzhiyun #define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1) 568*4882a593Smuzhiyun #define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD 569*4882a593Smuzhiyun #define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4) 570*4882a593Smuzhiyun #define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1) 571*4882a593Smuzhiyun #define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF 572*4882a593Smuzhiyun #define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5) 573*4882a593Smuzhiyun #define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1) 574*4882a593Smuzhiyun #define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF 575*4882a593Smuzhiyun #define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6) 576*4882a593Smuzhiyun #define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1) 577*4882a593Smuzhiyun #define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF 578*4882a593Smuzhiyun #define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7) 579*4882a593Smuzhiyun #define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1) 580*4882a593Smuzhiyun #define C_0003F8_CRT2_ON 0xFFFFFF7F 581*4882a593Smuzhiyun #define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8) 582*4882a593Smuzhiyun #define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF) 583*4882a593Smuzhiyun #define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF 584*4882a593Smuzhiyun #define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15) 585*4882a593Smuzhiyun #define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1) 586*4882a593Smuzhiyun #define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF 587*4882a593Smuzhiyun #define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16) 588*4882a593Smuzhiyun #define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1) 589*4882a593Smuzhiyun #define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF 590*4882a593Smuzhiyun #define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20) 591*4882a593Smuzhiyun #define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7) 592*4882a593Smuzhiyun #define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF 593*4882a593Smuzhiyun #define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23) 594*4882a593Smuzhiyun #define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1) 595*4882a593Smuzhiyun #define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF 596*4882a593Smuzhiyun #define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25) 597*4882a593Smuzhiyun #define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1) 598*4882a593Smuzhiyun #define C_0003F8_CRTC2_EN 0xFDFFFFFF 599*4882a593Smuzhiyun #define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26) 600*4882a593Smuzhiyun #define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1) 601*4882a593Smuzhiyun #define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF 602*4882a593Smuzhiyun #define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27) 603*4882a593Smuzhiyun #define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1) 604*4882a593Smuzhiyun #define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF 605*4882a593Smuzhiyun #define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28) 606*4882a593Smuzhiyun #define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1) 607*4882a593Smuzhiyun #define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF 608*4882a593Smuzhiyun #define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29) 609*4882a593Smuzhiyun #define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1) 610*4882a593Smuzhiyun #define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF 611*4882a593Smuzhiyun #define R_000420_OV0_SCALE_CNTL 0x000420 612*4882a593Smuzhiyun #define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1) 613*4882a593Smuzhiyun #define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1) 614*4882a593Smuzhiyun #define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD 615*4882a593Smuzhiyun #define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2) 616*4882a593Smuzhiyun #define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1) 617*4882a593Smuzhiyun #define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB 618*4882a593Smuzhiyun #define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3) 619*4882a593Smuzhiyun #define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1) 620*4882a593Smuzhiyun #define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7 621*4882a593Smuzhiyun #define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4) 622*4882a593Smuzhiyun #define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1) 623*4882a593Smuzhiyun #define C_000420_OV0_SIGNED_UV 0xFFFFFFEF 624*4882a593Smuzhiyun #define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5) 625*4882a593Smuzhiyun #define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7) 626*4882a593Smuzhiyun #define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F 627*4882a593Smuzhiyun #define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8) 628*4882a593Smuzhiyun #define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF) 629*4882a593Smuzhiyun #define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF 630*4882a593Smuzhiyun #define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12) 631*4882a593Smuzhiyun #define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1) 632*4882a593Smuzhiyun #define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF 633*4882a593Smuzhiyun #define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14) 634*4882a593Smuzhiyun #define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1) 635*4882a593Smuzhiyun #define C_000420_OV0_CRTC_SEL 0xFFFFBFFF 636*4882a593Smuzhiyun #define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16) 637*4882a593Smuzhiyun #define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F) 638*4882a593Smuzhiyun #define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF 639*4882a593Smuzhiyun #define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24) 640*4882a593Smuzhiyun #define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1) 641*4882a593Smuzhiyun #define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF 642*4882a593Smuzhiyun #define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26) 643*4882a593Smuzhiyun #define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1) 644*4882a593Smuzhiyun #define C_000420_OV0_BANDWIDTH 0xFBFFFFFF 645*4882a593Smuzhiyun #define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28) 646*4882a593Smuzhiyun #define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1) 647*4882a593Smuzhiyun #define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF 648*4882a593Smuzhiyun #define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29) 649*4882a593Smuzhiyun #define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1) 650*4882a593Smuzhiyun #define C_000420_OV0_INT_EMU 0xDFFFFFFF 651*4882a593Smuzhiyun #define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30) 652*4882a593Smuzhiyun #define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1) 653*4882a593Smuzhiyun #define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF 654*4882a593Smuzhiyun #define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31) 655*4882a593Smuzhiyun #define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1) 656*4882a593Smuzhiyun #define C_000420_OV0_SOFT_RESET 0x7FFFFFFF 657*4882a593Smuzhiyun #define R_00070C_CP_RB_RPTR_ADDR 0x00070C 658*4882a593Smuzhiyun #define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0) 659*4882a593Smuzhiyun #define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3) 660*4882a593Smuzhiyun #define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC 661*4882a593Smuzhiyun #define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2) 662*4882a593Smuzhiyun #define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF) 663*4882a593Smuzhiyun #define C_00070C_RB_RPTR_ADDR 0x00000003 664*4882a593Smuzhiyun #define R_000740_CP_CSQ_CNTL 0x000740 665*4882a593Smuzhiyun #define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0) 666*4882a593Smuzhiyun #define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF) 667*4882a593Smuzhiyun #define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00 668*4882a593Smuzhiyun #define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8) 669*4882a593Smuzhiyun #define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF) 670*4882a593Smuzhiyun #define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF 671*4882a593Smuzhiyun #define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28) 672*4882a593Smuzhiyun #define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF) 673*4882a593Smuzhiyun #define C_000740_CSQ_MODE 0x0FFFFFFF 674*4882a593Smuzhiyun #define R_000770_SCRATCH_UMSK 0x000770 675*4882a593Smuzhiyun #define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0) 676*4882a593Smuzhiyun #define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F) 677*4882a593Smuzhiyun #define C_000770_SCRATCH_UMSK 0xFFFFFFC0 678*4882a593Smuzhiyun #define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16) 679*4882a593Smuzhiyun #define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3) 680*4882a593Smuzhiyun #define C_000770_SCRATCH_SWAP 0xFFFCFFFF 681*4882a593Smuzhiyun #define R_000774_SCRATCH_ADDR 0x000774 682*4882a593Smuzhiyun #define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5) 683*4882a593Smuzhiyun #define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF) 684*4882a593Smuzhiyun #define C_000774_SCRATCH_ADDR 0x0000001F 685*4882a593Smuzhiyun #define R_0007C0_CP_STAT 0x0007C0 686*4882a593Smuzhiyun #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 687*4882a593Smuzhiyun #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 688*4882a593Smuzhiyun #define C_0007C0_MRU_BUSY 0xFFFFFFFE 689*4882a593Smuzhiyun #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 690*4882a593Smuzhiyun #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 691*4882a593Smuzhiyun #define C_0007C0_MWU_BUSY 0xFFFFFFFD 692*4882a593Smuzhiyun #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 693*4882a593Smuzhiyun #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 694*4882a593Smuzhiyun #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 695*4882a593Smuzhiyun #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 696*4882a593Smuzhiyun #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 697*4882a593Smuzhiyun #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 698*4882a593Smuzhiyun #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 699*4882a593Smuzhiyun #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 700*4882a593Smuzhiyun #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 701*4882a593Smuzhiyun #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 702*4882a593Smuzhiyun #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 703*4882a593Smuzhiyun #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 704*4882a593Smuzhiyun #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 705*4882a593Smuzhiyun #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 706*4882a593Smuzhiyun #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 707*4882a593Smuzhiyun #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 708*4882a593Smuzhiyun #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 709*4882a593Smuzhiyun #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 710*4882a593Smuzhiyun #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 711*4882a593Smuzhiyun #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 712*4882a593Smuzhiyun #define C_0007C0_CSI_BUSY 0xFFFFDFFF 713*4882a593Smuzhiyun #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 714*4882a593Smuzhiyun #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 715*4882a593Smuzhiyun #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 716*4882a593Smuzhiyun #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 717*4882a593Smuzhiyun #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 718*4882a593Smuzhiyun #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 719*4882a593Smuzhiyun #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 720*4882a593Smuzhiyun #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 721*4882a593Smuzhiyun #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 722*4882a593Smuzhiyun #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 723*4882a593Smuzhiyun #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 724*4882a593Smuzhiyun #define C_0007C0_CP_BUSY 0x7FFFFFFF 725*4882a593Smuzhiyun #define R_000E40_RBBM_STATUS 0x000E40 726*4882a593Smuzhiyun #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 727*4882a593Smuzhiyun #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 728*4882a593Smuzhiyun #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 729*4882a593Smuzhiyun #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 730*4882a593Smuzhiyun #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 731*4882a593Smuzhiyun #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 732*4882a593Smuzhiyun #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 733*4882a593Smuzhiyun #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 734*4882a593Smuzhiyun #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 735*4882a593Smuzhiyun #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 736*4882a593Smuzhiyun #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 737*4882a593Smuzhiyun #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 738*4882a593Smuzhiyun #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 739*4882a593Smuzhiyun #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 740*4882a593Smuzhiyun #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 741*4882a593Smuzhiyun #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 742*4882a593Smuzhiyun #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 743*4882a593Smuzhiyun #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 744*4882a593Smuzhiyun #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 745*4882a593Smuzhiyun #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 746*4882a593Smuzhiyun #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 747*4882a593Smuzhiyun #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 748*4882a593Smuzhiyun #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 749*4882a593Smuzhiyun #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 750*4882a593Smuzhiyun #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 751*4882a593Smuzhiyun #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 752*4882a593Smuzhiyun #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 753*4882a593Smuzhiyun #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 754*4882a593Smuzhiyun #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 755*4882a593Smuzhiyun #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 756*4882a593Smuzhiyun #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 757*4882a593Smuzhiyun #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 758*4882a593Smuzhiyun #define C_000E40_E2_BUSY 0xFFFDFFFF 759*4882a593Smuzhiyun #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 760*4882a593Smuzhiyun #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 761*4882a593Smuzhiyun #define C_000E40_RB2D_BUSY 0xFFFBFFFF 762*4882a593Smuzhiyun #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 763*4882a593Smuzhiyun #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 764*4882a593Smuzhiyun #define C_000E40_RB3D_BUSY 0xFFF7FFFF 765*4882a593Smuzhiyun #define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20) 766*4882a593Smuzhiyun #define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1) 767*4882a593Smuzhiyun #define C_000E40_SE_BUSY 0xFFEFFFFF 768*4882a593Smuzhiyun #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 769*4882a593Smuzhiyun #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 770*4882a593Smuzhiyun #define C_000E40_RE_BUSY 0xFFDFFFFF 771*4882a593Smuzhiyun #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 772*4882a593Smuzhiyun #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 773*4882a593Smuzhiyun #define C_000E40_TAM_BUSY 0xFFBFFFFF 774*4882a593Smuzhiyun #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 775*4882a593Smuzhiyun #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 776*4882a593Smuzhiyun #define C_000E40_TDM_BUSY 0xFF7FFFFF 777*4882a593Smuzhiyun #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 778*4882a593Smuzhiyun #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 779*4882a593Smuzhiyun #define C_000E40_PB_BUSY 0xFEFFFFFF 780*4882a593Smuzhiyun #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 781*4882a593Smuzhiyun #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 782*4882a593Smuzhiyun #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun #define R_00000D_SCLK_CNTL 0x00000D 786*4882a593Smuzhiyun #define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0) 787*4882a593Smuzhiyun #define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7) 788*4882a593Smuzhiyun #define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8 789*4882a593Smuzhiyun #define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8) 790*4882a593Smuzhiyun #define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7) 791*4882a593Smuzhiyun #define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF 792*4882a593Smuzhiyun #define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16) 793*4882a593Smuzhiyun #define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1) 794*4882a593Smuzhiyun #define C_00000D_FORCE_CP 0xFFFEFFFF 795*4882a593Smuzhiyun #define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17) 796*4882a593Smuzhiyun #define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1) 797*4882a593Smuzhiyun #define C_00000D_FORCE_HDP 0xFFFDFFFF 798*4882a593Smuzhiyun #define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18) 799*4882a593Smuzhiyun #define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1) 800*4882a593Smuzhiyun #define C_00000D_FORCE_DISP 0xFFFBFFFF 801*4882a593Smuzhiyun #define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19) 802*4882a593Smuzhiyun #define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1) 803*4882a593Smuzhiyun #define C_00000D_FORCE_TOP 0xFFF7FFFF 804*4882a593Smuzhiyun #define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20) 805*4882a593Smuzhiyun #define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1) 806*4882a593Smuzhiyun #define C_00000D_FORCE_E2 0xFFEFFFFF 807*4882a593Smuzhiyun #define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21) 808*4882a593Smuzhiyun #define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1) 809*4882a593Smuzhiyun #define C_00000D_FORCE_SE 0xFFDFFFFF 810*4882a593Smuzhiyun #define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22) 811*4882a593Smuzhiyun #define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1) 812*4882a593Smuzhiyun #define C_00000D_FORCE_IDCT 0xFFBFFFFF 813*4882a593Smuzhiyun #define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23) 814*4882a593Smuzhiyun #define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1) 815*4882a593Smuzhiyun #define C_00000D_FORCE_VIP 0xFF7FFFFF 816*4882a593Smuzhiyun #define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24) 817*4882a593Smuzhiyun #define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1) 818*4882a593Smuzhiyun #define C_00000D_FORCE_RE 0xFEFFFFFF 819*4882a593Smuzhiyun #define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25) 820*4882a593Smuzhiyun #define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1) 821*4882a593Smuzhiyun #define C_00000D_FORCE_PB 0xFDFFFFFF 822*4882a593Smuzhiyun #define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26) 823*4882a593Smuzhiyun #define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1) 824*4882a593Smuzhiyun #define C_00000D_FORCE_TAM 0xFBFFFFFF 825*4882a593Smuzhiyun #define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27) 826*4882a593Smuzhiyun #define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1) 827*4882a593Smuzhiyun #define C_00000D_FORCE_TDM 0xF7FFFFFF 828*4882a593Smuzhiyun #define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28) 829*4882a593Smuzhiyun #define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1) 830*4882a593Smuzhiyun #define C_00000D_FORCE_RB 0xEFFFFFFF 831*4882a593Smuzhiyun 832*4882a593Smuzhiyun /* PLL regs */ 833*4882a593Smuzhiyun #define SCLK_CNTL 0xd 834*4882a593Smuzhiyun #define FORCE_HDP (1 << 17) 835*4882a593Smuzhiyun #define CLK_PWRMGT_CNTL 0x14 836*4882a593Smuzhiyun #define GLOBAL_PMAN_EN (1 << 10) 837*4882a593Smuzhiyun #define DISP_PM (1 << 20) 838*4882a593Smuzhiyun #define PLL_PWRMGT_CNTL 0x15 839*4882a593Smuzhiyun #define MPLL_TURNOFF (1 << 0) 840*4882a593Smuzhiyun #define SPLL_TURNOFF (1 << 1) 841*4882a593Smuzhiyun #define PPLL_TURNOFF (1 << 2) 842*4882a593Smuzhiyun #define P2PLL_TURNOFF (1 << 3) 843*4882a593Smuzhiyun #define TVPLL_TURNOFF (1 << 4) 844*4882a593Smuzhiyun #define MOBILE_SU (1 << 16) 845*4882a593Smuzhiyun #define SU_SCLK_USE_BCLK (1 << 17) 846*4882a593Smuzhiyun #define SCLK_CNTL2 0x1e 847*4882a593Smuzhiyun #define REDUCED_SPEED_SCLK_MODE (1 << 16) 848*4882a593Smuzhiyun #define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17) 849*4882a593Smuzhiyun #define MCLK_MISC 0x1f 850*4882a593Smuzhiyun #define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18) 851*4882a593Smuzhiyun #define SCLK_MORE_CNTL 0x35 852*4882a593Smuzhiyun #define REDUCED_SPEED_SCLK_EN (1 << 16) 853*4882a593Smuzhiyun #define IO_CG_VOLTAGE_DROP (1 << 17) 854*4882a593Smuzhiyun #define VOLTAGE_DELAY_SEL(x) ((x) << 20) 855*4882a593Smuzhiyun #define VOLTAGE_DROP_SYNC (1 << 19) 856*4882a593Smuzhiyun 857*4882a593Smuzhiyun /* mmreg */ 858*4882a593Smuzhiyun #define DISP_PWR_MAN 0xd08 859*4882a593Smuzhiyun #define DISP_D3_GRPH_RST (1 << 18) 860*4882a593Smuzhiyun #define DISP_D3_SUBPIC_RST (1 << 19) 861*4882a593Smuzhiyun #define DISP_D3_OV0_RST (1 << 20) 862*4882a593Smuzhiyun #define DISP_D1D2_GRPH_RST (1 << 21) 863*4882a593Smuzhiyun #define DISP_D1D2_SUBPIC_RST (1 << 22) 864*4882a593Smuzhiyun #define DISP_D1D2_OV0_RST (1 << 23) 865*4882a593Smuzhiyun #define DISP_DVO_ENABLE_RST (1 << 24) 866*4882a593Smuzhiyun #define TV_ENABLE_RST (1 << 25) 867*4882a593Smuzhiyun #define AUTO_PWRUP_EN (1 << 26) 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun #endif 870