1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * mt6797-reg.h -- Mediatek 6797 audio driver reg definition 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 6*4882a593Smuzhiyun * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _MT6797_REG_H_ 10*4882a593Smuzhiyun #define _MT6797_REG_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AUDIO_TOP_CON0 0x0000 13*4882a593Smuzhiyun #define AUDIO_TOP_CON1 0x0004 14*4882a593Smuzhiyun #define AUDIO_TOP_CON3 0x000c 15*4882a593Smuzhiyun #define AFE_DAC_CON0 0x0010 16*4882a593Smuzhiyun #define AFE_DAC_CON1 0x0014 17*4882a593Smuzhiyun #define AFE_I2S_CON 0x0018 18*4882a593Smuzhiyun #define AFE_DAIBT_CON0 0x001c 19*4882a593Smuzhiyun #define AFE_CONN0 0x0020 20*4882a593Smuzhiyun #define AFE_CONN1 0x0024 21*4882a593Smuzhiyun #define AFE_CONN2 0x0028 22*4882a593Smuzhiyun #define AFE_CONN3 0x002c 23*4882a593Smuzhiyun #define AFE_CONN4 0x0030 24*4882a593Smuzhiyun #define AFE_I2S_CON1 0x0034 25*4882a593Smuzhiyun #define AFE_I2S_CON2 0x0038 26*4882a593Smuzhiyun #define AFE_MRGIF_CON 0x003c 27*4882a593Smuzhiyun #define AFE_DL1_BASE 0x0040 28*4882a593Smuzhiyun #define AFE_DL1_CUR 0x0044 29*4882a593Smuzhiyun #define AFE_DL1_END 0x0048 30*4882a593Smuzhiyun #define AFE_I2S_CON3 0x004c 31*4882a593Smuzhiyun #define AFE_DL2_BASE 0x0050 32*4882a593Smuzhiyun #define AFE_DL2_CUR 0x0054 33*4882a593Smuzhiyun #define AFE_DL2_END 0x0058 34*4882a593Smuzhiyun #define AFE_CONN5 0x005c 35*4882a593Smuzhiyun #define AFE_CONN_24BIT 0x006c 36*4882a593Smuzhiyun #define AFE_AWB_BASE 0x0070 37*4882a593Smuzhiyun #define AFE_AWB_END 0x0078 38*4882a593Smuzhiyun #define AFE_AWB_CUR 0x007c 39*4882a593Smuzhiyun #define AFE_VUL_BASE 0x0080 40*4882a593Smuzhiyun #define AFE_VUL_END 0x0088 41*4882a593Smuzhiyun #define AFE_VUL_CUR 0x008c 42*4882a593Smuzhiyun #define AFE_DAI_BASE 0x0090 43*4882a593Smuzhiyun #define AFE_DAI_END 0x0098 44*4882a593Smuzhiyun #define AFE_DAI_CUR 0x009c 45*4882a593Smuzhiyun #define AFE_CONN6 0x00bc 46*4882a593Smuzhiyun #define AFE_MEMIF_MSB 0x00cc 47*4882a593Smuzhiyun #define AFE_MEMIF_MON0 0x00d0 48*4882a593Smuzhiyun #define AFE_MEMIF_MON1 0x00d4 49*4882a593Smuzhiyun #define AFE_MEMIF_MON2 0x00d8 50*4882a593Smuzhiyun #define AFE_MEMIF_MON4 0x00e0 51*4882a593Smuzhiyun #define AFE_ADDA_DL_SRC2_CON0 0x0108 52*4882a593Smuzhiyun #define AFE_ADDA_DL_SRC2_CON1 0x010c 53*4882a593Smuzhiyun #define AFE_ADDA_UL_SRC_CON0 0x0114 54*4882a593Smuzhiyun #define AFE_ADDA_UL_SRC_CON1 0x0118 55*4882a593Smuzhiyun #define AFE_ADDA_TOP_CON0 0x0120 56*4882a593Smuzhiyun #define AFE_ADDA_UL_DL_CON0 0x0124 57*4882a593Smuzhiyun #define AFE_ADDA_SRC_DEBUG 0x012c 58*4882a593Smuzhiyun #define AFE_ADDA_SRC_DEBUG_MON0 0x0130 59*4882a593Smuzhiyun #define AFE_ADDA_SRC_DEBUG_MON1 0x0134 60*4882a593Smuzhiyun #define AFE_ADDA_NEWIF_CFG0 0x0138 61*4882a593Smuzhiyun #define AFE_ADDA_NEWIF_CFG1 0x013c 62*4882a593Smuzhiyun #define AFE_ADDA_NEWIF_CFG2 0x0140 63*4882a593Smuzhiyun #define AFE_DMA_CTL 0x0150 64*4882a593Smuzhiyun #define AFE_DMA_MON0 0x0154 65*4882a593Smuzhiyun #define AFE_DMA_MON1 0x0158 66*4882a593Smuzhiyun #define AFE_SIDETONE_DEBUG 0x01d0 67*4882a593Smuzhiyun #define AFE_SIDETONE_MON 0x01d4 68*4882a593Smuzhiyun #define AFE_SIDETONE_CON0 0x01e0 69*4882a593Smuzhiyun #define AFE_SIDETONE_COEFF 0x01e4 70*4882a593Smuzhiyun #define AFE_SIDETONE_CON1 0x01e8 71*4882a593Smuzhiyun #define AFE_SIDETONE_GAIN 0x01ec 72*4882a593Smuzhiyun #define AFE_SGEN_CON0 0x01f0 73*4882a593Smuzhiyun #define AFE_SINEGEN_CON_TDM 0x01fc 74*4882a593Smuzhiyun #define AFE_TOP_CON0 0x0200 75*4882a593Smuzhiyun #define AFE_ADDA_PREDIS_CON0 0x0260 76*4882a593Smuzhiyun #define AFE_ADDA_PREDIS_CON1 0x0264 77*4882a593Smuzhiyun #define AFE_MRGIF_MON0 0x0270 78*4882a593Smuzhiyun #define AFE_MRGIF_MON1 0x0274 79*4882a593Smuzhiyun #define AFE_MRGIF_MON2 0x0278 80*4882a593Smuzhiyun #define AFE_I2S_MON 0x027c 81*4882a593Smuzhiyun #define AFE_MOD_DAI_BASE 0x0330 82*4882a593Smuzhiyun #define AFE_MOD_DAI_END 0x0338 83*4882a593Smuzhiyun #define AFE_MOD_DAI_CUR 0x033c 84*4882a593Smuzhiyun #define AFE_VUL_D2_BASE 0x0350 85*4882a593Smuzhiyun #define AFE_VUL_D2_END 0x0358 86*4882a593Smuzhiyun #define AFE_VUL_D2_CUR 0x035c 87*4882a593Smuzhiyun #define AFE_DL3_BASE 0x0360 88*4882a593Smuzhiyun #define AFE_DL3_CUR 0x0364 89*4882a593Smuzhiyun #define AFE_DL3_END 0x0368 90*4882a593Smuzhiyun #define AFE_HDMI_OUT_CON0 0x0370 91*4882a593Smuzhiyun #define AFE_HDMI_BASE 0x0374 92*4882a593Smuzhiyun #define AFE_HDMI_CUR 0x0378 93*4882a593Smuzhiyun #define AFE_HDMI_END 0x037c 94*4882a593Smuzhiyun #define AFE_HDMI_CONN0 0x0390 95*4882a593Smuzhiyun #define AFE_IRQ3_MCU_CNT_MON 0x0398 96*4882a593Smuzhiyun #define AFE_IRQ4_MCU_CNT_MON 0x039c 97*4882a593Smuzhiyun #define AFE_IRQ_MCU_CON 0x03a0 98*4882a593Smuzhiyun #define AFE_IRQ_MCU_STATUS 0x03a4 99*4882a593Smuzhiyun #define AFE_IRQ_MCU_CLR 0x03a8 100*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT1 0x03ac 101*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT2 0x03b0 102*4882a593Smuzhiyun #define AFE_IRQ_MCU_EN 0x03b4 103*4882a593Smuzhiyun #define AFE_IRQ_MCU_MON2 0x03b8 104*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT5 0x03bc 105*4882a593Smuzhiyun #define AFE_IRQ1_MCU_CNT_MON 0x03c0 106*4882a593Smuzhiyun #define AFE_IRQ2_MCU_CNT_MON 0x03c4 107*4882a593Smuzhiyun #define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8 108*4882a593Smuzhiyun #define AFE_IRQ5_MCU_CNT_MON 0x03cc 109*4882a593Smuzhiyun #define AFE_MEMIF_MINLEN 0x03d0 110*4882a593Smuzhiyun #define AFE_MEMIF_MAXLEN 0x03d4 111*4882a593Smuzhiyun #define AFE_MEMIF_PBUF_SIZE 0x03d8 112*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT7 0x03dc 113*4882a593Smuzhiyun #define AFE_IRQ7_MCU_CNT_MON 0x03e0 114*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT3 0x03e4 115*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT4 0x03e8 116*4882a593Smuzhiyun #define AFE_APLL1_TUNER_CFG 0x03f0 117*4882a593Smuzhiyun #define AFE_APLL2_TUNER_CFG 0x03f4 118*4882a593Smuzhiyun #define AFE_MEMIF_HD_MODE 0x03f8 119*4882a593Smuzhiyun #define AFE_MEMIF_HDALIGN 0x03fc 120*4882a593Smuzhiyun #define AFE_GAIN1_CON0 0x0410 121*4882a593Smuzhiyun #define AFE_GAIN1_CON1 0x0414 122*4882a593Smuzhiyun #define AFE_GAIN1_CON2 0x0418 123*4882a593Smuzhiyun #define AFE_GAIN1_CON3 0x041c 124*4882a593Smuzhiyun #define AFE_CONN7 0x0420 125*4882a593Smuzhiyun #define AFE_GAIN1_CUR 0x0424 126*4882a593Smuzhiyun #define AFE_GAIN2_CON0 0x0428 127*4882a593Smuzhiyun #define AFE_GAIN2_CON1 0x042c 128*4882a593Smuzhiyun #define AFE_GAIN2_CON2 0x0430 129*4882a593Smuzhiyun #define AFE_GAIN2_CON3 0x0434 130*4882a593Smuzhiyun #define AFE_CONN8 0x0438 131*4882a593Smuzhiyun #define AFE_GAIN2_CUR 0x043c 132*4882a593Smuzhiyun #define AFE_CONN9 0x0440 133*4882a593Smuzhiyun #define AFE_CONN10 0x0444 134*4882a593Smuzhiyun #define AFE_CONN11 0x0448 135*4882a593Smuzhiyun #define AFE_CONN12 0x044c 136*4882a593Smuzhiyun #define AFE_CONN13 0x0450 137*4882a593Smuzhiyun #define AFE_CONN14 0x0454 138*4882a593Smuzhiyun #define AFE_CONN15 0x0458 139*4882a593Smuzhiyun #define AFE_CONN16 0x045c 140*4882a593Smuzhiyun #define AFE_CONN17 0x0460 141*4882a593Smuzhiyun #define AFE_CONN18 0x0464 142*4882a593Smuzhiyun #define AFE_CONN19 0x0468 143*4882a593Smuzhiyun #define AFE_CONN20 0x046c 144*4882a593Smuzhiyun #define AFE_CONN21 0x0470 145*4882a593Smuzhiyun #define AFE_CONN22 0x0474 146*4882a593Smuzhiyun #define AFE_CONN23 0x0478 147*4882a593Smuzhiyun #define AFE_CONN24 0x047c 148*4882a593Smuzhiyun #define AFE_CONN_RS 0x0494 149*4882a593Smuzhiyun #define AFE_CONN_DI 0x0498 150*4882a593Smuzhiyun #define AFE_CONN25 0x04b0 151*4882a593Smuzhiyun #define AFE_CONN26 0x04b4 152*4882a593Smuzhiyun #define AFE_CONN27 0x04b8 153*4882a593Smuzhiyun #define AFE_CONN28 0x04bc 154*4882a593Smuzhiyun #define AFE_CONN29 0x04c0 155*4882a593Smuzhiyun #define AFE_SRAM_DELSEL_CON0 0x04f0 156*4882a593Smuzhiyun #define AFE_SRAM_DELSEL_CON1 0x04f4 157*4882a593Smuzhiyun #define AFE_ASRC_CON0 0x0500 158*4882a593Smuzhiyun #define AFE_ASRC_CON1 0x0504 159*4882a593Smuzhiyun #define AFE_ASRC_CON2 0x0508 160*4882a593Smuzhiyun #define AFE_ASRC_CON3 0x050c 161*4882a593Smuzhiyun #define AFE_ASRC_CON4 0x0510 162*4882a593Smuzhiyun #define AFE_ASRC_CON5 0x0514 163*4882a593Smuzhiyun #define AFE_ASRC_CON6 0x0518 164*4882a593Smuzhiyun #define AFE_ASRC_CON7 0x051c 165*4882a593Smuzhiyun #define AFE_ASRC_CON8 0x0520 166*4882a593Smuzhiyun #define AFE_ASRC_CON9 0x0524 167*4882a593Smuzhiyun #define AFE_ASRC_CON10 0x0528 168*4882a593Smuzhiyun #define AFE_ASRC_CON11 0x052c 169*4882a593Smuzhiyun #define PCM_INTF_CON1 0x0530 170*4882a593Smuzhiyun #define PCM_INTF_CON2 0x0538 171*4882a593Smuzhiyun #define PCM2_INTF_CON 0x053c 172*4882a593Smuzhiyun #define AFE_TDM_CON1 0x0548 173*4882a593Smuzhiyun #define AFE_TDM_CON2 0x054c 174*4882a593Smuzhiyun #define AFE_ASRC_CON13 0x0550 175*4882a593Smuzhiyun #define AFE_ASRC_CON14 0x0554 176*4882a593Smuzhiyun #define AFE_ASRC_CON15 0x0558 177*4882a593Smuzhiyun #define AFE_ASRC_CON16 0x055c 178*4882a593Smuzhiyun #define AFE_ASRC_CON17 0x0560 179*4882a593Smuzhiyun #define AFE_ASRC_CON18 0x0564 180*4882a593Smuzhiyun #define AFE_ASRC_CON19 0x0568 181*4882a593Smuzhiyun #define AFE_ASRC_CON20 0x056c 182*4882a593Smuzhiyun #define AFE_ASRC_CON21 0x0570 183*4882a593Smuzhiyun #define CLK_AUDDIV_0 0x05a0 184*4882a593Smuzhiyun #define CLK_AUDDIV_1 0x05a4 185*4882a593Smuzhiyun #define CLK_AUDDIV_2 0x05a8 186*4882a593Smuzhiyun #define CLK_AUDDIV_3 0x05ac 187*4882a593Smuzhiyun #define AUDIO_TOP_DBG_CON 0x05c8 188*4882a593Smuzhiyun #define AUDIO_TOP_DBG_MON0 0x05cc 189*4882a593Smuzhiyun #define AUDIO_TOP_DBG_MON1 0x05d0 190*4882a593Smuzhiyun #define AUDIO_TOP_DBG_MON2 0x05d4 191*4882a593Smuzhiyun #define AFE_ADDA2_TOP_CON0 0x0600 192*4882a593Smuzhiyun #define AFE_ASRC4_CON0 0x06c0 193*4882a593Smuzhiyun #define AFE_ASRC4_CON1 0x06c4 194*4882a593Smuzhiyun #define AFE_ASRC4_CON2 0x06c8 195*4882a593Smuzhiyun #define AFE_ASRC4_CON3 0x06cc 196*4882a593Smuzhiyun #define AFE_ASRC4_CON4 0x06d0 197*4882a593Smuzhiyun #define AFE_ASRC4_CON5 0x06d4 198*4882a593Smuzhiyun #define AFE_ASRC4_CON6 0x06d8 199*4882a593Smuzhiyun #define AFE_ASRC4_CON7 0x06dc 200*4882a593Smuzhiyun #define AFE_ASRC4_CON8 0x06e0 201*4882a593Smuzhiyun #define AFE_ASRC4_CON9 0x06e4 202*4882a593Smuzhiyun #define AFE_ASRC4_CON10 0x06e8 203*4882a593Smuzhiyun #define AFE_ASRC4_CON11 0x06ec 204*4882a593Smuzhiyun #define AFE_ASRC4_CON12 0x06f0 205*4882a593Smuzhiyun #define AFE_ASRC4_CON13 0x06f4 206*4882a593Smuzhiyun #define AFE_ASRC4_CON14 0x06f8 207*4882a593Smuzhiyun #define AFE_ASRC2_CON0 0x0700 208*4882a593Smuzhiyun #define AFE_ASRC2_CON1 0x0704 209*4882a593Smuzhiyun #define AFE_ASRC2_CON2 0x0708 210*4882a593Smuzhiyun #define AFE_ASRC2_CON3 0x070c 211*4882a593Smuzhiyun #define AFE_ASRC2_CON4 0x0710 212*4882a593Smuzhiyun #define AFE_ASRC2_CON5 0x0714 213*4882a593Smuzhiyun #define AFE_ASRC2_CON6 0x0718 214*4882a593Smuzhiyun #define AFE_ASRC2_CON7 0x071c 215*4882a593Smuzhiyun #define AFE_ASRC2_CON8 0x0720 216*4882a593Smuzhiyun #define AFE_ASRC2_CON9 0x0724 217*4882a593Smuzhiyun #define AFE_ASRC2_CON10 0x0728 218*4882a593Smuzhiyun #define AFE_ASRC2_CON11 0x072c 219*4882a593Smuzhiyun #define AFE_ASRC2_CON12 0x0730 220*4882a593Smuzhiyun #define AFE_ASRC2_CON13 0x0734 221*4882a593Smuzhiyun #define AFE_ASRC2_CON14 0x0738 222*4882a593Smuzhiyun #define AFE_ASRC3_CON0 0x0740 223*4882a593Smuzhiyun #define AFE_ASRC3_CON1 0x0744 224*4882a593Smuzhiyun #define AFE_ASRC3_CON2 0x0748 225*4882a593Smuzhiyun #define AFE_ASRC3_CON3 0x074c 226*4882a593Smuzhiyun #define AFE_ASRC3_CON4 0x0750 227*4882a593Smuzhiyun #define AFE_ASRC3_CON5 0x0754 228*4882a593Smuzhiyun #define AFE_ASRC3_CON6 0x0758 229*4882a593Smuzhiyun #define AFE_ASRC3_CON7 0x075c 230*4882a593Smuzhiyun #define AFE_ASRC3_CON8 0x0760 231*4882a593Smuzhiyun #define AFE_ASRC3_CON9 0x0764 232*4882a593Smuzhiyun #define AFE_ASRC3_CON10 0x0768 233*4882a593Smuzhiyun #define AFE_ASRC3_CON11 0x076c 234*4882a593Smuzhiyun #define AFE_ASRC3_CON12 0x0770 235*4882a593Smuzhiyun #define AFE_ASRC3_CON13 0x0774 236*4882a593Smuzhiyun #define AFE_ASRC3_CON14 0x0778 237*4882a593Smuzhiyun #define AFE_GENERAL_REG0 0x0800 238*4882a593Smuzhiyun #define AFE_GENERAL_REG1 0x0804 239*4882a593Smuzhiyun #define AFE_GENERAL_REG2 0x0808 240*4882a593Smuzhiyun #define AFE_GENERAL_REG3 0x080c 241*4882a593Smuzhiyun #define AFE_GENERAL_REG4 0x0810 242*4882a593Smuzhiyun #define AFE_GENERAL_REG5 0x0814 243*4882a593Smuzhiyun #define AFE_GENERAL_REG6 0x0818 244*4882a593Smuzhiyun #define AFE_GENERAL_REG7 0x081c 245*4882a593Smuzhiyun #define AFE_GENERAL_REG8 0x0820 246*4882a593Smuzhiyun #define AFE_GENERAL_REG9 0x0824 247*4882a593Smuzhiyun #define AFE_GENERAL_REG10 0x0828 248*4882a593Smuzhiyun #define AFE_GENERAL_REG11 0x082c 249*4882a593Smuzhiyun #define AFE_GENERAL_REG12 0x0830 250*4882a593Smuzhiyun #define AFE_GENERAL_REG13 0x0834 251*4882a593Smuzhiyun #define AFE_GENERAL_REG14 0x0838 252*4882a593Smuzhiyun #define AFE_GENERAL_REG15 0x083c 253*4882a593Smuzhiyun #define AFE_CBIP_CFG0 0x0840 254*4882a593Smuzhiyun #define AFE_CBIP_MON0 0x0844 255*4882a593Smuzhiyun #define AFE_CBIP_SLV_MUX_MON0 0x0848 256*4882a593Smuzhiyun #define AFE_CBIP_SLV_DECODER_MON0 0x084c 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun #define AFE_MAX_REGISTER AFE_CBIP_SLV_DECODER_MON0 259*4882a593Smuzhiyun #define AFE_IRQ_STATUS_BITS 0x5f 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /* AUDIO_TOP_CON0 */ 262*4882a593Smuzhiyun #define AHB_IDLE_EN_INT_SFT 30 263*4882a593Smuzhiyun #define AHB_IDLE_EN_INT_MASK 0x1 264*4882a593Smuzhiyun #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30) 265*4882a593Smuzhiyun #define AHB_IDLE_EN_EXT_SFT 29 266*4882a593Smuzhiyun #define AHB_IDLE_EN_EXT_MASK 0x1 267*4882a593Smuzhiyun #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29) 268*4882a593Smuzhiyun #define PDN_TML_SFT 27 269*4882a593Smuzhiyun #define PDN_TML_MASK 0x1 270*4882a593Smuzhiyun #define PDN_TML_MASK_SFT (0x1 << 27) 271*4882a593Smuzhiyun #define PDN_DAC_PREDIS_SFT 26 272*4882a593Smuzhiyun #define PDN_DAC_PREDIS_MASK 0x1 273*4882a593Smuzhiyun #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26) 274*4882a593Smuzhiyun #define PDN_DAC_SFT 25 275*4882a593Smuzhiyun #define PDN_DAC_MASK 0x1 276*4882a593Smuzhiyun #define PDN_DAC_MASK_SFT (0x1 << 25) 277*4882a593Smuzhiyun #define PDN_ADC_SFT 24 278*4882a593Smuzhiyun #define PDN_ADC_MASK 0x1 279*4882a593Smuzhiyun #define PDN_ADC_MASK_SFT (0x1 << 24) 280*4882a593Smuzhiyun #define PDN_TDM_CK_SFT 20 281*4882a593Smuzhiyun #define PDN_TDM_CK_MASK 0x1 282*4882a593Smuzhiyun #define PDN_TDM_CK_MASK_SFT (0x1 << 20) 283*4882a593Smuzhiyun #define PDN_APLL_TUNER_SFT 19 284*4882a593Smuzhiyun #define PDN_APLL_TUNER_MASK 0x1 285*4882a593Smuzhiyun #define PDN_APLL_TUNER_MASK_SFT (0x1 << 19) 286*4882a593Smuzhiyun #define PDN_APLL2_TUNER_SFT 18 287*4882a593Smuzhiyun #define PDN_APLL2_TUNER_MASK 0x1 288*4882a593Smuzhiyun #define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18) 289*4882a593Smuzhiyun #define APB3_SEL_SFT 14 290*4882a593Smuzhiyun #define APB3_SEL_MASK 0x1 291*4882a593Smuzhiyun #define APB3_SEL_MASK_SFT (0x1 << 14) 292*4882a593Smuzhiyun #define APB_R2T_SFT 13 293*4882a593Smuzhiyun #define APB_R2T_MASK 0x1 294*4882a593Smuzhiyun #define APB_R2T_MASK_SFT (0x1 << 13) 295*4882a593Smuzhiyun #define APB_W2T_SFT 12 296*4882a593Smuzhiyun #define APB_W2T_MASK 0x1 297*4882a593Smuzhiyun #define APB_W2T_MASK_SFT (0x1 << 12) 298*4882a593Smuzhiyun #define PDN_24M_SFT 9 299*4882a593Smuzhiyun #define PDN_24M_MASK 0x1 300*4882a593Smuzhiyun #define PDN_24M_MASK_SFT (0x1 << 9) 301*4882a593Smuzhiyun #define PDN_22M_SFT 8 302*4882a593Smuzhiyun #define PDN_22M_MASK 0x1 303*4882a593Smuzhiyun #define PDN_22M_MASK_SFT (0x1 << 8) 304*4882a593Smuzhiyun #define PDN_ADDA4_ADC_SFT 7 305*4882a593Smuzhiyun #define PDN_ADDA4_ADC_MASK 0x1 306*4882a593Smuzhiyun #define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7) 307*4882a593Smuzhiyun #define PDN_I2S_SFT 6 308*4882a593Smuzhiyun #define PDN_I2S_MASK 0x1 309*4882a593Smuzhiyun #define PDN_I2S_MASK_SFT (0x1 << 6) 310*4882a593Smuzhiyun #define PDN_AFE_SFT 2 311*4882a593Smuzhiyun #define PDN_AFE_MASK 0x1 312*4882a593Smuzhiyun #define PDN_AFE_MASK_SFT (0x1 << 2) 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* AUDIO_TOP_CON1 */ 315*4882a593Smuzhiyun #define PDN_ADC_HIRES_TML_SFT 17 316*4882a593Smuzhiyun #define PDN_ADC_HIRES_TML_MASK 0x1 317*4882a593Smuzhiyun #define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17) 318*4882a593Smuzhiyun #define PDN_ADC_HIRES_SFT 16 319*4882a593Smuzhiyun #define PDN_ADC_HIRES_MASK 0x1 320*4882a593Smuzhiyun #define PDN_ADC_HIRES_MASK_SFT (0x1 << 16) 321*4882a593Smuzhiyun #define I2S4_BCLK_SW_CG_SFT 7 322*4882a593Smuzhiyun #define I2S4_BCLK_SW_CG_MASK 0x1 323*4882a593Smuzhiyun #define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7) 324*4882a593Smuzhiyun #define I2S3_BCLK_SW_CG_SFT 6 325*4882a593Smuzhiyun #define I2S3_BCLK_SW_CG_MASK 0x1 326*4882a593Smuzhiyun #define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6) 327*4882a593Smuzhiyun #define I2S2_BCLK_SW_CG_SFT 5 328*4882a593Smuzhiyun #define I2S2_BCLK_SW_CG_MASK 0x1 329*4882a593Smuzhiyun #define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5) 330*4882a593Smuzhiyun #define I2S1_BCLK_SW_CG_SFT 4 331*4882a593Smuzhiyun #define I2S1_BCLK_SW_CG_MASK 0x1 332*4882a593Smuzhiyun #define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4) 333*4882a593Smuzhiyun #define I2S_SOFT_RST2_SFT 2 334*4882a593Smuzhiyun #define I2S_SOFT_RST2_MASK 0x1 335*4882a593Smuzhiyun #define I2S_SOFT_RST2_MASK_SFT (0x1 << 2) 336*4882a593Smuzhiyun #define I2S_SOFT_RST_SFT 1 337*4882a593Smuzhiyun #define I2S_SOFT_RST_MASK 0x1 338*4882a593Smuzhiyun #define I2S_SOFT_RST_MASK_SFT (0x1 << 1) 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* AFE_DAC_CON0 */ 341*4882a593Smuzhiyun #define AFE_AWB_RETM_SFT 31 342*4882a593Smuzhiyun #define AFE_AWB_RETM_MASK 0x1 343*4882a593Smuzhiyun #define AFE_AWB_RETM_MASK_SFT (0x1 << 31) 344*4882a593Smuzhiyun #define AFE_DL1_DATA2_RETM_SFT 30 345*4882a593Smuzhiyun #define AFE_DL1_DATA2_RETM_MASK 0x1 346*4882a593Smuzhiyun #define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30) 347*4882a593Smuzhiyun #define AFE_DL2_RETM_SFT 29 348*4882a593Smuzhiyun #define AFE_DL2_RETM_MASK 0x1 349*4882a593Smuzhiyun #define AFE_DL2_RETM_MASK_SFT (0x1 << 29) 350*4882a593Smuzhiyun #define AFE_DL1_RETM_SFT 28 351*4882a593Smuzhiyun #define AFE_DL1_RETM_MASK 0x1 352*4882a593Smuzhiyun #define AFE_DL1_RETM_MASK_SFT (0x1 << 28) 353*4882a593Smuzhiyun #define AFE_ON_RETM_SFT 27 354*4882a593Smuzhiyun #define AFE_ON_RETM_MASK 0x1 355*4882a593Smuzhiyun #define AFE_ON_RETM_MASK_SFT (0x1 << 27) 356*4882a593Smuzhiyun #define MOD_DAI_DUP_WR_SFT 26 357*4882a593Smuzhiyun #define MOD_DAI_DUP_WR_MASK 0x1 358*4882a593Smuzhiyun #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26) 359*4882a593Smuzhiyun #define DAI_MODE_SFT 24 360*4882a593Smuzhiyun #define DAI_MODE_MASK 0x3 361*4882a593Smuzhiyun #define DAI_MODE_MASK_SFT (0x3 << 24) 362*4882a593Smuzhiyun #define VUL_DATA2_MODE_SFT 20 363*4882a593Smuzhiyun #define VUL_DATA2_MODE_MASK 0xf 364*4882a593Smuzhiyun #define VUL_DATA2_MODE_MASK_SFT (0xf << 20) 365*4882a593Smuzhiyun #define DL1_DATA2_MODE_SFT 16 366*4882a593Smuzhiyun #define DL1_DATA2_MODE_MASK 0xf 367*4882a593Smuzhiyun #define DL1_DATA2_MODE_MASK_SFT (0xf << 16) 368*4882a593Smuzhiyun #define DL3_MODE_SFT 12 369*4882a593Smuzhiyun #define DL3_MODE_MASK 0xf 370*4882a593Smuzhiyun #define DL3_MODE_MASK_SFT (0xf << 12) 371*4882a593Smuzhiyun #define VUL_DATA2_R_MONO_SFT 11 372*4882a593Smuzhiyun #define VUL_DATA2_R_MONO_MASK 0x1 373*4882a593Smuzhiyun #define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11) 374*4882a593Smuzhiyun #define VUL_DATA2_DATA_SFT 10 375*4882a593Smuzhiyun #define VUL_DATA2_DATA_MASK 0x1 376*4882a593Smuzhiyun #define VUL_DATA2_DATA_MASK_SFT (0x1 << 10) 377*4882a593Smuzhiyun #define VUL_DATA2_ON_SFT 9 378*4882a593Smuzhiyun #define VUL_DATA2_ON_MASK 0x1 379*4882a593Smuzhiyun #define VUL_DATA2_ON_MASK_SFT (0x1 << 9) 380*4882a593Smuzhiyun #define DL1_DATA2_ON_SFT 8 381*4882a593Smuzhiyun #define DL1_DATA2_ON_MASK 0x1 382*4882a593Smuzhiyun #define DL1_DATA2_ON_MASK_SFT (0x1 << 8) 383*4882a593Smuzhiyun #define MOD_DAI_ON_SFT 7 384*4882a593Smuzhiyun #define MOD_DAI_ON_MASK 0x1 385*4882a593Smuzhiyun #define MOD_DAI_ON_MASK_SFT (0x1 << 7) 386*4882a593Smuzhiyun #define AWB_ON_SFT 6 387*4882a593Smuzhiyun #define AWB_ON_MASK 0x1 388*4882a593Smuzhiyun #define AWB_ON_MASK_SFT (0x1 << 6) 389*4882a593Smuzhiyun #define DL3_ON_SFT 5 390*4882a593Smuzhiyun #define DL3_ON_MASK 0x1 391*4882a593Smuzhiyun #define DL3_ON_MASK_SFT (0x1 << 5) 392*4882a593Smuzhiyun #define DAI_ON_SFT 4 393*4882a593Smuzhiyun #define DAI_ON_MASK 0x1 394*4882a593Smuzhiyun #define DAI_ON_MASK_SFT (0x1 << 4) 395*4882a593Smuzhiyun #define VUL_ON_SFT 3 396*4882a593Smuzhiyun #define VUL_ON_MASK 0x1 397*4882a593Smuzhiyun #define VUL_ON_MASK_SFT (0x1 << 3) 398*4882a593Smuzhiyun #define DL2_ON_SFT 2 399*4882a593Smuzhiyun #define DL2_ON_MASK 0x1 400*4882a593Smuzhiyun #define DL2_ON_MASK_SFT (0x1 << 2) 401*4882a593Smuzhiyun #define DL1_ON_SFT 1 402*4882a593Smuzhiyun #define DL1_ON_MASK 0x1 403*4882a593Smuzhiyun #define DL1_ON_MASK_SFT (0x1 << 1) 404*4882a593Smuzhiyun #define AFE_ON_SFT 0 405*4882a593Smuzhiyun #define AFE_ON_MASK 0x1 406*4882a593Smuzhiyun #define AFE_ON_MASK_SFT (0x1 << 0) 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun /* AFE_DAC_CON1 */ 409*4882a593Smuzhiyun #define MOD_DAI_MODE_SFT 30 410*4882a593Smuzhiyun #define MOD_DAI_MODE_MASK 0x3 411*4882a593Smuzhiyun #define MOD_DAI_MODE_MASK_SFT (0x3 << 30) 412*4882a593Smuzhiyun #define DAI_DUP_WR_SFT 29 413*4882a593Smuzhiyun #define DAI_DUP_WR_MASK 0x1 414*4882a593Smuzhiyun #define DAI_DUP_WR_MASK_SFT (0x1 << 29) 415*4882a593Smuzhiyun #define VUL_R_MONO_SFT 28 416*4882a593Smuzhiyun #define VUL_R_MONO_MASK 0x1 417*4882a593Smuzhiyun #define VUL_R_MONO_MASK_SFT (0x1 << 28) 418*4882a593Smuzhiyun #define VUL_DATA_SFT 27 419*4882a593Smuzhiyun #define VUL_DATA_MASK 0x1 420*4882a593Smuzhiyun #define VUL_DATA_MASK_SFT (0x1 << 27) 421*4882a593Smuzhiyun #define AXI_2X1_CG_DISABLE_SFT 26 422*4882a593Smuzhiyun #define AXI_2X1_CG_DISABLE_MASK 0x1 423*4882a593Smuzhiyun #define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26) 424*4882a593Smuzhiyun #define AWB_R_MONO_SFT 25 425*4882a593Smuzhiyun #define AWB_R_MONO_MASK 0x1 426*4882a593Smuzhiyun #define AWB_R_MONO_MASK_SFT (0x1 << 25) 427*4882a593Smuzhiyun #define AWB_DATA_SFT 24 428*4882a593Smuzhiyun #define AWB_DATA_MASK 0x1 429*4882a593Smuzhiyun #define AWB_DATA_MASK_SFT (0x1 << 24) 430*4882a593Smuzhiyun #define DL3_DATA_SFT 23 431*4882a593Smuzhiyun #define DL3_DATA_MASK 0x1 432*4882a593Smuzhiyun #define DL3_DATA_MASK_SFT (0x1 << 23) 433*4882a593Smuzhiyun #define DL2_DATA_SFT 22 434*4882a593Smuzhiyun #define DL2_DATA_MASK 0x1 435*4882a593Smuzhiyun #define DL2_DATA_MASK_SFT (0x1 << 22) 436*4882a593Smuzhiyun #define DL1_DATA_SFT 21 437*4882a593Smuzhiyun #define DL1_DATA_MASK 0x1 438*4882a593Smuzhiyun #define DL1_DATA_MASK_SFT (0x1 << 21) 439*4882a593Smuzhiyun #define DL1_DATA2_DATA_SFT 20 440*4882a593Smuzhiyun #define DL1_DATA2_DATA_MASK 0x1 441*4882a593Smuzhiyun #define DL1_DATA2_DATA_MASK_SFT (0x1 << 20) 442*4882a593Smuzhiyun #define VUL_MODE_SFT 16 443*4882a593Smuzhiyun #define VUL_MODE_MASK 0xf 444*4882a593Smuzhiyun #define VUL_MODE_MASK_SFT (0xf << 16) 445*4882a593Smuzhiyun #define AWB_MODE_SFT 12 446*4882a593Smuzhiyun #define AWB_MODE_MASK 0xf 447*4882a593Smuzhiyun #define AWB_MODE_MASK_SFT (0xf << 12) 448*4882a593Smuzhiyun #define I2S_MODE_SFT 8 449*4882a593Smuzhiyun #define I2S_MODE_MASK 0xf 450*4882a593Smuzhiyun #define I2S_MODE_MASK_SFT (0xf << 8) 451*4882a593Smuzhiyun #define DL2_MODE_SFT 4 452*4882a593Smuzhiyun #define DL2_MODE_MASK 0xf 453*4882a593Smuzhiyun #define DL2_MODE_MASK_SFT (0xf << 4) 454*4882a593Smuzhiyun #define DL1_MODE_SFT 0 455*4882a593Smuzhiyun #define DL1_MODE_MASK 0xf 456*4882a593Smuzhiyun #define DL1_MODE_MASK_SFT (0xf << 0) 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /* AFE_ADDA_DL_SRC2_CON0 */ 459*4882a593Smuzhiyun #define DL_2_INPUT_MODE_CTL_SFT 28 460*4882a593Smuzhiyun #define DL_2_INPUT_MODE_CTL_MASK 0xf 461*4882a593Smuzhiyun #define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28) 462*4882a593Smuzhiyun #define DL_2_CH1_SATURATION_EN_CTL_SFT 27 463*4882a593Smuzhiyun #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1 464*4882a593Smuzhiyun #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27) 465*4882a593Smuzhiyun #define DL_2_CH2_SATURATION_EN_CTL_SFT 26 466*4882a593Smuzhiyun #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1 467*4882a593Smuzhiyun #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26) 468*4882a593Smuzhiyun #define DL_2_OUTPUT_SEL_CTL_SFT 24 469*4882a593Smuzhiyun #define DL_2_OUTPUT_SEL_CTL_MASK 0x3 470*4882a593Smuzhiyun #define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24) 471*4882a593Smuzhiyun #define DL_2_FADEIN_0START_EN_SFT 16 472*4882a593Smuzhiyun #define DL_2_FADEIN_0START_EN_MASK 0x3 473*4882a593Smuzhiyun #define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16) 474*4882a593Smuzhiyun #define DL_DISABLE_HW_CG_CTL_SFT 15 475*4882a593Smuzhiyun #define DL_DISABLE_HW_CG_CTL_MASK 0x1 476*4882a593Smuzhiyun #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15) 477*4882a593Smuzhiyun #define C_DATA_EN_SEL_CTL_PRE_SFT 14 478*4882a593Smuzhiyun #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1 479*4882a593Smuzhiyun #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14) 480*4882a593Smuzhiyun #define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13 481*4882a593Smuzhiyun #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1 482*4882a593Smuzhiyun #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13) 483*4882a593Smuzhiyun #define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12 484*4882a593Smuzhiyun #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1 485*4882a593Smuzhiyun #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12) 486*4882a593Smuzhiyun #define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11 487*4882a593Smuzhiyun #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1 488*4882a593Smuzhiyun #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11) 489*4882a593Smuzhiyun #define DL2_ARAMPSP_CTL_PRE_SFT 9 490*4882a593Smuzhiyun #define DL2_ARAMPSP_CTL_PRE_MASK 0x3 491*4882a593Smuzhiyun #define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9) 492*4882a593Smuzhiyun #define DL_2_IIRMODE_CTL_PRE_SFT 6 493*4882a593Smuzhiyun #define DL_2_IIRMODE_CTL_PRE_MASK 0x7 494*4882a593Smuzhiyun #define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6) 495*4882a593Smuzhiyun #define DL_2_VOICE_MODE_CTL_PRE_SFT 5 496*4882a593Smuzhiyun #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1 497*4882a593Smuzhiyun #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5) 498*4882a593Smuzhiyun #define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4 499*4882a593Smuzhiyun #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1 500*4882a593Smuzhiyun #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4) 501*4882a593Smuzhiyun #define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3 502*4882a593Smuzhiyun #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1 503*4882a593Smuzhiyun #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3) 504*4882a593Smuzhiyun #define DL_2_IIR_ON_CTL_PRE_SFT 2 505*4882a593Smuzhiyun #define DL_2_IIR_ON_CTL_PRE_MASK 0x1 506*4882a593Smuzhiyun #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2) 507*4882a593Smuzhiyun #define DL_2_GAIN_ON_CTL_PRE_SFT 1 508*4882a593Smuzhiyun #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1 509*4882a593Smuzhiyun #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1) 510*4882a593Smuzhiyun #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0 511*4882a593Smuzhiyun #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1 512*4882a593Smuzhiyun #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0) 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun /* AFE_ADDA_DL_SRC2_CON1 */ 515*4882a593Smuzhiyun #define DL_2_GAIN_CTL_PRE_SFT 16 516*4882a593Smuzhiyun #define DL_2_GAIN_CTL_PRE_MASK 0xffff 517*4882a593Smuzhiyun #define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16) 518*4882a593Smuzhiyun #define DL_2_GAIN_MODE_CTL_SFT 0 519*4882a593Smuzhiyun #define DL_2_GAIN_MODE_CTL_MASK 0x1 520*4882a593Smuzhiyun #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0) 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun /* AFE_ADDA_UL_SRC_CON0 */ 523*4882a593Smuzhiyun #define C_COMB_OUT_SIN_GEN_CTL_SFT 31 524*4882a593Smuzhiyun #define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1 525*4882a593Smuzhiyun #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31) 526*4882a593Smuzhiyun #define C_BASEBAND_SIN_GEN_CTL_SFT 30 527*4882a593Smuzhiyun #define C_BASEBAND_SIN_GEN_CTL_MASK 0x1 528*4882a593Smuzhiyun #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30) 529*4882a593Smuzhiyun #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT 27 530*4882a593Smuzhiyun #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7 531*4882a593Smuzhiyun #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 27) 532*4882a593Smuzhiyun #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT 24 533*4882a593Smuzhiyun #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7 534*4882a593Smuzhiyun #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 24) 535*4882a593Smuzhiyun #define C_TWO_DIGITAL_MIC_CTL_SFT 23 536*4882a593Smuzhiyun #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1 537*4882a593Smuzhiyun #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23) 538*4882a593Smuzhiyun #define UL_MODE_3P25M_CH2_CTL_SFT 22 539*4882a593Smuzhiyun #define UL_MODE_3P25M_CH2_CTL_MASK 0x1 540*4882a593Smuzhiyun #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22) 541*4882a593Smuzhiyun #define UL_MODE_3P25M_CH1_CTL_SFT 21 542*4882a593Smuzhiyun #define UL_MODE_3P25M_CH1_CTL_MASK 0x1 543*4882a593Smuzhiyun #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21) 544*4882a593Smuzhiyun #define UL_SRC_USE_CIC_OUT_CTL_SFT 20 545*4882a593Smuzhiyun #define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1 546*4882a593Smuzhiyun #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20) 547*4882a593Smuzhiyun #define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17 548*4882a593Smuzhiyun #define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7 549*4882a593Smuzhiyun #define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17) 550*4882a593Smuzhiyun #define DMIC_LOW_POWER_MODE_CTL_SFT 14 551*4882a593Smuzhiyun #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3 552*4882a593Smuzhiyun #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14) 553*4882a593Smuzhiyun #define DMIC_48K_SEL_CTL_SFT 13 554*4882a593Smuzhiyun #define DMIC_48K_SEL_CTL_MASK 0x1 555*4882a593Smuzhiyun #define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13) 556*4882a593Smuzhiyun #define UL_DISABLE_HW_CG_CTL_SFT 12 557*4882a593Smuzhiyun #define UL_DISABLE_HW_CG_CTL_MASK 0x1 558*4882a593Smuzhiyun #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12) 559*4882a593Smuzhiyun #define UL_IIR_ON_TMP_CTL_SFT 10 560*4882a593Smuzhiyun #define UL_IIR_ON_TMP_CTL_MASK 0x1 561*4882a593Smuzhiyun #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10) 562*4882a593Smuzhiyun #define UL_IIRMODE_CTL_SFT 7 563*4882a593Smuzhiyun #define UL_IIRMODE_CTL_MASK 0x7 564*4882a593Smuzhiyun #define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7) 565*4882a593Smuzhiyun #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5 566*4882a593Smuzhiyun #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1 567*4882a593Smuzhiyun #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5) 568*4882a593Smuzhiyun #define AGC_260K_SEL_CH2_CTL_SFT 4 569*4882a593Smuzhiyun #define AGC_260K_SEL_CH2_CTL_MASK 0x1 570*4882a593Smuzhiyun #define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4) 571*4882a593Smuzhiyun #define AGC_260K_SEL_CH1_CTL_SFT 3 572*4882a593Smuzhiyun #define AGC_260K_SEL_CH1_CTL_MASK 0x1 573*4882a593Smuzhiyun #define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3) 574*4882a593Smuzhiyun #define UL_LOOP_BACK_MODE_CTL_SFT 2 575*4882a593Smuzhiyun #define UL_LOOP_BACK_MODE_CTL_MASK 0x1 576*4882a593Smuzhiyun #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2) 577*4882a593Smuzhiyun #define UL_SDM_3_LEVEL_CTL_SFT 1 578*4882a593Smuzhiyun #define UL_SDM_3_LEVEL_CTL_MASK 0x1 579*4882a593Smuzhiyun #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1) 580*4882a593Smuzhiyun #define UL_SRC_ON_TMP_CTL_SFT 0 581*4882a593Smuzhiyun #define UL_SRC_ON_TMP_CTL_MASK 0x1 582*4882a593Smuzhiyun #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0) 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun /* AFE_ADDA_UL_SRC_CON1 */ 585*4882a593Smuzhiyun #define C_SDM_RESET_CTL_SFT 31 586*4882a593Smuzhiyun #define C_SDM_RESET_CTL_MASK 0x1 587*4882a593Smuzhiyun #define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31) 588*4882a593Smuzhiyun #define ADITHON_CTL_SFT 30 589*4882a593Smuzhiyun #define ADITHON_CTL_MASK 0x1 590*4882a593Smuzhiyun #define ADITHON_CTL_MASK_SFT (0x1 << 30) 591*4882a593Smuzhiyun #define ADITHVAL_CTL_SFT 28 592*4882a593Smuzhiyun #define ADITHVAL_CTL_MASK 0x3 593*4882a593Smuzhiyun #define ADITHVAL_CTL_MASK_SFT (0x3 << 28) 594*4882a593Smuzhiyun #define C_DAC_EN_CTL_SFT 27 595*4882a593Smuzhiyun #define C_DAC_EN_CTL_MASK 0x1 596*4882a593Smuzhiyun #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27) 597*4882a593Smuzhiyun #define C_MUTE_SW_CTL_SFT 26 598*4882a593Smuzhiyun #define C_MUTE_SW_CTL_MASK 0x1 599*4882a593Smuzhiyun #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26) 600*4882a593Smuzhiyun #define ASDM_SRC_SEL_CTL_SFT 25 601*4882a593Smuzhiyun #define ASDM_SRC_SEL_CTL_MASK 0x1 602*4882a593Smuzhiyun #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25) 603*4882a593Smuzhiyun #define C_AMP_DIV_CH2_CTL_SFT 21 604*4882a593Smuzhiyun #define C_AMP_DIV_CH2_CTL_MASK 0x7 605*4882a593Smuzhiyun #define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21) 606*4882a593Smuzhiyun #define C_FREQ_DIV_CH2_CTL_SFT 16 607*4882a593Smuzhiyun #define C_FREQ_DIV_CH2_CTL_MASK 0x1f 608*4882a593Smuzhiyun #define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16) 609*4882a593Smuzhiyun #define C_SINE_MODE_CH2_CTL_SFT 12 610*4882a593Smuzhiyun #define C_SINE_MODE_CH2_CTL_MASK 0xf 611*4882a593Smuzhiyun #define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12) 612*4882a593Smuzhiyun #define C_AMP_DIV_CH1_CTL_SFT 9 613*4882a593Smuzhiyun #define C_AMP_DIV_CH1_CTL_MASK 0x7 614*4882a593Smuzhiyun #define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9) 615*4882a593Smuzhiyun #define C_FREQ_DIV_CH1_CTL_SFT 4 616*4882a593Smuzhiyun #define C_FREQ_DIV_CH1_CTL_MASK 0x1f 617*4882a593Smuzhiyun #define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4) 618*4882a593Smuzhiyun #define C_SINE_MODE_CH1_CTL_SFT 0 619*4882a593Smuzhiyun #define C_SINE_MODE_CH1_CTL_MASK 0xf 620*4882a593Smuzhiyun #define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0) 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun /* AFE_ADDA_TOP_CON0 */ 623*4882a593Smuzhiyun #define C_LOOP_BACK_MODE_CTL_SFT 12 624*4882a593Smuzhiyun #define C_LOOP_BACK_MODE_CTL_MASK 0xf 625*4882a593Smuzhiyun #define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12) 626*4882a593Smuzhiyun #define C_EXT_ADC_CTL_SFT 0 627*4882a593Smuzhiyun #define C_EXT_ADC_CTL_MASK 0x1 628*4882a593Smuzhiyun #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0) 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun /* AFE_ADDA_UL_DL_CON0 */ 631*4882a593Smuzhiyun #define AFE_UL_DL_CON0_RESERVED_SFT 1 632*4882a593Smuzhiyun #define AFE_UL_DL_CON0_RESERVED_MASK 0x3fff 633*4882a593Smuzhiyun #define AFE_UL_DL_CON0_RESERVED_MASK_SFT (0x3fff << 1) 634*4882a593Smuzhiyun #define ADDA_AFE_ON_SFT 0 635*4882a593Smuzhiyun #define ADDA_AFE_ON_MASK 0x1 636*4882a593Smuzhiyun #define ADDA_AFE_ON_MASK_SFT (0x1 << 0) 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun /* AFE_IRQ_MCU_CON */ 639*4882a593Smuzhiyun #define IRQ7_MCU_MODE_SFT 24 640*4882a593Smuzhiyun #define IRQ7_MCU_MODE_MASK 0xf 641*4882a593Smuzhiyun #define IRQ7_MCU_MODE_MASK_SFT (0xf << 24) 642*4882a593Smuzhiyun #define IRQ4_MCU_MODE_SFT 20 643*4882a593Smuzhiyun #define IRQ4_MCU_MODE_MASK 0xf 644*4882a593Smuzhiyun #define IRQ4_MCU_MODE_MASK_SFT (0xf << 20) 645*4882a593Smuzhiyun #define IRQ3_MCU_MODE_SFT 16 646*4882a593Smuzhiyun #define IRQ3_MCU_MODE_MASK 0xf 647*4882a593Smuzhiyun #define IRQ3_MCU_MODE_MASK_SFT (0xf << 16) 648*4882a593Smuzhiyun #define IRQ7_MCU_ON_SFT 14 649*4882a593Smuzhiyun #define IRQ7_MCU_ON_MASK 0x1 650*4882a593Smuzhiyun #define IRQ7_MCU_ON_MASK_SFT (0x1 << 14) 651*4882a593Smuzhiyun #define IRQ5_MCU_ON_SFT 12 652*4882a593Smuzhiyun #define IRQ5_MCU_ON_MASK 0x1 653*4882a593Smuzhiyun #define IRQ5_MCU_ON_MASK_SFT (0x1 << 12) 654*4882a593Smuzhiyun #define IRQ2_MCU_MODE_SFT 8 655*4882a593Smuzhiyun #define IRQ2_MCU_MODE_MASK 0xf 656*4882a593Smuzhiyun #define IRQ2_MCU_MODE_MASK_SFT (0xf << 8) 657*4882a593Smuzhiyun #define IRQ1_MCU_MODE_SFT 4 658*4882a593Smuzhiyun #define IRQ1_MCU_MODE_MASK 0xf 659*4882a593Smuzhiyun #define IRQ1_MCU_MODE_MASK_SFT (0xf << 4) 660*4882a593Smuzhiyun #define IRQ4_MCU_ON_SFT 3 661*4882a593Smuzhiyun #define IRQ4_MCU_ON_MASK 0x1 662*4882a593Smuzhiyun #define IRQ4_MCU_ON_MASK_SFT (0x1 << 3) 663*4882a593Smuzhiyun #define IRQ3_MCU_ON_SFT 2 664*4882a593Smuzhiyun #define IRQ3_MCU_ON_MASK 0x1 665*4882a593Smuzhiyun #define IRQ3_MCU_ON_MASK_SFT (0x1 << 2) 666*4882a593Smuzhiyun #define IRQ2_MCU_ON_SFT 1 667*4882a593Smuzhiyun #define IRQ2_MCU_ON_MASK 0x1 668*4882a593Smuzhiyun #define IRQ2_MCU_ON_MASK_SFT (0x1 << 1) 669*4882a593Smuzhiyun #define IRQ1_MCU_ON_SFT 0 670*4882a593Smuzhiyun #define IRQ1_MCU_ON_MASK 0x1 671*4882a593Smuzhiyun #define IRQ1_MCU_ON_MASK_SFT (0x1 << 0) 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun /* AFE_IRQ_MCU_EN */ 674*4882a593Smuzhiyun #define AFE_IRQ_CM4_EN_SFT 16 675*4882a593Smuzhiyun #define AFE_IRQ_CM4_EN_MASK 0x7f 676*4882a593Smuzhiyun #define AFE_IRQ_CM4_EN_MASK_SFT (0x7f << 16) 677*4882a593Smuzhiyun #define AFE_IRQ_MD32_EN_SFT 8 678*4882a593Smuzhiyun #define AFE_IRQ_MD32_EN_MASK 0x7f 679*4882a593Smuzhiyun #define AFE_IRQ_MD32_EN_MASK_SFT (0x7f << 8) 680*4882a593Smuzhiyun #define AFE_IRQ_MCU_EN_SFT 0 681*4882a593Smuzhiyun #define AFE_IRQ_MCU_EN_MASK 0x7f 682*4882a593Smuzhiyun #define AFE_IRQ_MCU_EN_MASK_SFT (0x7f << 0) 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun /* AFE_IRQ_MCU_CLR */ 685*4882a593Smuzhiyun #define IRQ7_MCU_CLR_SFT 6 686*4882a593Smuzhiyun #define IRQ7_MCU_CLR_MASK 0x1 687*4882a593Smuzhiyun #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6) 688*4882a593Smuzhiyun #define IRQ5_MCU_CLR_SFT 4 689*4882a593Smuzhiyun #define IRQ5_MCU_CLR_MASK 0x1 690*4882a593Smuzhiyun #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4) 691*4882a593Smuzhiyun #define IRQ4_MCU_CLR_SFT 3 692*4882a593Smuzhiyun #define IRQ4_MCU_CLR_MASK 0x1 693*4882a593Smuzhiyun #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3) 694*4882a593Smuzhiyun #define IRQ3_MCU_CLR_SFT 2 695*4882a593Smuzhiyun #define IRQ3_MCU_CLR_MASK 0x1 696*4882a593Smuzhiyun #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2) 697*4882a593Smuzhiyun #define IRQ2_MCU_CLR_SFT 1 698*4882a593Smuzhiyun #define IRQ2_MCU_CLR_MASK 0x1 699*4882a593Smuzhiyun #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1) 700*4882a593Smuzhiyun #define IRQ1_MCU_CLR_SFT 0 701*4882a593Smuzhiyun #define IRQ1_MCU_CLR_MASK 0x1 702*4882a593Smuzhiyun #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0) 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun /* AFE_IRQ_MCU_CNT1 */ 705*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT1_SFT 0 706*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT1_MASK 0x3ffff 707*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT1_MASK_SFT (0x3ffff << 0) 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun /* AFE_IRQ_MCU_CNT2 */ 710*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT2_SFT 0 711*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT2_MASK 0x3ffff 712*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT2_MASK_SFT (0x3ffff << 0) 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun /* AFE_IRQ_MCU_CNT3 */ 715*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT3_SFT 0 716*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT3_MASK 0x3ffff 717*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT3_MASK_SFT (0x3ffff << 0) 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun /* AFE_IRQ_MCU_CNT4 */ 720*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT4_SFT 0 721*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT4_MASK 0x3ffff 722*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT4_MASK_SFT (0x3ffff << 0) 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun /* AFE_IRQ_MCU_CNT5 */ 725*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT5_SFT 0 726*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT5_MASK 0x3ffff 727*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT5_MASK_SFT (0x3ffff << 0) 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun /* AFE_IRQ_MCU_CNT7 */ 730*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT7_SFT 0 731*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT7_MASK 0x3ffff 732*4882a593Smuzhiyun #define AFE_IRQ_MCU_CNT7_MASK_SFT (0x3ffff << 0) 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun /* AFE_MEMIF_MSB */ 735*4882a593Smuzhiyun #define CPU_COMPACT_MODE_SFT 23 736*4882a593Smuzhiyun #define CPU_COMPACT_MODE_MASK 0x1 737*4882a593Smuzhiyun #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23) 738*4882a593Smuzhiyun #define CPU_HD_ALIGN_SFT 22 739*4882a593Smuzhiyun #define CPU_HD_ALIGN_MASK 0x1 740*4882a593Smuzhiyun #define CPU_HD_ALIGN_MASK_SFT (0x1 << 22) 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun /* AFE_MEMIF_HD_MODE */ 743*4882a593Smuzhiyun #define HDMI_HD_SFT 20 744*4882a593Smuzhiyun #define HDMI_HD_MASK 0x3 745*4882a593Smuzhiyun #define HDMI_HD_MASK_SFT (0x3 << 20) 746*4882a593Smuzhiyun #define MOD_DAI_HD_SFT 18 747*4882a593Smuzhiyun #define MOD_DAI_HD_MASK 0x3 748*4882a593Smuzhiyun #define MOD_DAI_HD_MASK_SFT (0x3 << 18) 749*4882a593Smuzhiyun #define DAI_HD_SFT 16 750*4882a593Smuzhiyun #define DAI_HD_MASK 0x3 751*4882a593Smuzhiyun #define DAI_HD_MASK_SFT (0x3 << 16) 752*4882a593Smuzhiyun #define VUL_DATA2_HD_SFT 12 753*4882a593Smuzhiyun #define VUL_DATA2_HD_MASK 0x3 754*4882a593Smuzhiyun #define VUL_DATA2_HD_MASK_SFT (0x3 << 12) 755*4882a593Smuzhiyun #define VUL_HD_SFT 10 756*4882a593Smuzhiyun #define VUL_HD_MASK 0x3 757*4882a593Smuzhiyun #define VUL_HD_MASK_SFT (0x3 << 10) 758*4882a593Smuzhiyun #define AWB_HD_SFT 8 759*4882a593Smuzhiyun #define AWB_HD_MASK 0x3 760*4882a593Smuzhiyun #define AWB_HD_MASK_SFT (0x3 << 8) 761*4882a593Smuzhiyun #define DL3_HD_SFT 6 762*4882a593Smuzhiyun #define DL3_HD_MASK 0x3 763*4882a593Smuzhiyun #define DL3_HD_MASK_SFT (0x3 << 6) 764*4882a593Smuzhiyun #define DL2_HD_SFT 4 765*4882a593Smuzhiyun #define DL2_HD_MASK 0x3 766*4882a593Smuzhiyun #define DL2_HD_MASK_SFT (0x3 << 4) 767*4882a593Smuzhiyun #define DL1_DATA2_HD_SFT 2 768*4882a593Smuzhiyun #define DL1_DATA2_HD_MASK 0x3 769*4882a593Smuzhiyun #define DL1_DATA2_HD_MASK_SFT (0x3 << 2) 770*4882a593Smuzhiyun #define DL1_HD_SFT 0 771*4882a593Smuzhiyun #define DL1_HD_MASK 0x3 772*4882a593Smuzhiyun #define DL1_HD_MASK_SFT (0x3 << 0) 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun /* AFE_MEMIF_HDALIGN */ 775*4882a593Smuzhiyun #define HDMI_NORMAL_MODE_SFT 26 776*4882a593Smuzhiyun #define HDMI_NORMAL_MODE_MASK 0x1 777*4882a593Smuzhiyun #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26) 778*4882a593Smuzhiyun #define MOD_DAI_NORMAL_MODE_SFT 25 779*4882a593Smuzhiyun #define MOD_DAI_NORMAL_MODE_MASK 0x1 780*4882a593Smuzhiyun #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25) 781*4882a593Smuzhiyun #define DAI_NORMAL_MODE_SFT 24 782*4882a593Smuzhiyun #define DAI_NORMAL_MODE_MASK 0x1 783*4882a593Smuzhiyun #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24) 784*4882a593Smuzhiyun #define VUL_DATA2_NORMAL_MODE_SFT 22 785*4882a593Smuzhiyun #define VUL_DATA2_NORMAL_MODE_MASK 0x1 786*4882a593Smuzhiyun #define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22) 787*4882a593Smuzhiyun #define VUL_NORMAL_MODE_SFT 21 788*4882a593Smuzhiyun #define VUL_NORMAL_MODE_MASK 0x1 789*4882a593Smuzhiyun #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21) 790*4882a593Smuzhiyun #define AWB_NORMAL_MODE_SFT 20 791*4882a593Smuzhiyun #define AWB_NORMAL_MODE_MASK 0x1 792*4882a593Smuzhiyun #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20) 793*4882a593Smuzhiyun #define DL3_NORMAL_MODE_SFT 19 794*4882a593Smuzhiyun #define DL3_NORMAL_MODE_MASK 0x1 795*4882a593Smuzhiyun #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19) 796*4882a593Smuzhiyun #define DL2_NORMAL_MODE_SFT 18 797*4882a593Smuzhiyun #define DL2_NORMAL_MODE_MASK 0x1 798*4882a593Smuzhiyun #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18) 799*4882a593Smuzhiyun #define DL1_DATA2_NORMAL_MODE_SFT 17 800*4882a593Smuzhiyun #define DL1_DATA2_NORMAL_MODE_MASK 0x1 801*4882a593Smuzhiyun #define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17) 802*4882a593Smuzhiyun #define DL1_NORMAL_MODE_SFT 16 803*4882a593Smuzhiyun #define DL1_NORMAL_MODE_MASK 0x1 804*4882a593Smuzhiyun #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16) 805*4882a593Smuzhiyun #define HDMI_HD_ALIGN_SFT 10 806*4882a593Smuzhiyun #define HDMI_HD_ALIGN_MASK 0x1 807*4882a593Smuzhiyun #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10) 808*4882a593Smuzhiyun #define MOD_DAI_HD_ALIGN_SFT 9 809*4882a593Smuzhiyun #define MOD_DAI_HD_ALIGN_MASK 0x1 810*4882a593Smuzhiyun #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9) 811*4882a593Smuzhiyun #define DAI_ALIGN_SFT 8 812*4882a593Smuzhiyun #define DAI_ALIGN_MASK 0x1 813*4882a593Smuzhiyun #define DAI_ALIGN_MASK_SFT (0x1 << 8) 814*4882a593Smuzhiyun #define VUL2_HD_ALIGN_SFT 7 815*4882a593Smuzhiyun #define VUL2_HD_ALIGN_MASK 0x1 816*4882a593Smuzhiyun #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7) 817*4882a593Smuzhiyun #define VUL_DATA2_HD_ALIGN_SFT 6 818*4882a593Smuzhiyun #define VUL_DATA2_HD_ALIGN_MASK 0x1 819*4882a593Smuzhiyun #define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6) 820*4882a593Smuzhiyun #define VUL_HD_ALIGN_SFT 5 821*4882a593Smuzhiyun #define VUL_HD_ALIGN_MASK 0x1 822*4882a593Smuzhiyun #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5) 823*4882a593Smuzhiyun #define AWB_HD_ALIGN_SFT 4 824*4882a593Smuzhiyun #define AWB_HD_ALIGN_MASK 0x1 825*4882a593Smuzhiyun #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4) 826*4882a593Smuzhiyun #define DL3_HD_ALIGN_SFT 3 827*4882a593Smuzhiyun #define DL3_HD_ALIGN_MASK 0x1 828*4882a593Smuzhiyun #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3) 829*4882a593Smuzhiyun #define DL2_HD_ALIGN_SFT 2 830*4882a593Smuzhiyun #define DL2_HD_ALIGN_MASK 0x1 831*4882a593Smuzhiyun #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2) 832*4882a593Smuzhiyun #define DL1_DATA2_HD_ALIGN_SFT 1 833*4882a593Smuzhiyun #define DL1_DATA2_HD_ALIGN_MASK 0x1 834*4882a593Smuzhiyun #define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1) 835*4882a593Smuzhiyun #define DL1_HD_ALIGN_SFT 0 836*4882a593Smuzhiyun #define DL1_HD_ALIGN_MASK 0x1 837*4882a593Smuzhiyun #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0) 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun /* PCM_INTF_CON1 */ 840*4882a593Smuzhiyun #define PCM_FIX_VALUE_SEL_SFT 31 841*4882a593Smuzhiyun #define PCM_FIX_VALUE_SEL_MASK 0x1 842*4882a593Smuzhiyun #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31) 843*4882a593Smuzhiyun #define PCM_BUFFER_LOOPBACK_SFT 30 844*4882a593Smuzhiyun #define PCM_BUFFER_LOOPBACK_MASK 0x1 845*4882a593Smuzhiyun #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30) 846*4882a593Smuzhiyun #define PCM_PARALLEL_LOOPBACK_SFT 29 847*4882a593Smuzhiyun #define PCM_PARALLEL_LOOPBACK_MASK 0x1 848*4882a593Smuzhiyun #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29) 849*4882a593Smuzhiyun #define PCM_SERIAL_LOOPBACK_SFT 28 850*4882a593Smuzhiyun #define PCM_SERIAL_LOOPBACK_MASK 0x1 851*4882a593Smuzhiyun #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28) 852*4882a593Smuzhiyun #define PCM_DAI_PCM_LOOPBACK_SFT 27 853*4882a593Smuzhiyun #define PCM_DAI_PCM_LOOPBACK_MASK 0x1 854*4882a593Smuzhiyun #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27) 855*4882a593Smuzhiyun #define PCM_I2S_PCM_LOOPBACK_SFT 26 856*4882a593Smuzhiyun #define PCM_I2S_PCM_LOOPBACK_MASK 0x1 857*4882a593Smuzhiyun #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26) 858*4882a593Smuzhiyun #define PCM_SYNC_DELSEL_SFT 25 859*4882a593Smuzhiyun #define PCM_SYNC_DELSEL_MASK 0x1 860*4882a593Smuzhiyun #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25) 861*4882a593Smuzhiyun #define PCM_TX_LR_SWAP_SFT 24 862*4882a593Smuzhiyun #define PCM_TX_LR_SWAP_MASK 0x1 863*4882a593Smuzhiyun #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24) 864*4882a593Smuzhiyun #define PCM_SYNC_OUT_INV_SFT 23 865*4882a593Smuzhiyun #define PCM_SYNC_OUT_INV_MASK 0x1 866*4882a593Smuzhiyun #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23) 867*4882a593Smuzhiyun #define PCM_BCLK_OUT_INV_SFT 22 868*4882a593Smuzhiyun #define PCM_BCLK_OUT_INV_MASK 0x1 869*4882a593Smuzhiyun #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22) 870*4882a593Smuzhiyun #define PCM_SYNC_IN_INV_SFT 21 871*4882a593Smuzhiyun #define PCM_SYNC_IN_INV_MASK 0x1 872*4882a593Smuzhiyun #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21) 873*4882a593Smuzhiyun #define PCM_BCLK_IN_INV_SFT 20 874*4882a593Smuzhiyun #define PCM_BCLK_IN_INV_MASK 0x1 875*4882a593Smuzhiyun #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20) 876*4882a593Smuzhiyun #define PCM_TX_LCH_RPT_SFT 19 877*4882a593Smuzhiyun #define PCM_TX_LCH_RPT_MASK 0x1 878*4882a593Smuzhiyun #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19) 879*4882a593Smuzhiyun #define PCM_VBT_16K_MODE_SFT 18 880*4882a593Smuzhiyun #define PCM_VBT_16K_MODE_MASK 0x1 881*4882a593Smuzhiyun #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18) 882*4882a593Smuzhiyun #define PCM_EXT_MODEM_SFT 17 883*4882a593Smuzhiyun #define PCM_EXT_MODEM_MASK 0x1 884*4882a593Smuzhiyun #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17) 885*4882a593Smuzhiyun #define PCM_24BIT_SFT 16 886*4882a593Smuzhiyun #define PCM_24BIT_MASK 0x1 887*4882a593Smuzhiyun #define PCM_24BIT_MASK_SFT (0x1 << 16) 888*4882a593Smuzhiyun #define PCM_WLEN_SFT 14 889*4882a593Smuzhiyun #define PCM_WLEN_MASK 0x3 890*4882a593Smuzhiyun #define PCM_WLEN_MASK_SFT (0x3 << 14) 891*4882a593Smuzhiyun #define PCM_SYNC_LENGTH_SFT 9 892*4882a593Smuzhiyun #define PCM_SYNC_LENGTH_MASK 0x1f 893*4882a593Smuzhiyun #define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9) 894*4882a593Smuzhiyun #define PCM_SYNC_TYPE_SFT 8 895*4882a593Smuzhiyun #define PCM_SYNC_TYPE_MASK 0x1 896*4882a593Smuzhiyun #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8) 897*4882a593Smuzhiyun #define PCM_BT_MODE_SFT 7 898*4882a593Smuzhiyun #define PCM_BT_MODE_MASK 0x1 899*4882a593Smuzhiyun #define PCM_BT_MODE_MASK_SFT (0x1 << 7) 900*4882a593Smuzhiyun #define PCM_BYP_ASRC_SFT 6 901*4882a593Smuzhiyun #define PCM_BYP_ASRC_MASK 0x1 902*4882a593Smuzhiyun #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6) 903*4882a593Smuzhiyun #define PCM_SLAVE_SFT 5 904*4882a593Smuzhiyun #define PCM_SLAVE_MASK 0x1 905*4882a593Smuzhiyun #define PCM_SLAVE_MASK_SFT (0x1 << 5) 906*4882a593Smuzhiyun #define PCM_MODE_SFT 3 907*4882a593Smuzhiyun #define PCM_MODE_MASK 0x3 908*4882a593Smuzhiyun #define PCM_MODE_MASK_SFT (0x3 << 3) 909*4882a593Smuzhiyun #define PCM_FMT_SFT 1 910*4882a593Smuzhiyun #define PCM_FMT_MASK 0x3 911*4882a593Smuzhiyun #define PCM_FMT_MASK_SFT (0x3 << 1) 912*4882a593Smuzhiyun #define PCM_EN_SFT 0 913*4882a593Smuzhiyun #define PCM_EN_MASK 0x1 914*4882a593Smuzhiyun #define PCM_EN_MASK_SFT (0x1 << 0) 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun /* PCM_INTF_CON2 */ 917*4882a593Smuzhiyun #define PCM1_TX_FIFO_OV_SFT 31 918*4882a593Smuzhiyun #define PCM1_TX_FIFO_OV_MASK 0x1 919*4882a593Smuzhiyun #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31) 920*4882a593Smuzhiyun #define PCM1_RX_FIFO_OV_SFT 30 921*4882a593Smuzhiyun #define PCM1_RX_FIFO_OV_MASK 0x1 922*4882a593Smuzhiyun #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30) 923*4882a593Smuzhiyun #define PCM2_TX_FIFO_OV_SFT 29 924*4882a593Smuzhiyun #define PCM2_TX_FIFO_OV_MASK 0x1 925*4882a593Smuzhiyun #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29) 926*4882a593Smuzhiyun #define PCM2_RX_FIFO_OV_SFT 28 927*4882a593Smuzhiyun #define PCM2_RX_FIFO_OV_MASK 0x1 928*4882a593Smuzhiyun #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28) 929*4882a593Smuzhiyun #define PCM1_SYNC_GLITCH_SFT 27 930*4882a593Smuzhiyun #define PCM1_SYNC_GLITCH_MASK 0x1 931*4882a593Smuzhiyun #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27) 932*4882a593Smuzhiyun #define PCM2_SYNC_GLITCH_SFT 26 933*4882a593Smuzhiyun #define PCM2_SYNC_GLITCH_MASK 0x1 934*4882a593Smuzhiyun #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26) 935*4882a593Smuzhiyun #define PCM1_PCM2_LOOPBACK_SFT 15 936*4882a593Smuzhiyun #define PCM1_PCM2_LOOPBACK_MASK 0x1 937*4882a593Smuzhiyun #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15) 938*4882a593Smuzhiyun #define DAI_PCM_LOOPBACK_CH_SFT 13 939*4882a593Smuzhiyun #define DAI_PCM_LOOPBACK_CH_MASK 0x1 940*4882a593Smuzhiyun #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13) 941*4882a593Smuzhiyun #define I2S_PCM_LOOPBACK_CH_SFT 12 942*4882a593Smuzhiyun #define I2S_PCM_LOOPBACK_CH_MASK 0x1 943*4882a593Smuzhiyun #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12) 944*4882a593Smuzhiyun #define PCM_USE_MD3_SFT 8 945*4882a593Smuzhiyun #define PCM_USE_MD3_MASK 0x1 946*4882a593Smuzhiyun #define PCM_USE_MD3_MASK_SFT (0x1 << 8) 947*4882a593Smuzhiyun #define TX_FIX_VALUE_SFT 0 948*4882a593Smuzhiyun #define TX_FIX_VALUE_MASK 0xff 949*4882a593Smuzhiyun #define TX_FIX_VALUE_MASK_SFT (0xff << 0) 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun /* PCM2_INTF_CON */ 952*4882a593Smuzhiyun #define PCM2_TX_FIX_VALUE_SFT 24 953*4882a593Smuzhiyun #define PCM2_TX_FIX_VALUE_MASK 0xff 954*4882a593Smuzhiyun #define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24) 955*4882a593Smuzhiyun #define PCM2_FIX_VALUE_SEL_SFT 23 956*4882a593Smuzhiyun #define PCM2_FIX_VALUE_SEL_MASK 0x1 957*4882a593Smuzhiyun #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23) 958*4882a593Smuzhiyun #define PCM2_BUFFER_LOOPBACK_SFT 22 959*4882a593Smuzhiyun #define PCM2_BUFFER_LOOPBACK_MASK 0x1 960*4882a593Smuzhiyun #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22) 961*4882a593Smuzhiyun #define PCM2_PARALLEL_LOOPBACK_SFT 21 962*4882a593Smuzhiyun #define PCM2_PARALLEL_LOOPBACK_MASK 0x1 963*4882a593Smuzhiyun #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21) 964*4882a593Smuzhiyun #define PCM2_SERIAL_LOOPBACK_SFT 20 965*4882a593Smuzhiyun #define PCM2_SERIAL_LOOPBACK_MASK 0x1 966*4882a593Smuzhiyun #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20) 967*4882a593Smuzhiyun #define PCM2_DAI_PCM_LOOPBACK_SFT 19 968*4882a593Smuzhiyun #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1 969*4882a593Smuzhiyun #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19) 970*4882a593Smuzhiyun #define PCM2_I2S_PCM_LOOPBACK_SFT 18 971*4882a593Smuzhiyun #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1 972*4882a593Smuzhiyun #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18) 973*4882a593Smuzhiyun #define PCM2_SYNC_DELSEL_SFT 17 974*4882a593Smuzhiyun #define PCM2_SYNC_DELSEL_MASK 0x1 975*4882a593Smuzhiyun #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17) 976*4882a593Smuzhiyun #define PCM2_TX_LR_SWAP_SFT 16 977*4882a593Smuzhiyun #define PCM2_TX_LR_SWAP_MASK 0x1 978*4882a593Smuzhiyun #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16) 979*4882a593Smuzhiyun #define PCM2_SYNC_IN_INV_SFT 15 980*4882a593Smuzhiyun #define PCM2_SYNC_IN_INV_MASK 0x1 981*4882a593Smuzhiyun #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15) 982*4882a593Smuzhiyun #define PCM2_BCLK_IN_INV_SFT 14 983*4882a593Smuzhiyun #define PCM2_BCLK_IN_INV_MASK 0x1 984*4882a593Smuzhiyun #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14) 985*4882a593Smuzhiyun #define PCM2_TX_LCH_RPT_SFT 13 986*4882a593Smuzhiyun #define PCM2_TX_LCH_RPT_MASK 0x1 987*4882a593Smuzhiyun #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13) 988*4882a593Smuzhiyun #define PCM2_VBT_16K_MODE_SFT 12 989*4882a593Smuzhiyun #define PCM2_VBT_16K_MODE_MASK 0x1 990*4882a593Smuzhiyun #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12) 991*4882a593Smuzhiyun #define PCM2_LOOPBACK_CH_SEL_SFT 10 992*4882a593Smuzhiyun #define PCM2_LOOPBACK_CH_SEL_MASK 0x3 993*4882a593Smuzhiyun #define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10) 994*4882a593Smuzhiyun #define PCM2_TX2_BT_MODE_SFT 8 995*4882a593Smuzhiyun #define PCM2_TX2_BT_MODE_MASK 0x1 996*4882a593Smuzhiyun #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8) 997*4882a593Smuzhiyun #define PCM2_BT_MODE_SFT 7 998*4882a593Smuzhiyun #define PCM2_BT_MODE_MASK 0x1 999*4882a593Smuzhiyun #define PCM2_BT_MODE_MASK_SFT (0x1 << 7) 1000*4882a593Smuzhiyun #define PCM2_AFIFO_SFT 6 1001*4882a593Smuzhiyun #define PCM2_AFIFO_MASK 0x1 1002*4882a593Smuzhiyun #define PCM2_AFIFO_MASK_SFT (0x1 << 6) 1003*4882a593Smuzhiyun #define PCM2_WLEN_SFT 5 1004*4882a593Smuzhiyun #define PCM2_WLEN_MASK 0x1 1005*4882a593Smuzhiyun #define PCM2_WLEN_MASK_SFT (0x1 << 5) 1006*4882a593Smuzhiyun #define PCM2_MODE_SFT 3 1007*4882a593Smuzhiyun #define PCM2_MODE_MASK 0x3 1008*4882a593Smuzhiyun #define PCM2_MODE_MASK_SFT (0x3 << 3) 1009*4882a593Smuzhiyun #define PCM2_FMT_SFT 1 1010*4882a593Smuzhiyun #define PCM2_FMT_MASK 0x3 1011*4882a593Smuzhiyun #define PCM2_FMT_MASK_SFT (0x3 << 1) 1012*4882a593Smuzhiyun #define PCM2_EN_SFT 0 1013*4882a593Smuzhiyun #define PCM2_EN_MASK 0x1 1014*4882a593Smuzhiyun #define PCM2_EN_MASK_SFT (0x1 << 0) 1015*4882a593Smuzhiyun #endif 1016