1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2008 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * Copyright 2008 Red Hat Inc. 4*4882a593Smuzhiyun * Copyright 2009 Jerome Glisse. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 7*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 8*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 9*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 11*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 14*4882a593Smuzhiyun * all copies or substantial portions of the Software. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * Authors: Dave Airlie 25*4882a593Smuzhiyun * Alex Deucher 26*4882a593Smuzhiyun * Jerome Glisse 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #ifndef __RS600D_H__ 29*4882a593Smuzhiyun #define __RS600D_H__ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* Registers */ 32*4882a593Smuzhiyun #define R_000040_GEN_INT_CNTL 0x000040 33*4882a593Smuzhiyun #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 34*4882a593Smuzhiyun #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 35*4882a593Smuzhiyun #define C_000040_SCRATCH_INT_MASK 0xFFFBFFFF 36*4882a593Smuzhiyun #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 37*4882a593Smuzhiyun #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 38*4882a593Smuzhiyun #define C_000040_GUI_IDLE_MASK 0xFFF7FFFF 39*4882a593Smuzhiyun #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 40*4882a593Smuzhiyun #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 41*4882a593Smuzhiyun #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF 42*4882a593Smuzhiyun #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 43*4882a593Smuzhiyun #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 44*4882a593Smuzhiyun #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF 45*4882a593Smuzhiyun #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 46*4882a593Smuzhiyun #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) 47*4882a593Smuzhiyun #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF 48*4882a593Smuzhiyun #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17) 49*4882a593Smuzhiyun #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1) 50*4882a593Smuzhiyun #define C_000040_I2C_INT_EN 0xFFFDFFFF 51*4882a593Smuzhiyun #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19) 52*4882a593Smuzhiyun #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1) 53*4882a593Smuzhiyun #define C_000040_GUI_IDLE 0xFFF7FFFF 54*4882a593Smuzhiyun #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24) 55*4882a593Smuzhiyun #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1) 56*4882a593Smuzhiyun #define C_000040_VIPH_INT_EN 0xFEFFFFFF 57*4882a593Smuzhiyun #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25) 58*4882a593Smuzhiyun #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1) 59*4882a593Smuzhiyun #define C_000040_SW_INT_EN 0xFDFFFFFF 60*4882a593Smuzhiyun #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27) 61*4882a593Smuzhiyun #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1) 62*4882a593Smuzhiyun #define C_000040_GEYSERVILLE 0xF7FFFFFF 63*4882a593Smuzhiyun #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28) 64*4882a593Smuzhiyun #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1) 65*4882a593Smuzhiyun #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF 66*4882a593Smuzhiyun #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29) 67*4882a593Smuzhiyun #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1) 68*4882a593Smuzhiyun #define C_000040_DVI_I2C_INT 0xDFFFFFFF 69*4882a593Smuzhiyun #define S_000040_GUIDMA(x) (((x) & 0x1) << 30) 70*4882a593Smuzhiyun #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1) 71*4882a593Smuzhiyun #define C_000040_GUIDMA 0xBFFFFFFF 72*4882a593Smuzhiyun #define S_000040_VIDDMA(x) (((x) & 0x1) << 31) 73*4882a593Smuzhiyun #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1) 74*4882a593Smuzhiyun #define C_000040_VIDDMA 0x7FFFFFFF 75*4882a593Smuzhiyun #define R_000044_GEN_INT_STATUS 0x000044 76*4882a593Smuzhiyun #define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0) 77*4882a593Smuzhiyun #define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1) 78*4882a593Smuzhiyun #define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE 79*4882a593Smuzhiyun #define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1) 80*4882a593Smuzhiyun #define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1) 81*4882a593Smuzhiyun #define C_000044_VGA_INT_STAT 0xFFFFFFFD 82*4882a593Smuzhiyun #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8) 83*4882a593Smuzhiyun #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1) 84*4882a593Smuzhiyun #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF 85*4882a593Smuzhiyun #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12) 86*4882a593Smuzhiyun #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1) 87*4882a593Smuzhiyun #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF 88*4882a593Smuzhiyun #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13) 89*4882a593Smuzhiyun #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1) 90*4882a593Smuzhiyun #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF 91*4882a593Smuzhiyun #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14) 92*4882a593Smuzhiyun #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1) 93*4882a593Smuzhiyun #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF 94*4882a593Smuzhiyun #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15) 95*4882a593Smuzhiyun #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1) 96*4882a593Smuzhiyun #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF 97*4882a593Smuzhiyun #define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16) 98*4882a593Smuzhiyun #define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1) 99*4882a593Smuzhiyun #define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF 100*4882a593Smuzhiyun #define S_000044_I2C_INT(x) (((x) & 0x1) << 17) 101*4882a593Smuzhiyun #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1) 102*4882a593Smuzhiyun #define C_000044_I2C_INT 0xFFFDFFFF 103*4882a593Smuzhiyun #define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18) 104*4882a593Smuzhiyun #define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1) 105*4882a593Smuzhiyun #define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF 106*4882a593Smuzhiyun #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19) 107*4882a593Smuzhiyun #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1) 108*4882a593Smuzhiyun #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF 109*4882a593Smuzhiyun #define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20) 110*4882a593Smuzhiyun #define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1) 111*4882a593Smuzhiyun #define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF 112*4882a593Smuzhiyun #define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21) 113*4882a593Smuzhiyun #define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1) 114*4882a593Smuzhiyun #define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF 115*4882a593Smuzhiyun #define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22) 116*4882a593Smuzhiyun #define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1) 117*4882a593Smuzhiyun #define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF 118*4882a593Smuzhiyun #define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23) 119*4882a593Smuzhiyun #define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1) 120*4882a593Smuzhiyun #define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF 121*4882a593Smuzhiyun #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24) 122*4882a593Smuzhiyun #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1) 123*4882a593Smuzhiyun #define C_000044_VIPH_INT 0xFEFFFFFF 124*4882a593Smuzhiyun #define S_000044_SW_INT(x) (((x) & 0x1) << 25) 125*4882a593Smuzhiyun #define G_000044_SW_INT(x) (((x) >> 25) & 0x1) 126*4882a593Smuzhiyun #define C_000044_SW_INT 0xFDFFFFFF 127*4882a593Smuzhiyun #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26) 128*4882a593Smuzhiyun #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1) 129*4882a593Smuzhiyun #define C_000044_SW_INT_SET 0xFBFFFFFF 130*4882a593Smuzhiyun #define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27) 131*4882a593Smuzhiyun #define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1) 132*4882a593Smuzhiyun #define C_000044_IDCT_INT_STAT 0xF7FFFFFF 133*4882a593Smuzhiyun #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30) 134*4882a593Smuzhiyun #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1) 135*4882a593Smuzhiyun #define C_000044_GUIDMA_STAT 0xBFFFFFFF 136*4882a593Smuzhiyun #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31) 137*4882a593Smuzhiyun #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1) 138*4882a593Smuzhiyun #define C_000044_VIDDMA_STAT 0x7FFFFFFF 139*4882a593Smuzhiyun #define R_00004C_BUS_CNTL 0x00004C 140*4882a593Smuzhiyun #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14) 141*4882a593Smuzhiyun #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1) 142*4882a593Smuzhiyun #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF 143*4882a593Smuzhiyun #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20) 144*4882a593Smuzhiyun #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1) 145*4882a593Smuzhiyun #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF 146*4882a593Smuzhiyun #define R_000070_MC_IND_INDEX 0x000070 147*4882a593Smuzhiyun #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0) 148*4882a593Smuzhiyun #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF) 149*4882a593Smuzhiyun #define C_000070_MC_IND_ADDR 0xFFFF0000 150*4882a593Smuzhiyun #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16) 151*4882a593Smuzhiyun #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1) 152*4882a593Smuzhiyun #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF 153*4882a593Smuzhiyun #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17) 154*4882a593Smuzhiyun #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1) 155*4882a593Smuzhiyun #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF 156*4882a593Smuzhiyun #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18) 157*4882a593Smuzhiyun #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1) 158*4882a593Smuzhiyun #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF 159*4882a593Smuzhiyun #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19) 160*4882a593Smuzhiyun #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1) 161*4882a593Smuzhiyun #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF 162*4882a593Smuzhiyun #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20) 163*4882a593Smuzhiyun #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1) 164*4882a593Smuzhiyun #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF 165*4882a593Smuzhiyun #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21) 166*4882a593Smuzhiyun #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1) 167*4882a593Smuzhiyun #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF 168*4882a593Smuzhiyun #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22) 169*4882a593Smuzhiyun #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1) 170*4882a593Smuzhiyun #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF 171*4882a593Smuzhiyun #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23) 172*4882a593Smuzhiyun #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1) 173*4882a593Smuzhiyun #define C_000070_MC_IND_WR_EN 0xFF7FFFFF 174*4882a593Smuzhiyun #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24) 175*4882a593Smuzhiyun #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1) 176*4882a593Smuzhiyun #define C_000070_MC_IND_RD_INV 0xFEFFFFFF 177*4882a593Smuzhiyun #define R_000074_MC_IND_DATA 0x000074 178*4882a593Smuzhiyun #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0) 179*4882a593Smuzhiyun #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF) 180*4882a593Smuzhiyun #define C_000074_MC_IND_DATA 0x00000000 181*4882a593Smuzhiyun #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 182*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 183*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 184*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE 185*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 186*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 187*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD 188*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_VAP(x) (((x) & 0x1) << 2) 189*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_VAP(x) (((x) >> 2) & 0x1) 190*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_VAP 0xFFFFFFFB 191*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 192*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 193*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_RE 0xFFFFFFF7 194*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 195*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) 196*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF 197*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5) 198*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1) 199*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF 200*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6) 201*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1) 202*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF 203*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7) 204*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1) 205*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F 206*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8) 207*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1) 208*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF 209*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9) 210*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1) 211*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF 212*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10) 213*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1) 214*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF 215*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11) 216*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1) 217*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF 218*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12) 219*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1) 220*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF 221*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_GA(x) (((x) & 0x1) << 13) 222*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_GA(x) (((x) >> 13) & 0x1) 223*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_GA 0xFFFFDFFF 224*4882a593Smuzhiyun #define S_0000F0_SOFT_RESET_IDCT(x) (((x) & 0x1) << 14) 225*4882a593Smuzhiyun #define G_0000F0_SOFT_RESET_IDCT(x) (((x) >> 14) & 0x1) 226*4882a593Smuzhiyun #define C_0000F0_SOFT_RESET_IDCT 0xFFFFBFFF 227*4882a593Smuzhiyun #define R_000134_HDP_FB_LOCATION 0x000134 228*4882a593Smuzhiyun #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0) 229*4882a593Smuzhiyun #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF) 230*4882a593Smuzhiyun #define C_000134_HDP_FB_START 0xFFFF0000 231*4882a593Smuzhiyun #define R_0007C0_CP_STAT 0x0007C0 232*4882a593Smuzhiyun #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 233*4882a593Smuzhiyun #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 234*4882a593Smuzhiyun #define C_0007C0_MRU_BUSY 0xFFFFFFFE 235*4882a593Smuzhiyun #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 236*4882a593Smuzhiyun #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 237*4882a593Smuzhiyun #define C_0007C0_MWU_BUSY 0xFFFFFFFD 238*4882a593Smuzhiyun #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 239*4882a593Smuzhiyun #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 240*4882a593Smuzhiyun #define C_0007C0_RSIU_BUSY 0xFFFFFFFB 241*4882a593Smuzhiyun #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 242*4882a593Smuzhiyun #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 243*4882a593Smuzhiyun #define C_0007C0_RCIU_BUSY 0xFFFFFFF7 244*4882a593Smuzhiyun #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 245*4882a593Smuzhiyun #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) 246*4882a593Smuzhiyun #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF 247*4882a593Smuzhiyun #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10) 248*4882a593Smuzhiyun #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1) 249*4882a593Smuzhiyun #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF 250*4882a593Smuzhiyun #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11) 251*4882a593Smuzhiyun #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1) 252*4882a593Smuzhiyun #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF 253*4882a593Smuzhiyun #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12) 254*4882a593Smuzhiyun #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1) 255*4882a593Smuzhiyun #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF 256*4882a593Smuzhiyun #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13) 257*4882a593Smuzhiyun #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1) 258*4882a593Smuzhiyun #define C_0007C0_CSI_BUSY 0xFFFFDFFF 259*4882a593Smuzhiyun #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14) 260*4882a593Smuzhiyun #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1) 261*4882a593Smuzhiyun #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF 262*4882a593Smuzhiyun #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15) 263*4882a593Smuzhiyun #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1) 264*4882a593Smuzhiyun #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF 265*4882a593Smuzhiyun #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28) 266*4882a593Smuzhiyun #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1) 267*4882a593Smuzhiyun #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF 268*4882a593Smuzhiyun #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29) 269*4882a593Smuzhiyun #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1) 270*4882a593Smuzhiyun #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF 271*4882a593Smuzhiyun #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30) 272*4882a593Smuzhiyun #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1) 273*4882a593Smuzhiyun #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF 274*4882a593Smuzhiyun #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31) 275*4882a593Smuzhiyun #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1) 276*4882a593Smuzhiyun #define C_0007C0_CP_BUSY 0x7FFFFFFF 277*4882a593Smuzhiyun #define R_000E40_RBBM_STATUS 0x000E40 278*4882a593Smuzhiyun #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0) 279*4882a593Smuzhiyun #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F) 280*4882a593Smuzhiyun #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80 281*4882a593Smuzhiyun #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8) 282*4882a593Smuzhiyun #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1) 283*4882a593Smuzhiyun #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF 284*4882a593Smuzhiyun #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9) 285*4882a593Smuzhiyun #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1) 286*4882a593Smuzhiyun #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF 287*4882a593Smuzhiyun #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10) 288*4882a593Smuzhiyun #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1) 289*4882a593Smuzhiyun #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF 290*4882a593Smuzhiyun #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11) 291*4882a593Smuzhiyun #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1) 292*4882a593Smuzhiyun #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF 293*4882a593Smuzhiyun #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12) 294*4882a593Smuzhiyun #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1) 295*4882a593Smuzhiyun #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF 296*4882a593Smuzhiyun #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13) 297*4882a593Smuzhiyun #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1) 298*4882a593Smuzhiyun #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF 299*4882a593Smuzhiyun #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14) 300*4882a593Smuzhiyun #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1) 301*4882a593Smuzhiyun #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF 302*4882a593Smuzhiyun #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15) 303*4882a593Smuzhiyun #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1) 304*4882a593Smuzhiyun #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF 305*4882a593Smuzhiyun #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16) 306*4882a593Smuzhiyun #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1) 307*4882a593Smuzhiyun #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF 308*4882a593Smuzhiyun #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17) 309*4882a593Smuzhiyun #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1) 310*4882a593Smuzhiyun #define C_000E40_E2_BUSY 0xFFFDFFFF 311*4882a593Smuzhiyun #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18) 312*4882a593Smuzhiyun #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1) 313*4882a593Smuzhiyun #define C_000E40_RB2D_BUSY 0xFFFBFFFF 314*4882a593Smuzhiyun #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19) 315*4882a593Smuzhiyun #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1) 316*4882a593Smuzhiyun #define C_000E40_RB3D_BUSY 0xFFF7FFFF 317*4882a593Smuzhiyun #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20) 318*4882a593Smuzhiyun #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1) 319*4882a593Smuzhiyun #define C_000E40_VAP_BUSY 0xFFEFFFFF 320*4882a593Smuzhiyun #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21) 321*4882a593Smuzhiyun #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1) 322*4882a593Smuzhiyun #define C_000E40_RE_BUSY 0xFFDFFFFF 323*4882a593Smuzhiyun #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22) 324*4882a593Smuzhiyun #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1) 325*4882a593Smuzhiyun #define C_000E40_TAM_BUSY 0xFFBFFFFF 326*4882a593Smuzhiyun #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23) 327*4882a593Smuzhiyun #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1) 328*4882a593Smuzhiyun #define C_000E40_TDM_BUSY 0xFF7FFFFF 329*4882a593Smuzhiyun #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24) 330*4882a593Smuzhiyun #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1) 331*4882a593Smuzhiyun #define C_000E40_PB_BUSY 0xFEFFFFFF 332*4882a593Smuzhiyun #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25) 333*4882a593Smuzhiyun #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1) 334*4882a593Smuzhiyun #define C_000E40_TIM_BUSY 0xFDFFFFFF 335*4882a593Smuzhiyun #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26) 336*4882a593Smuzhiyun #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1) 337*4882a593Smuzhiyun #define C_000E40_GA_BUSY 0xFBFFFFFF 338*4882a593Smuzhiyun #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27) 339*4882a593Smuzhiyun #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1) 340*4882a593Smuzhiyun #define C_000E40_CBA2D_BUSY 0xF7FFFFFF 341*4882a593Smuzhiyun #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31) 342*4882a593Smuzhiyun #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1) 343*4882a593Smuzhiyun #define C_000E40_GUI_ACTIVE 0x7FFFFFFF 344*4882a593Smuzhiyun #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4 345*4882a593Smuzhiyun #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 346*4882a593Smuzhiyun #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 347*4882a593Smuzhiyun #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000 348*4882a593Smuzhiyun #define R_006534_D1MODE_VBLANK_STATUS 0x006534 349*4882a593Smuzhiyun #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 350*4882a593Smuzhiyun #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 351*4882a593Smuzhiyun #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE 352*4882a593Smuzhiyun #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 353*4882a593Smuzhiyun #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 354*4882a593Smuzhiyun #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF 355*4882a593Smuzhiyun #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 356*4882a593Smuzhiyun #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 357*4882a593Smuzhiyun #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF 358*4882a593Smuzhiyun #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 359*4882a593Smuzhiyun #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 360*4882a593Smuzhiyun #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF 361*4882a593Smuzhiyun #define R_006540_DxMODE_INT_MASK 0x006540 362*4882a593Smuzhiyun #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0) 363*4882a593Smuzhiyun #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1) 364*4882a593Smuzhiyun #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE 365*4882a593Smuzhiyun #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4) 366*4882a593Smuzhiyun #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1) 367*4882a593Smuzhiyun #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF 368*4882a593Smuzhiyun #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8) 369*4882a593Smuzhiyun #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1) 370*4882a593Smuzhiyun #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF 371*4882a593Smuzhiyun #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12) 372*4882a593Smuzhiyun #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1) 373*4882a593Smuzhiyun #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF 374*4882a593Smuzhiyun #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30) 375*4882a593Smuzhiyun #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1) 376*4882a593Smuzhiyun #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF 377*4882a593Smuzhiyun #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31) 378*4882a593Smuzhiyun #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1) 379*4882a593Smuzhiyun #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF 380*4882a593Smuzhiyun #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4 381*4882a593Smuzhiyun #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0) 382*4882a593Smuzhiyun #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF) 383*4882a593Smuzhiyun #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000 384*4882a593Smuzhiyun #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34 385*4882a593Smuzhiyun #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0) 386*4882a593Smuzhiyun #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1) 387*4882a593Smuzhiyun #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE 388*4882a593Smuzhiyun #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4) 389*4882a593Smuzhiyun #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1) 390*4882a593Smuzhiyun #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF 391*4882a593Smuzhiyun #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12) 392*4882a593Smuzhiyun #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1) 393*4882a593Smuzhiyun #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF 394*4882a593Smuzhiyun #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16) 395*4882a593Smuzhiyun #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1) 396*4882a593Smuzhiyun #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF 397*4882a593Smuzhiyun #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC 398*4882a593Smuzhiyun #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4) 399*4882a593Smuzhiyun #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1) 400*4882a593Smuzhiyun #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF 401*4882a593Smuzhiyun #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5) 402*4882a593Smuzhiyun #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1) 403*4882a593Smuzhiyun #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF 404*4882a593Smuzhiyun #define S_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 16) 405*4882a593Smuzhiyun #define G_007EDC_DACA_AUTODETECT_INTERRUPT(x) (((x) >> 16) & 0x1) 406*4882a593Smuzhiyun #define C_007EDC_DACA_AUTODETECT_INTERRUPT 0xFFFEFFFF 407*4882a593Smuzhiyun #define S_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) & 0x1) << 17) 408*4882a593Smuzhiyun #define G_007EDC_DACB_AUTODETECT_INTERRUPT(x) (((x) >> 17) & 0x1) 409*4882a593Smuzhiyun #define C_007EDC_DACB_AUTODETECT_INTERRUPT 0xFFFDFFFF 410*4882a593Smuzhiyun #define S_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) & 0x1) << 18) 411*4882a593Smuzhiyun #define G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(x) (((x) >> 18) & 0x1) 412*4882a593Smuzhiyun #define C_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT 0xFFFBFFFF 413*4882a593Smuzhiyun #define S_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) & 0x1) << 19) 414*4882a593Smuzhiyun #define G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(x) (((x) >> 19) & 0x1) 415*4882a593Smuzhiyun #define C_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT 0xFFF7FFFF 416*4882a593Smuzhiyun #define R_007828_DACA_AUTODETECT_CONTROL 0x007828 417*4882a593Smuzhiyun #define S_007828_DACA_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 418*4882a593Smuzhiyun #define G_007828_DACA_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 419*4882a593Smuzhiyun #define C_007828_DACA_AUTODETECT_MODE 0xFFFFFFFC 420*4882a593Smuzhiyun #define S_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 421*4882a593Smuzhiyun #define G_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 422*4882a593Smuzhiyun #define C_007828_DACA_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 423*4882a593Smuzhiyun #define S_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 424*4882a593Smuzhiyun #define G_007828_DACA_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 425*4882a593Smuzhiyun #define C_007828_DACA_AUTODETECT_CHECK_MASK 0xFFFCFFFF 426*4882a593Smuzhiyun #define R_007838_DACA_AUTODETECT_INT_CONTROL 0x007838 427*4882a593Smuzhiyun #define S_007838_DACA_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 428*4882a593Smuzhiyun #define C_007838_DACA_DACA_AUTODETECT_ACK 0xFFFFFFFE 429*4882a593Smuzhiyun #define S_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 430*4882a593Smuzhiyun #define G_007838_DACA_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 431*4882a593Smuzhiyun #define C_007838_DACA_AUTODETECT_INT_ENABLE 0xFFFCFFFF 432*4882a593Smuzhiyun #define R_007A28_DACB_AUTODETECT_CONTROL 0x007A28 433*4882a593Smuzhiyun #define S_007A28_DACB_AUTODETECT_MODE(x) (((x) & 0x3) << 0) 434*4882a593Smuzhiyun #define G_007A28_DACB_AUTODETECT_MODE(x) (((x) >> 0) & 0x3) 435*4882a593Smuzhiyun #define C_007A28_DACB_AUTODETECT_MODE 0xFFFFFFFC 436*4882a593Smuzhiyun #define S_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) & 0xff) << 8) 437*4882a593Smuzhiyun #define G_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER(x) (((x) >> 8) & 0xff) 438*4882a593Smuzhiyun #define C_007A28_DACB_AUTODETECT_FRAME_TIME_COUNTER 0xFFFF00FF 439*4882a593Smuzhiyun #define S_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) & 0x3) << 16) 440*4882a593Smuzhiyun #define G_007A28_DACB_AUTODETECT_CHECK_MASK(x) (((x) >> 16) & 0x3) 441*4882a593Smuzhiyun #define C_007A28_DACB_AUTODETECT_CHECK_MASK 0xFFFCFFFF 442*4882a593Smuzhiyun #define R_007A38_DACB_AUTODETECT_INT_CONTROL 0x007A38 443*4882a593Smuzhiyun #define S_007A38_DACB_AUTODETECT_ACK(x) (((x) & 0x1) << 0) 444*4882a593Smuzhiyun #define C_007A38_DACB_DACA_AUTODETECT_ACK 0xFFFFFFFE 445*4882a593Smuzhiyun #define S_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) & 0x1) << 16) 446*4882a593Smuzhiyun #define G_007A38_DACB_AUTODETECT_INT_ENABLE(x) (((x) >> 16) & 0x1) 447*4882a593Smuzhiyun #define C_007A38_DACB_AUTODETECT_INT_ENABLE 0xFFFCFFFF 448*4882a593Smuzhiyun #define R_007D00_DC_HOT_PLUG_DETECT1_CONTROL 0x007D00 449*4882a593Smuzhiyun #define S_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) & 0x1) << 0) 450*4882a593Smuzhiyun #define G_007D00_DC_HOT_PLUG_DETECT1_EN(x) (((x) >> 0) & 0x1) 451*4882a593Smuzhiyun #define C_007D00_DC_HOT_PLUG_DETECT1_EN 0xFFFFFFFE 452*4882a593Smuzhiyun #define R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0x007D04 453*4882a593Smuzhiyun #define S_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) & 0x1) << 0) 454*4882a593Smuzhiyun #define G_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS(x) (((x) >> 0) & 0x1) 455*4882a593Smuzhiyun #define C_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS 0xFFFFFFFE 456*4882a593Smuzhiyun #define S_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) & 0x1) << 1) 457*4882a593Smuzhiyun #define G_007D04_DC_HOT_PLUG_DETECT1_SENSE(x) (((x) >> 1) & 0x1) 458*4882a593Smuzhiyun #define C_007D04_DC_HOT_PLUG_DETECT1_SENSE 0xFFFFFFFD 459*4882a593Smuzhiyun #define R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL 0x007D08 460*4882a593Smuzhiyun #define S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(x) (((x) & 0x1) << 0) 461*4882a593Smuzhiyun #define C_007D08_DC_HOT_PLUG_DETECT1_INT_ACK 0xFFFFFFFE 462*4882a593Smuzhiyun #define S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) & 0x1) << 8) 463*4882a593Smuzhiyun #define G_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(x) (((x) >> 8) & 0x1) 464*4882a593Smuzhiyun #define C_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY 0xFFFFFEFF 465*4882a593Smuzhiyun #define S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) & 0x1) << 16) 466*4882a593Smuzhiyun #define G_007D08_DC_HOT_PLUG_DETECT1_INT_EN(x) (((x) >> 16) & 0x1) 467*4882a593Smuzhiyun #define C_007D08_DC_HOT_PLUG_DETECT1_INT_EN 0xFFFEFFFF 468*4882a593Smuzhiyun #define R_007D10_DC_HOT_PLUG_DETECT2_CONTROL 0x007D10 469*4882a593Smuzhiyun #define S_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) & 0x1) << 0) 470*4882a593Smuzhiyun #define G_007D10_DC_HOT_PLUG_DETECT2_EN(x) (((x) >> 0) & 0x1) 471*4882a593Smuzhiyun #define C_007D10_DC_HOT_PLUG_DETECT2_EN 0xFFFFFFFE 472*4882a593Smuzhiyun #define R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0x007D14 473*4882a593Smuzhiyun #define S_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) & 0x1) << 0) 474*4882a593Smuzhiyun #define G_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS(x) (((x) >> 0) & 0x1) 475*4882a593Smuzhiyun #define C_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS 0xFFFFFFFE 476*4882a593Smuzhiyun #define S_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) & 0x1) << 1) 477*4882a593Smuzhiyun #define G_007D14_DC_HOT_PLUG_DETECT2_SENSE(x) (((x) >> 1) & 0x1) 478*4882a593Smuzhiyun #define C_007D14_DC_HOT_PLUG_DETECT2_SENSE 0xFFFFFFFD 479*4882a593Smuzhiyun #define R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL 0x007D18 480*4882a593Smuzhiyun #define S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(x) (((x) & 0x1) << 0) 481*4882a593Smuzhiyun #define C_007D18_DC_HOT_PLUG_DETECT2_INT_ACK 0xFFFFFFFE 482*4882a593Smuzhiyun #define S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) & 0x1) << 8) 483*4882a593Smuzhiyun #define G_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(x) (((x) >> 8) & 0x1) 484*4882a593Smuzhiyun #define C_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY 0xFFFFFEFF 485*4882a593Smuzhiyun #define S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) & 0x1) << 16) 486*4882a593Smuzhiyun #define G_007D18_DC_HOT_PLUG_DETECT2_INT_EN(x) (((x) >> 16) & 0x1) 487*4882a593Smuzhiyun #define C_007D18_DC_HOT_PLUG_DETECT2_INT_EN 0xFFFEFFFF 488*4882a593Smuzhiyun #define R_007404_HDMI0_STATUS 0x007404 489*4882a593Smuzhiyun #define S_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) & 0x1) << 28) 490*4882a593Smuzhiyun #define G_007404_HDMI0_AZ_FORMAT_WTRIG(x) (((x) >> 28) & 0x1) 491*4882a593Smuzhiyun #define C_007404_HDMI0_AZ_FORMAT_WTRIG 0xEFFFFFFF 492*4882a593Smuzhiyun #define S_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) & 0x1) << 29) 493*4882a593Smuzhiyun #define G_007404_HDMI0_AZ_FORMAT_WTRIG_INT(x) (((x) >> 29) & 0x1) 494*4882a593Smuzhiyun #define C_007404_HDMI0_AZ_FORMAT_WTRIG_INT 0xDFFFFFFF 495*4882a593Smuzhiyun #define R_007408_HDMI0_AUDIO_PACKET_CONTROL 0x007408 496*4882a593Smuzhiyun #define S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) & 0x1) << 28) 497*4882a593Smuzhiyun #define G_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(x) (((x) >> 28) & 0x1) 498*4882a593Smuzhiyun #define C_007408_HDMI0_AZ_FORMAT_WTRIG_MASK 0xEFFFFFFF 499*4882a593Smuzhiyun #define S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) & 0x1) << 29) 500*4882a593Smuzhiyun #define G_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(x) (((x) >> 29) & 0x1) 501*4882a593Smuzhiyun #define C_007408_HDMI0_AZ_FORMAT_WTRIG_ACK 0xDFFFFFFF 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /* MC registers */ 504*4882a593Smuzhiyun #define R_000000_MC_STATUS 0x000000 505*4882a593Smuzhiyun #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0) 506*4882a593Smuzhiyun #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1) 507*4882a593Smuzhiyun #define C_000000_MC_IDLE 0xFFFFFFFE 508*4882a593Smuzhiyun #define R_000004_MC_FB_LOCATION 0x000004 509*4882a593Smuzhiyun #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0) 510*4882a593Smuzhiyun #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF) 511*4882a593Smuzhiyun #define C_000004_MC_FB_START 0xFFFF0000 512*4882a593Smuzhiyun #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16) 513*4882a593Smuzhiyun #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF) 514*4882a593Smuzhiyun #define C_000004_MC_FB_TOP 0x0000FFFF 515*4882a593Smuzhiyun #define R_000005_MC_AGP_LOCATION 0x000005 516*4882a593Smuzhiyun #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0) 517*4882a593Smuzhiyun #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF) 518*4882a593Smuzhiyun #define C_000005_MC_AGP_START 0xFFFF0000 519*4882a593Smuzhiyun #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16) 520*4882a593Smuzhiyun #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF) 521*4882a593Smuzhiyun #define C_000005_MC_AGP_TOP 0x0000FFFF 522*4882a593Smuzhiyun #define R_000006_AGP_BASE 0x000006 523*4882a593Smuzhiyun #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0) 524*4882a593Smuzhiyun #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF) 525*4882a593Smuzhiyun #define C_000006_AGP_BASE_ADDR 0x00000000 526*4882a593Smuzhiyun #define R_000007_AGP_BASE_2 0x000007 527*4882a593Smuzhiyun #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0) 528*4882a593Smuzhiyun #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF) 529*4882a593Smuzhiyun #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0 530*4882a593Smuzhiyun #define R_000009_MC_CNTL1 0x000009 531*4882a593Smuzhiyun #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26) 532*4882a593Smuzhiyun #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1) 533*4882a593Smuzhiyun #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF 534*4882a593Smuzhiyun /* FIXME don't know the various field size need feedback from AMD */ 535*4882a593Smuzhiyun #define R_000100_MC_PT0_CNTL 0x000100 536*4882a593Smuzhiyun #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0) 537*4882a593Smuzhiyun #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1) 538*4882a593Smuzhiyun #define C_000100_ENABLE_PT 0xFFFFFFFE 539*4882a593Smuzhiyun #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15) 540*4882a593Smuzhiyun #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7) 541*4882a593Smuzhiyun #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF 542*4882a593Smuzhiyun #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21) 543*4882a593Smuzhiyun #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7) 544*4882a593Smuzhiyun #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF 545*4882a593Smuzhiyun #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28) 546*4882a593Smuzhiyun #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1) 547*4882a593Smuzhiyun #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF 548*4882a593Smuzhiyun #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29) 549*4882a593Smuzhiyun #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1) 550*4882a593Smuzhiyun #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF 551*4882a593Smuzhiyun #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102 552*4882a593Smuzhiyun #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0) 553*4882a593Smuzhiyun #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1) 554*4882a593Smuzhiyun #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE 555*4882a593Smuzhiyun #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1) 556*4882a593Smuzhiyun #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3) 557*4882a593Smuzhiyun #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9 558*4882a593Smuzhiyun #define V_000102_PAGE_TABLE_FLAT 0 559*4882a593Smuzhiyun /* R600 documentation suggest that this should be a number of pages */ 560*4882a593Smuzhiyun #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112 561*4882a593Smuzhiyun #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114 562*4882a593Smuzhiyun #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C 563*4882a593Smuzhiyun #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C 564*4882a593Smuzhiyun #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C 565*4882a593Smuzhiyun #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C 566*4882a593Smuzhiyun #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C 567*4882a593Smuzhiyun #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0) 568*4882a593Smuzhiyun #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1) 569*4882a593Smuzhiyun #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE 570*4882a593Smuzhiyun #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1) 571*4882a593Smuzhiyun #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1) 572*4882a593Smuzhiyun #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD 573*4882a593Smuzhiyun #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8) 574*4882a593Smuzhiyun #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3) 575*4882a593Smuzhiyun #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF 576*4882a593Smuzhiyun #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0 577*4882a593Smuzhiyun #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1 578*4882a593Smuzhiyun #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2 579*4882a593Smuzhiyun #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3 580*4882a593Smuzhiyun #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10) 581*4882a593Smuzhiyun #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1) 582*4882a593Smuzhiyun #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF 583*4882a593Smuzhiyun #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0 584*4882a593Smuzhiyun #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1 585*4882a593Smuzhiyun #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11) 586*4882a593Smuzhiyun #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7) 587*4882a593Smuzhiyun #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF 588*4882a593Smuzhiyun #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14) 589*4882a593Smuzhiyun #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1) 590*4882a593Smuzhiyun #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF 591*4882a593Smuzhiyun #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15) 592*4882a593Smuzhiyun #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7) 593*4882a593Smuzhiyun #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF 594*4882a593Smuzhiyun #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20) 595*4882a593Smuzhiyun #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1) 596*4882a593Smuzhiyun #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun #define R_006548_D1MODE_PRIORITY_A_CNT 0x006548 599*4882a593Smuzhiyun #define S_006548_D1MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 600*4882a593Smuzhiyun #define G_006548_D1MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 601*4882a593Smuzhiyun #define C_006548_D1MODE_PRIORITY_MARK_A 0xFFFF8000 602*4882a593Smuzhiyun #define S_006548_D1MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 603*4882a593Smuzhiyun #define G_006548_D1MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 604*4882a593Smuzhiyun #define C_006548_D1MODE_PRIORITY_A_OFF 0xFFFEFFFF 605*4882a593Smuzhiyun #define S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 606*4882a593Smuzhiyun #define G_006548_D1MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 607*4882a593Smuzhiyun #define C_006548_D1MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 608*4882a593Smuzhiyun #define S_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 609*4882a593Smuzhiyun #define G_006548_D1MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 610*4882a593Smuzhiyun #define C_006548_D1MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 611*4882a593Smuzhiyun #define R_00654C_D1MODE_PRIORITY_B_CNT 0x00654C 612*4882a593Smuzhiyun #define S_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 613*4882a593Smuzhiyun #define G_00654C_D1MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 614*4882a593Smuzhiyun #define C_00654C_D1MODE_PRIORITY_MARK_B 0xFFFF8000 615*4882a593Smuzhiyun #define S_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 616*4882a593Smuzhiyun #define G_00654C_D1MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 617*4882a593Smuzhiyun #define C_00654C_D1MODE_PRIORITY_B_OFF 0xFFFEFFFF 618*4882a593Smuzhiyun #define S_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 619*4882a593Smuzhiyun #define G_00654C_D1MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 620*4882a593Smuzhiyun #define C_00654C_D1MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 621*4882a593Smuzhiyun #define S_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 622*4882a593Smuzhiyun #define G_00654C_D1MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 623*4882a593Smuzhiyun #define C_00654C_D1MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 624*4882a593Smuzhiyun #define R_006D48_D2MODE_PRIORITY_A_CNT 0x006D48 625*4882a593Smuzhiyun #define S_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) & 0x7FFF) << 0) 626*4882a593Smuzhiyun #define G_006D48_D2MODE_PRIORITY_MARK_A(x) (((x) >> 0) & 0x7FFF) 627*4882a593Smuzhiyun #define C_006D48_D2MODE_PRIORITY_MARK_A 0xFFFF8000 628*4882a593Smuzhiyun #define S_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) & 0x1) << 16) 629*4882a593Smuzhiyun #define G_006D48_D2MODE_PRIORITY_A_OFF(x) (((x) >> 16) & 0x1) 630*4882a593Smuzhiyun #define C_006D48_D2MODE_PRIORITY_A_OFF 0xFFFEFFFF 631*4882a593Smuzhiyun #define S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) & 0x1) << 20) 632*4882a593Smuzhiyun #define G_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(x) (((x) >> 20) & 0x1) 633*4882a593Smuzhiyun #define C_006D48_D2MODE_PRIORITY_A_ALWAYS_ON 0xFFEFFFFF 634*4882a593Smuzhiyun #define S_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) & 0x1) << 24) 635*4882a593Smuzhiyun #define G_006D48_D2MODE_PRIORITY_A_FORCE_MASK(x) (((x) >> 24) & 0x1) 636*4882a593Smuzhiyun #define C_006D48_D2MODE_PRIORITY_A_FORCE_MASK 0xFEFFFFFF 637*4882a593Smuzhiyun #define R_006D4C_D2MODE_PRIORITY_B_CNT 0x006D4C 638*4882a593Smuzhiyun #define S_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) & 0x7FFF) << 0) 639*4882a593Smuzhiyun #define G_006D4C_D2MODE_PRIORITY_MARK_B(x) (((x) >> 0) & 0x7FFF) 640*4882a593Smuzhiyun #define C_006D4C_D2MODE_PRIORITY_MARK_B 0xFFFF8000 641*4882a593Smuzhiyun #define S_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) & 0x1) << 16) 642*4882a593Smuzhiyun #define G_006D4C_D2MODE_PRIORITY_B_OFF(x) (((x) >> 16) & 0x1) 643*4882a593Smuzhiyun #define C_006D4C_D2MODE_PRIORITY_B_OFF 0xFFFEFFFF 644*4882a593Smuzhiyun #define S_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) & 0x1) << 20) 645*4882a593Smuzhiyun #define G_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON(x) (((x) >> 20) & 0x1) 646*4882a593Smuzhiyun #define C_006D4C_D2MODE_PRIORITY_B_ALWAYS_ON 0xFFEFFFFF 647*4882a593Smuzhiyun #define S_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) & 0x1) << 24) 648*4882a593Smuzhiyun #define G_006D4C_D2MODE_PRIORITY_B_FORCE_MASK(x) (((x) >> 24) & 0x1) 649*4882a593Smuzhiyun #define C_006D4C_D2MODE_PRIORITY_B_FORCE_MASK 0xFEFFFFFF 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun /* PLL regs */ 652*4882a593Smuzhiyun #define GENERAL_PWRMGT 0x8 653*4882a593Smuzhiyun #define GLOBAL_PWRMGT_EN (1 << 0) 654*4882a593Smuzhiyun #define MOBILE_SU (1 << 2) 655*4882a593Smuzhiyun #define DYN_PWRMGT_SCLK_LENGTH 0xc 656*4882a593Smuzhiyun #define NORMAL_POWER_SCLK_HILEN(x) ((x) << 0) 657*4882a593Smuzhiyun #define NORMAL_POWER_SCLK_LOLEN(x) ((x) << 4) 658*4882a593Smuzhiyun #define REDUCED_POWER_SCLK_HILEN(x) ((x) << 8) 659*4882a593Smuzhiyun #define REDUCED_POWER_SCLK_LOLEN(x) ((x) << 12) 660*4882a593Smuzhiyun #define POWER_D1_SCLK_HILEN(x) ((x) << 16) 661*4882a593Smuzhiyun #define POWER_D1_SCLK_LOLEN(x) ((x) << 20) 662*4882a593Smuzhiyun #define STATIC_SCREEN_HILEN(x) ((x) << 24) 663*4882a593Smuzhiyun #define STATIC_SCREEN_LOLEN(x) ((x) << 28) 664*4882a593Smuzhiyun #define DYN_SCLK_VOL_CNTL 0xe 665*4882a593Smuzhiyun #define IO_CG_VOLTAGE_DROP (1 << 0) 666*4882a593Smuzhiyun #define VOLTAGE_DROP_SYNC (1 << 2) 667*4882a593Smuzhiyun #define VOLTAGE_DELAY_SEL(x) ((x) << 3) 668*4882a593Smuzhiyun #define HDP_DYN_CNTL 0x10 669*4882a593Smuzhiyun #define HDP_FORCEON (1 << 0) 670*4882a593Smuzhiyun #define MC_HOST_DYN_CNTL 0x1e 671*4882a593Smuzhiyun #define MC_HOST_FORCEON (1 << 0) 672*4882a593Smuzhiyun #define DYN_BACKBIAS_CNTL 0x29 673*4882a593Smuzhiyun #define IO_CG_BACKBIAS_EN (1 << 0) 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun /* mmreg */ 676*4882a593Smuzhiyun #define DOUT_POWER_MANAGEMENT_CNTL 0x7ee0 677*4882a593Smuzhiyun #define PWRDN_WAIT_BUSY_OFF (1 << 0) 678*4882a593Smuzhiyun #define PWRDN_WAIT_PWRSEQ_OFF (1 << 4) 679*4882a593Smuzhiyun #define PWRDN_WAIT_PPLL_OFF (1 << 8) 680*4882a593Smuzhiyun #define PWRUP_WAIT_PPLL_ON (1 << 12) 681*4882a593Smuzhiyun #define PWRUP_WAIT_MEM_INIT_DONE (1 << 16) 682*4882a593Smuzhiyun #define PM_ASSERT_RESET (1 << 20) 683*4882a593Smuzhiyun #define PM_PWRDN_PPLL (1 << 24) 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun #endif 686