1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __RTCODEC5631_H__ 3*4882a593Smuzhiyun #define __RTCODEC5631_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define RT5631_RESET 0x00 7*4882a593Smuzhiyun #define RT5631_SPK_OUT_VOL 0x02 8*4882a593Smuzhiyun #define RT5631_HP_OUT_VOL 0x04 9*4882a593Smuzhiyun #define RT5631_MONO_AXO_1_2_VOL 0x06 10*4882a593Smuzhiyun #define RT5631_AUX_IN_VOL 0x0A 11*4882a593Smuzhiyun #define RT5631_STEREO_DAC_VOL_1 0x0C 12*4882a593Smuzhiyun #define RT5631_MIC_CTRL_1 0x0E 13*4882a593Smuzhiyun #define RT5631_STEREO_DAC_VOL_2 0x10 14*4882a593Smuzhiyun #define RT5631_ADC_CTRL_1 0x12 15*4882a593Smuzhiyun #define RT5631_ADC_REC_MIXER 0x14 16*4882a593Smuzhiyun #define RT5631_ADC_CTRL_2 0x16 17*4882a593Smuzhiyun #define RT5631_VDAC_DIG_VOL 0x18 18*4882a593Smuzhiyun #define RT5631_OUTMIXER_L_CTRL 0x1A 19*4882a593Smuzhiyun #define RT5631_OUTMIXER_R_CTRL 0x1C 20*4882a593Smuzhiyun #define RT5631_AXO1MIXER_CTRL 0x1E 21*4882a593Smuzhiyun #define RT5631_AXO2MIXER_CTRL 0x20 22*4882a593Smuzhiyun #define RT5631_MIC_CTRL_2 0x22 23*4882a593Smuzhiyun #define RT5631_DIG_MIC_CTRL 0x24 24*4882a593Smuzhiyun #define RT5631_MONO_INPUT_VOL 0x26 25*4882a593Smuzhiyun #define RT5631_SPK_MIXER_CTRL 0x28 26*4882a593Smuzhiyun #define RT5631_SPK_MONO_OUT_CTRL 0x2A 27*4882a593Smuzhiyun #define RT5631_SPK_MONO_HP_OUT_CTRL 0x2C 28*4882a593Smuzhiyun #define RT5631_SDP_CTRL 0x34 29*4882a593Smuzhiyun #define RT5631_MONO_SDP_CTRL 0x36 30*4882a593Smuzhiyun #define RT5631_STEREO_AD_DA_CLK_CTRL 0x38 31*4882a593Smuzhiyun #define RT5631_PWR_MANAG_ADD1 0x3A 32*4882a593Smuzhiyun #define RT5631_PWR_MANAG_ADD2 0x3B 33*4882a593Smuzhiyun #define RT5631_PWR_MANAG_ADD3 0x3C 34*4882a593Smuzhiyun #define RT5631_PWR_MANAG_ADD4 0x3E 35*4882a593Smuzhiyun #define RT5631_GEN_PUR_CTRL_REG 0x40 36*4882a593Smuzhiyun #define RT5631_GLOBAL_CLK_CTRL 0x42 37*4882a593Smuzhiyun #define RT5631_PLL_CTRL 0x44 38*4882a593Smuzhiyun #define RT5631_INT_ST_IRQ_CTRL_1 0x48 39*4882a593Smuzhiyun #define RT5631_INT_ST_IRQ_CTRL_2 0x4A 40*4882a593Smuzhiyun #define RT5631_GPIO_CTRL 0x4C 41*4882a593Smuzhiyun #define RT5631_MISC_CTRL 0x52 42*4882a593Smuzhiyun #define RT5631_DEPOP_FUN_CTRL_1 0x54 43*4882a593Smuzhiyun #define RT5631_DEPOP_FUN_CTRL_2 0x56 44*4882a593Smuzhiyun #define RT5631_JACK_DET_CTRL 0x5A 45*4882a593Smuzhiyun #define RT5631_SOFT_VOL_CTRL 0x5C 46*4882a593Smuzhiyun #define RT5631_ALC_CTRL_1 0x64 47*4882a593Smuzhiyun #define RT5631_ALC_CTRL_2 0x65 48*4882a593Smuzhiyun #define RT5631_ALC_CTRL_3 0x66 49*4882a593Smuzhiyun #define RT5631_PSEUDO_SPATL_CTRL 0x68 50*4882a593Smuzhiyun #define RT5631_INDEX_ADD 0x6A 51*4882a593Smuzhiyun #define RT5631_INDEX_DATA 0x6C 52*4882a593Smuzhiyun #define RT5631_EQ_CTRL 0x6E 53*4882a593Smuzhiyun #define RT5631_VENDOR_ID 0x7A 54*4882a593Smuzhiyun #define RT5631_VENDOR_ID1 0x7C 55*4882a593Smuzhiyun #define RT5631_VENDOR_ID2 0x7E 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Index of Codec Private Register definition */ 58*4882a593Smuzhiyun #define RT5631_EQ_BW_LOP 0x00 59*4882a593Smuzhiyun #define RT5631_EQ_GAIN_LOP 0x01 60*4882a593Smuzhiyun #define RT5631_EQ_FC_BP1 0x02 61*4882a593Smuzhiyun #define RT5631_EQ_BW_BP1 0x03 62*4882a593Smuzhiyun #define RT5631_EQ_GAIN_BP1 0x04 63*4882a593Smuzhiyun #define RT5631_EQ_FC_BP2 0x05 64*4882a593Smuzhiyun #define RT5631_EQ_BW_BP2 0x06 65*4882a593Smuzhiyun #define RT5631_EQ_GAIN_BP2 0x07 66*4882a593Smuzhiyun #define RT5631_EQ_FC_BP3 0x08 67*4882a593Smuzhiyun #define RT5631_EQ_BW_BP3 0x09 68*4882a593Smuzhiyun #define RT5631_EQ_GAIN_BP3 0x0a 69*4882a593Smuzhiyun #define RT5631_EQ_BW_HIP 0x0b 70*4882a593Smuzhiyun #define RT5631_EQ_GAIN_HIP 0x0c 71*4882a593Smuzhiyun #define RT5631_EQ_HPF_A1 0x0d 72*4882a593Smuzhiyun #define RT5631_EQ_HPF_A2 0x0e 73*4882a593Smuzhiyun #define RT5631_EQ_HPF_GAIN 0x0f 74*4882a593Smuzhiyun #define RT5631_EQ_PRE_VOL_CTRL 0x11 75*4882a593Smuzhiyun #define RT5631_EQ_POST_VOL_CTRL 0x12 76*4882a593Smuzhiyun #define RT5631_TEST_MODE_CTRL 0x39 77*4882a593Smuzhiyun #define RT5631_CP_INTL_REG2 0x45 78*4882a593Smuzhiyun #define RT5631_ADDA_MIXER_INTL_REG3 0x52 79*4882a593Smuzhiyun #define RT5631_SPK_INTL_CTRL 0x56 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* global definition */ 83*4882a593Smuzhiyun #define RT5631_L_MUTE (0x1 << 15) 84*4882a593Smuzhiyun #define RT5631_L_MUTE_SHIFT 15 85*4882a593Smuzhiyun #define RT5631_L_EN (0x1 << 14) 86*4882a593Smuzhiyun #define RT5631_L_EN_SHIFT 14 87*4882a593Smuzhiyun #define RT5631_R_MUTE (0x1 << 7) 88*4882a593Smuzhiyun #define RT5631_R_MUTE_SHIFT 7 89*4882a593Smuzhiyun #define RT5631_R_EN (0x1 << 6) 90*4882a593Smuzhiyun #define RT5631_R_EN_SHIFT 6 91*4882a593Smuzhiyun #define RT5631_VOL_MASK 0x1f 92*4882a593Smuzhiyun #define RT5631_L_VOL_SHIFT 8 93*4882a593Smuzhiyun #define RT5631_R_VOL_SHIFT 0 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* Speaker Output Control(0x02) */ 96*4882a593Smuzhiyun #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14) 97*4882a593Smuzhiyun #define RT5631_SPK_L_VOL_SEL_VMID (0x0 << 14) 98*4882a593Smuzhiyun #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14) 99*4882a593Smuzhiyun #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6) 100*4882a593Smuzhiyun #define RT5631_SPK_R_VOL_SEL_VMID (0x0 << 6) 101*4882a593Smuzhiyun #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Headphone Output Control(0x04) */ 104*4882a593Smuzhiyun #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14) 105*4882a593Smuzhiyun #define RT5631_HP_L_VOL_SEL_VMID (0x0 << 14) 106*4882a593Smuzhiyun #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 14) 107*4882a593Smuzhiyun #define RT5631_HP_R_VOL_SEL_MASK (0x1 << 6) 108*4882a593Smuzhiyun #define RT5631_HP_R_VOL_SEL_VMID (0x0 << 6) 109*4882a593Smuzhiyun #define RT5631_HP_R_VOL_SEL_OUTMIX_R (0x1 << 6) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Output Control for AUXOUT/MONO(0x06) */ 112*4882a593Smuzhiyun #define RT5631_AUXOUT_1_VOL_SEL_MASK (0x1 << 14) 113*4882a593Smuzhiyun #define RT5631_AUXOUT_1_VOL_SEL_VMID (0x0 << 14) 114*4882a593Smuzhiyun #define RT5631_AUXOUT_1_VOL_SEL_OUTMIX_L (0x1 << 14) 115*4882a593Smuzhiyun #define RT5631_MUTE_MONO (0x1 << 13) 116*4882a593Smuzhiyun #define RT5631_MUTE_MONO_SHIFT 13 117*4882a593Smuzhiyun #define RT5631_AUXOUT_2_VOL_SEL_MASK (0x1 << 6) 118*4882a593Smuzhiyun #define RT5631_AUXOUT_2_VOL_SEL_VMID (0x0 << 6) 119*4882a593Smuzhiyun #define RT5631_AUXOUT_2_VOL_SEL_OUTMIX_R (0x1 << 6) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* Microphone Input Control 1(0x0E) */ 122*4882a593Smuzhiyun #define RT5631_MIC1_DIFF_INPUT_CTRL (0x1 << 15) 123*4882a593Smuzhiyun #define RT5631_MIC1_DIFF_INPUT_SHIFT 15 124*4882a593Smuzhiyun #define RT5631_MIC2_DIFF_INPUT_CTRL (0x1 << 7) 125*4882a593Smuzhiyun #define RT5631_MIC2_DIFF_INPUT_SHIFT 7 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* Stereo DAC Digital Volume2(0x10) */ 128*4882a593Smuzhiyun #define RT5631_DAC_VOL_MASK 0xff 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* ADC Recording Mixer Control(0x14) */ 131*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_L_TO_RECMIXER_L (0x1 << 15) 132*4882a593Smuzhiyun #define RT5631_M_OUTMIXL_RECMIXL_BIT 15 133*4882a593Smuzhiyun #define RT5631_M_MIC1_TO_RECMIXER_L (0x1 << 14) 134*4882a593Smuzhiyun #define RT5631_M_MIC1_RECMIXL_BIT 14 135*4882a593Smuzhiyun #define RT5631_M_AXIL_TO_RECMIXER_L (0x1 << 13) 136*4882a593Smuzhiyun #define RT5631_M_AXIL_RECMIXL_BIT 13 137*4882a593Smuzhiyun #define RT5631_M_MONO_IN_TO_RECMIXER_L (0x1 << 12) 138*4882a593Smuzhiyun #define RT5631_M_MONO_IN_RECMIXL_BIT 12 139*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_R_TO_RECMIXER_R (0x1 << 7) 140*4882a593Smuzhiyun #define RT5631_M_OUTMIXR_RECMIXR_BIT 7 141*4882a593Smuzhiyun #define RT5631_M_MIC2_TO_RECMIXER_R (0x1 << 6) 142*4882a593Smuzhiyun #define RT5631_M_MIC2_RECMIXR_BIT 6 143*4882a593Smuzhiyun #define RT5631_M_AXIR_TO_RECMIXER_R (0x1 << 5) 144*4882a593Smuzhiyun #define RT5631_M_AXIR_RECMIXR_BIT 5 145*4882a593Smuzhiyun #define RT5631_M_MONO_IN_TO_RECMIXER_R (0x1 << 4) 146*4882a593Smuzhiyun #define RT5631_M_MONO_IN_RECMIXR_BIT 4 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Left Output Mixer Control(0x1A) */ 149*4882a593Smuzhiyun #define RT5631_M_RECMIXER_L_TO_OUTMIXER_L (0x1 << 15) 150*4882a593Smuzhiyun #define RT5631_M_RECMIXL_OUTMIXL_BIT 15 151*4882a593Smuzhiyun #define RT5631_M_RECMIXER_R_TO_OUTMIXER_L (0x1 << 14) 152*4882a593Smuzhiyun #define RT5631_M_RECMIXR_OUTMIXL_BIT 14 153*4882a593Smuzhiyun #define RT5631_M_DAC_L_TO_OUTMIXER_L (0x1 << 13) 154*4882a593Smuzhiyun #define RT5631_M_DACL_OUTMIXL_BIT 13 155*4882a593Smuzhiyun #define RT5631_M_MIC1_TO_OUTMIXER_L (0x1 << 12) 156*4882a593Smuzhiyun #define RT5631_M_MIC1_OUTMIXL_BIT 12 157*4882a593Smuzhiyun #define RT5631_M_MIC2_TO_OUTMIXER_L (0x1 << 11) 158*4882a593Smuzhiyun #define RT5631_M_MIC2_OUTMIXL_BIT 11 159*4882a593Smuzhiyun #define RT5631_M_MONO_IN_P_TO_OUTMIXER_L (0x1 << 10) 160*4882a593Smuzhiyun #define RT5631_M_MONO_INP_OUTMIXL_BIT 10 161*4882a593Smuzhiyun #define RT5631_M_AXIL_TO_OUTMIXER_L (0x1 << 9) 162*4882a593Smuzhiyun #define RT5631_M_AXIL_OUTMIXL_BIT 9 163*4882a593Smuzhiyun #define RT5631_M_AXIR_TO_OUTMIXER_L (0x1 << 8) 164*4882a593Smuzhiyun #define RT5631_M_AXIR_OUTMIXL_BIT 8 165*4882a593Smuzhiyun #define RT5631_M_VDAC_TO_OUTMIXER_L (0x1 << 7) 166*4882a593Smuzhiyun #define RT5631_M_VDAC_OUTMIXL_BIT 7 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* Right Output Mixer Control(0x1C) */ 169*4882a593Smuzhiyun #define RT5631_M_RECMIXER_L_TO_OUTMIXER_R (0x1 << 15) 170*4882a593Smuzhiyun #define RT5631_M_RECMIXL_OUTMIXR_BIT 15 171*4882a593Smuzhiyun #define RT5631_M_RECMIXER_R_TO_OUTMIXER_R (0x1 << 14) 172*4882a593Smuzhiyun #define RT5631_M_RECMIXR_OUTMIXR_BIT 14 173*4882a593Smuzhiyun #define RT5631_M_DAC_R_TO_OUTMIXER_R (0x1 << 13) 174*4882a593Smuzhiyun #define RT5631_M_DACR_OUTMIXR_BIT 13 175*4882a593Smuzhiyun #define RT5631_M_MIC1_TO_OUTMIXER_R (0x1 << 12) 176*4882a593Smuzhiyun #define RT5631_M_MIC1_OUTMIXR_BIT 12 177*4882a593Smuzhiyun #define RT5631_M_MIC2_TO_OUTMIXER_R (0x1 << 11) 178*4882a593Smuzhiyun #define RT5631_M_MIC2_OUTMIXR_BIT 11 179*4882a593Smuzhiyun #define RT5631_M_MONO_IN_N_TO_OUTMIXER_R (0x1 << 10) 180*4882a593Smuzhiyun #define RT5631_M_MONO_INN_OUTMIXR_BIT 10 181*4882a593Smuzhiyun #define RT5631_M_AXIL_TO_OUTMIXER_R (0x1 << 9) 182*4882a593Smuzhiyun #define RT5631_M_AXIL_OUTMIXR_BIT 9 183*4882a593Smuzhiyun #define RT5631_M_AXIR_TO_OUTMIXER_R (0x1 << 8) 184*4882a593Smuzhiyun #define RT5631_M_AXIR_OUTMIXR_BIT 8 185*4882a593Smuzhiyun #define RT5631_M_VDAC_TO_OUTMIXER_R (0x1 << 7) 186*4882a593Smuzhiyun #define RT5631_M_VDAC_OUTMIXR_BIT 7 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* Lout Mixer Control(0x1E) */ 189*4882a593Smuzhiyun #define RT5631_M_MIC1_TO_AXO1MIXER (0x1 << 15) 190*4882a593Smuzhiyun #define RT5631_M_MIC1_AXO1MIX_BIT 15 191*4882a593Smuzhiyun #define RT5631_M_MIC2_TO_AXO1MIXER (0x1 << 11) 192*4882a593Smuzhiyun #define RT5631_M_MIC2_AXO1MIX_BIT 11 193*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_L_TO_AXO1MIXER (0x1 << 7) 194*4882a593Smuzhiyun #define RT5631_M_OUTMIXL_AXO1MIX_BIT 7 195*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_R_TO_AXO1MIXER (0x1 << 6) 196*4882a593Smuzhiyun #define RT5631_M_OUTMIXR_AXO1MIX_BIT 6 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* Rout Mixer Control(0x20) */ 199*4882a593Smuzhiyun #define RT5631_M_MIC1_TO_AXO2MIXER (0x1 << 15) 200*4882a593Smuzhiyun #define RT5631_M_MIC1_AXO2MIX_BIT 15 201*4882a593Smuzhiyun #define RT5631_M_MIC2_TO_AXO2MIXER (0x1 << 11) 202*4882a593Smuzhiyun #define RT5631_M_MIC2_AXO2MIX_BIT 11 203*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_L_TO_AXO2MIXER (0x1 << 7) 204*4882a593Smuzhiyun #define RT5631_M_OUTMIXL_AXO2MIX_BIT 7 205*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_R_TO_AXO2MIXER (0x1 << 6) 206*4882a593Smuzhiyun #define RT5631_M_OUTMIXR_AXO2MIX_BIT 6 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* Micphone Input Control 2(0x22) */ 209*4882a593Smuzhiyun #define RT5631_MIC_BIAS_90_PRECNET_AVDD 1 210*4882a593Smuzhiyun #define RT5631_MIC_BIAS_75_PRECNET_AVDD 2 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_MASK (0xf << 12) 213*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_BYPASS (0x0 << 12) 214*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_20DB (0x1 << 12) 215*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_24DB (0x2 << 12) 216*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_30DB (0x3 << 12) 217*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_35DB (0x4 << 12) 218*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_40DB (0x5 << 12) 219*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_34DB (0x6 << 12) 220*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_50DB (0x7 << 12) 221*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_CTRL_52DB (0x8 << 12) 222*4882a593Smuzhiyun #define RT5631_MIC1_BOOST_SHIFT 12 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_MASK (0xf << 8) 225*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_BYPASS (0x0 << 8) 226*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_20DB (0x1 << 8) 227*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_24DB (0x2 << 8) 228*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8) 229*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_35DB (0x4 << 8) 230*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_40DB (0x5 << 8) 231*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_34DB (0x6 << 8) 232*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_50DB (0x7 << 8) 233*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_CTRL_52DB (0x8 << 8) 234*4882a593Smuzhiyun #define RT5631_MIC2_BOOST_SHIFT 8 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define RT5631_MICBIAS1_VOLT_CTRL_MASK (0x1 << 7) 237*4882a593Smuzhiyun #define RT5631_MICBIAS1_VOLT_CTRL_90P (0x0 << 7) 238*4882a593Smuzhiyun #define RT5631_MICBIAS1_VOLT_CTRL_75P (0x1 << 7) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define RT5631_MICBIAS1_S_C_DET_MASK (0x1 << 6) 241*4882a593Smuzhiyun #define RT5631_MICBIAS1_S_C_DET_DIS (0x0 << 6) 242*4882a593Smuzhiyun #define RT5631_MICBIAS1_S_C_DET_ENA (0x1 << 6) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK (0x3 << 4) 245*4882a593Smuzhiyun #define RT5631_MICBIAS1_SHORT_CURR_DET_600UA (0x0 << 4) 246*4882a593Smuzhiyun #define RT5631_MICBIAS1_SHORT_CURR_DET_1500UA (0x1 << 4) 247*4882a593Smuzhiyun #define RT5631_MICBIAS1_SHORT_CURR_DET_2000UA (0x2 << 4) 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define RT5631_MICBIAS2_VOLT_CTRL_MASK (0x1 << 3) 250*4882a593Smuzhiyun #define RT5631_MICBIAS2_VOLT_CTRL_90P (0x0 << 3) 251*4882a593Smuzhiyun #define RT5631_MICBIAS2_VOLT_CTRL_75P (0x1 << 3) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define RT5631_MICBIAS2_S_C_DET_MASK (0x1 << 2) 254*4882a593Smuzhiyun #define RT5631_MICBIAS2_S_C_DET_DIS (0x0 << 2) 255*4882a593Smuzhiyun #define RT5631_MICBIAS2_S_C_DET_ENA (0x1 << 2) 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK (0x3) 258*4882a593Smuzhiyun #define RT5631_MICBIAS2_SHORT_CURR_DET_600UA (0x0) 259*4882a593Smuzhiyun #define RT5631_MICBIAS2_SHORT_CURR_DET_1500UA (0x1) 260*4882a593Smuzhiyun #define RT5631_MICBIAS2_SHORT_CURR_DET_2000UA (0x2) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* Digital Microphone Control(0x24) */ 264*4882a593Smuzhiyun #define RT5631_DMIC_ENA_MASK (0x1 << 15) 265*4882a593Smuzhiyun #define RT5631_DMIC_ENA_SHIFT 15 266*4882a593Smuzhiyun /* DMIC_ENA: DMIC to ADC Digital filter */ 267*4882a593Smuzhiyun #define RT5631_DMIC_ENA (0x1 << 15) 268*4882a593Smuzhiyun /* DMIC_DIS: ADC mixer to ADC Digital filter */ 269*4882a593Smuzhiyun #define RT5631_DMIC_DIS (0x0 << 15) 270*4882a593Smuzhiyun #define RT5631_DMIC_L_CH_MUTE (0x1 << 13) 271*4882a593Smuzhiyun #define RT5631_DMIC_L_CH_MUTE_SHIFT 13 272*4882a593Smuzhiyun #define RT5631_DMIC_R_CH_MUTE (0x1 << 12) 273*4882a593Smuzhiyun #define RT5631_DMIC_R_CH_MUTE_SHIFT 12 274*4882a593Smuzhiyun #define RT5631_DMIC_L_CH_LATCH_MASK (0x1 << 9) 275*4882a593Smuzhiyun #define RT5631_DMIC_L_CH_LATCH_RISING (0x1 << 9) 276*4882a593Smuzhiyun #define RT5631_DMIC_L_CH_LATCH_FALLING (0x0 << 9) 277*4882a593Smuzhiyun #define RT5631_DMIC_R_CH_LATCH_MASK (0x1 << 8) 278*4882a593Smuzhiyun #define RT5631_DMIC_R_CH_LATCH_RISING (0x1 << 8) 279*4882a593Smuzhiyun #define RT5631_DMIC_R_CH_LATCH_FALLING (0x0 << 8) 280*4882a593Smuzhiyun #define RT5631_DMIC_CLK_CTRL_MASK (0x3 << 4) 281*4882a593Smuzhiyun #define RT5631_DMIC_CLK_CTRL_TO_128FS (0x0 << 4) 282*4882a593Smuzhiyun #define RT5631_DMIC_CLK_CTRL_TO_64FS (0x1 << 4) 283*4882a593Smuzhiyun #define RT5631_DMIC_CLK_CTRL_TO_32FS (0x2 << 4) 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /* Microphone Input Volume(0x26) */ 286*4882a593Smuzhiyun #define RT5631_MONO_DIFF_INPUT_SHIFT 15 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* Speaker Mixer Control(0x28) */ 289*4882a593Smuzhiyun #define RT5631_M_RECMIXER_L_TO_SPKMIXER_L (0x1 << 15) 290*4882a593Smuzhiyun #define RT5631_M_RECMIXL_SPKMIXL_BIT 15 291*4882a593Smuzhiyun #define RT5631_M_MIC1_P_TO_SPKMIXER_L (0x1 << 14) 292*4882a593Smuzhiyun #define RT5631_M_MIC1P_SPKMIXL_BIT 14 293*4882a593Smuzhiyun #define RT5631_M_DAC_L_TO_SPKMIXER_L (0x1 << 13) 294*4882a593Smuzhiyun #define RT5631_M_DACL_SPKMIXL_BIT 13 295*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_L_TO_SPKMIXER_L (0x1 << 12) 296*4882a593Smuzhiyun #define RT5631_M_OUTMIXL_SPKMIXL_BIT 12 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun #define RT5631_M_RECMIXER_R_TO_SPKMIXER_R (0x1 << 7) 299*4882a593Smuzhiyun #define RT5631_M_RECMIXR_SPKMIXR_BIT 7 300*4882a593Smuzhiyun #define RT5631_M_MIC2_P_TO_SPKMIXER_R (0x1 << 6) 301*4882a593Smuzhiyun #define RT5631_M_MIC2P_SPKMIXR_BIT 6 302*4882a593Smuzhiyun #define RT5631_M_DAC_R_TO_SPKMIXER_R (0x1 << 5) 303*4882a593Smuzhiyun #define RT5631_M_DACR_SPKMIXR_BIT 5 304*4882a593Smuzhiyun #define RT5631_M_OUTMIXER_R_TO_SPKMIXER_R (0x1 << 4) 305*4882a593Smuzhiyun #define RT5631_M_OUTMIXR_SPKMIXR_BIT 4 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* Speaker/Mono Output Control(0x2A) */ 308*4882a593Smuzhiyun #define RT5631_M_SPKVOL_L_TO_SPOL_MIXER (0x1 << 15) 309*4882a593Smuzhiyun #define RT5631_M_SPKVOLL_SPOLMIX_BIT 15 310*4882a593Smuzhiyun #define RT5631_M_SPKVOL_R_TO_SPOL_MIXER (0x1 << 14) 311*4882a593Smuzhiyun #define RT5631_M_SPKVOLR_SPOLMIX_BIT 14 312*4882a593Smuzhiyun #define RT5631_M_SPKVOL_L_TO_SPOR_MIXER (0x1 << 13) 313*4882a593Smuzhiyun #define RT5631_M_SPKVOLL_SPORMIX_BIT 13 314*4882a593Smuzhiyun #define RT5631_M_SPKVOL_R_TO_SPOR_MIXER (0x1 << 12) 315*4882a593Smuzhiyun #define RT5631_M_SPKVOLR_SPORMIX_BIT 12 316*4882a593Smuzhiyun #define RT5631_M_OUTVOL_L_TO_MONOMIXER (0x1 << 11) 317*4882a593Smuzhiyun #define RT5631_M_OUTVOLL_MONOMIX_BIT 11 318*4882a593Smuzhiyun #define RT5631_M_OUTVOL_R_TO_MONOMIXER (0x1 << 10) 319*4882a593Smuzhiyun #define RT5631_M_OUTVOLR_MONOMIX_BIT 10 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun /* Speaker/Mono/HP Output Control(0x2C) */ 322*4882a593Smuzhiyun #define RT5631_SPK_L_MUX_SEL_MASK (0x3 << 14) 323*4882a593Smuzhiyun #define RT5631_SPK_L_MUX_SEL_SPKMIXER_L (0x0 << 14) 324*4882a593Smuzhiyun #define RT5631_SPK_L_MUX_SEL_MONO_IN (0x1 << 14) 325*4882a593Smuzhiyun #define RT5631_SPK_L_MUX_SEL_DAC_L (0x3 << 14) 326*4882a593Smuzhiyun #define RT5631_SPK_L_MUX_SEL_SHIFT 14 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun #define RT5631_SPK_R_MUX_SEL_MASK (0x3 << 10) 329*4882a593Smuzhiyun #define RT5631_SPK_R_MUX_SEL_SPKMIXER_R (0x0 << 10) 330*4882a593Smuzhiyun #define RT5631_SPK_R_MUX_SEL_MONO_IN (0x1 << 10) 331*4882a593Smuzhiyun #define RT5631_SPK_R_MUX_SEL_DAC_R (0x3 << 10) 332*4882a593Smuzhiyun #define RT5631_SPK_R_MUX_SEL_SHIFT 10 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun #define RT5631_MONO_MUX_SEL_MASK (0x3 << 6) 335*4882a593Smuzhiyun #define RT5631_MONO_MUX_SEL_MONOMIXER (0x0 << 6) 336*4882a593Smuzhiyun #define RT5631_MONO_MUX_SEL_MONO_IN (0x1 << 6) 337*4882a593Smuzhiyun #define RT5631_MONO_MUX_SEL_SHIFT 6 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun #define RT5631_HP_L_MUX_SEL_MASK (0x1 << 3) 340*4882a593Smuzhiyun #define RT5631_HP_L_MUX_SEL_HPVOL_L (0x0 << 3) 341*4882a593Smuzhiyun #define RT5631_HP_L_MUX_SEL_DAC_L (0x1 << 3) 342*4882a593Smuzhiyun #define RT5631_HP_L_MUX_SEL_SHIFT 3 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define RT5631_HP_R_MUX_SEL_MASK (0x1 << 2) 345*4882a593Smuzhiyun #define RT5631_HP_R_MUX_SEL_HPVOL_R (0x0 << 2) 346*4882a593Smuzhiyun #define RT5631_HP_R_MUX_SEL_DAC_R (0x1 << 2) 347*4882a593Smuzhiyun #define RT5631_HP_R_MUX_SEL_SHIFT 2 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun /* Stereo I2S Serial Data Port Control(0x34) */ 350*4882a593Smuzhiyun #define RT5631_SDP_MODE_SEL_MASK (0x1 << 15) 351*4882a593Smuzhiyun #define RT5631_SDP_MODE_SEL_MASTER (0x0 << 15) 352*4882a593Smuzhiyun #define RT5631_SDP_MODE_SEL_SLAVE (0x1 << 15) 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun #define RT5631_SDP_ADC_CPS_SEL_MASK (0x3 << 10) 355*4882a593Smuzhiyun #define RT5631_SDP_ADC_CPS_SEL_OFF (0x0 << 10) 356*4882a593Smuzhiyun #define RT5631_SDP_ADC_CPS_SEL_U_LAW (0x1 << 10) 357*4882a593Smuzhiyun #define RT5631_SDP_ADC_CPS_SEL_A_LAW (0x2 << 10) 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #define RT5631_SDP_DAC_CPS_SEL_MASK (0x3 << 8) 360*4882a593Smuzhiyun #define RT5631_SDP_DAC_CPS_SEL_OFF (0x0 << 8) 361*4882a593Smuzhiyun #define RT5631_SDP_DAC_CPS_SEL_U_LAW (0x1 << 8) 362*4882a593Smuzhiyun #define RT5631_SDP_DAC_CPS_SEL_A_LAW (0x2 << 8) 363*4882a593Smuzhiyun /* 0:Normal 1:Invert */ 364*4882a593Smuzhiyun #define RT5631_SDP_I2S_BCLK_POL_CTRL (0x1 << 7) 365*4882a593Smuzhiyun /* 0:Normal 1:Invert */ 366*4882a593Smuzhiyun #define RT5631_SDP_DAC_R_INV (0x1 << 6) 367*4882a593Smuzhiyun /* 0:ADC data appear at left phase of LRCK 368*4882a593Smuzhiyun * 1:ADC data appear at right phase of LRCK 369*4882a593Smuzhiyun */ 370*4882a593Smuzhiyun #define RT5631_SDP_ADC_DATA_L_R_SWAP (0x1 << 5) 371*4882a593Smuzhiyun /* 0:DAC data appear at left phase of LRCK 372*4882a593Smuzhiyun * 1:DAC data appear at right phase of LRCK 373*4882a593Smuzhiyun */ 374*4882a593Smuzhiyun #define RT5631_SDP_DAC_DATA_L_R_SWAP (0x1 << 4) 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* Data Length Slection */ 377*4882a593Smuzhiyun #define RT5631_SDP_I2S_DL_MASK (0x3 << 2) 378*4882a593Smuzhiyun #define RT5631_SDP_I2S_DL_16 (0x0 << 2) 379*4882a593Smuzhiyun #define RT5631_SDP_I2S_DL_20 (0x1 << 2) 380*4882a593Smuzhiyun #define RT5631_SDP_I2S_DL_24 (0x2 << 2) 381*4882a593Smuzhiyun #define RT5631_SDP_I2S_DL_8 (0x3 << 2) 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun /* PCM Data Format Selection */ 384*4882a593Smuzhiyun #define RT5631_SDP_I2S_DF_MASK (0x3) 385*4882a593Smuzhiyun #define RT5631_SDP_I2S_DF_I2S (0x0) 386*4882a593Smuzhiyun #define RT5631_SDP_I2S_DF_LEFT (0x1) 387*4882a593Smuzhiyun #define RT5631_SDP_I2S_DF_PCM_A (0x2) 388*4882a593Smuzhiyun #define RT5631_SDP_I2S_DF_PCM_B (0x3) 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun /* Stereo AD/DA Clock Control(0x38h) */ 391*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_MASK (0x7 << 13) 392*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_1 (0x0 << 13) 393*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_2 (0x1 << 13) 394*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_4 (0x2 << 13) 395*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_8 (0x3 << 13) 396*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_16 (0x4 << 13) 397*4882a593Smuzhiyun #define RT5631_I2S_PRE_DIV_32 (0x5 << 13) 398*4882a593Smuzhiyun /* CLOCK RELATIVE OF BCLK AND LCRK */ 399*4882a593Smuzhiyun #define RT5631_I2S_LRCK_SEL_N_BCLK_MASK (0x1 << 12) 400*4882a593Smuzhiyun #define RT5631_I2S_LRCK_SEL_64_BCLK (0x0 << 12) /* 64FS */ 401*4882a593Smuzhiyun #define RT5631_I2S_LRCK_SEL_32_BCLK (0x1 << 12) /* 32FS */ 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun #define RT5631_DAC_OSR_SEL_MASK (0x3 << 10) 404*4882a593Smuzhiyun #define RT5631_DAC_OSR_SEL_128FS (0x3 << 10) 405*4882a593Smuzhiyun #define RT5631_DAC_OSR_SEL_64FS (0x3 << 10) 406*4882a593Smuzhiyun #define RT5631_DAC_OSR_SEL_32FS (0x3 << 10) 407*4882a593Smuzhiyun #define RT5631_DAC_OSR_SEL_16FS (0x3 << 10) 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun #define RT5631_ADC_OSR_SEL_MASK (0x3 << 8) 410*4882a593Smuzhiyun #define RT5631_ADC_OSR_SEL_128FS (0x3 << 8) 411*4882a593Smuzhiyun #define RT5631_ADC_OSR_SEL_64FS (0x3 << 8) 412*4882a593Smuzhiyun #define RT5631_ADC_OSR_SEL_32FS (0x3 << 8) 413*4882a593Smuzhiyun #define RT5631_ADC_OSR_SEL_16FS (0x3 << 8) 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define RT5631_ADDA_FILTER_CLK_SEL_256FS (0 << 7) /* 256FS */ 416*4882a593Smuzhiyun #define RT5631_ADDA_FILTER_CLK_SEL_384FS (1 << 7) /* 384FS */ 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun /* Power managment addition 1 (0x3A) */ 419*4882a593Smuzhiyun #define RT5631_PWR_MAIN_I2S_EN (0x1 << 15) 420*4882a593Smuzhiyun #define RT5631_PWR_MAIN_I2S_BIT 15 421*4882a593Smuzhiyun #define RT5631_PWR_CLASS_D (0x1 << 12) 422*4882a593Smuzhiyun #define RT5631_PWR_CLASS_D_BIT 12 423*4882a593Smuzhiyun #define RT5631_PWR_ADC_L_CLK (0x1 << 11) 424*4882a593Smuzhiyun #define RT5631_PWR_ADC_L_CLK_BIT 11 425*4882a593Smuzhiyun #define RT5631_PWR_ADC_R_CLK (0x1 << 10) 426*4882a593Smuzhiyun #define RT5631_PWR_ADC_R_CLK_BIT 10 427*4882a593Smuzhiyun #define RT5631_PWR_DAC_L_CLK (0x1 << 9) 428*4882a593Smuzhiyun #define RT5631_PWR_DAC_L_CLK_BIT 9 429*4882a593Smuzhiyun #define RT5631_PWR_DAC_R_CLK (0x1 << 8) 430*4882a593Smuzhiyun #define RT5631_PWR_DAC_R_CLK_BIT 8 431*4882a593Smuzhiyun #define RT5631_PWR_DAC_REF (0x1 << 7) 432*4882a593Smuzhiyun #define RT5631_PWR_DAC_REF_BIT 7 433*4882a593Smuzhiyun #define RT5631_PWR_DAC_L_TO_MIXER (0x1 << 6) 434*4882a593Smuzhiyun #define RT5631_PWR_DAC_L_TO_MIXER_BIT 6 435*4882a593Smuzhiyun #define RT5631_PWR_DAC_R_TO_MIXER (0x1 << 5) 436*4882a593Smuzhiyun #define RT5631_PWR_DAC_R_TO_MIXER_BIT 5 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun /* Power managment addition 2 (0x3B) */ 439*4882a593Smuzhiyun #define RT5631_PWR_OUTMIXER_L (0x1 << 15) 440*4882a593Smuzhiyun #define RT5631_PWR_OUTMIXER_L_BIT 15 441*4882a593Smuzhiyun #define RT5631_PWR_OUTMIXER_R (0x1 << 14) 442*4882a593Smuzhiyun #define RT5631_PWR_OUTMIXER_R_BIT 14 443*4882a593Smuzhiyun #define RT5631_PWR_SPKMIXER_L (0x1 << 13) 444*4882a593Smuzhiyun #define RT5631_PWR_SPKMIXER_L_BIT 13 445*4882a593Smuzhiyun #define RT5631_PWR_SPKMIXER_R (0x1 << 12) 446*4882a593Smuzhiyun #define RT5631_PWR_SPKMIXER_R_BIT 12 447*4882a593Smuzhiyun #define RT5631_PWR_RECMIXER_L (0x1 << 11) 448*4882a593Smuzhiyun #define RT5631_PWR_RECMIXER_L_BIT 11 449*4882a593Smuzhiyun #define RT5631_PWR_RECMIXER_R (0x1 << 10) 450*4882a593Smuzhiyun #define RT5631_PWR_RECMIXER_R_BIT 10 451*4882a593Smuzhiyun #define RT5631_PWR_MIC1_BOOT_GAIN (0x1 << 5) 452*4882a593Smuzhiyun #define RT5631_PWR_MIC1_BOOT_GAIN_BIT 5 453*4882a593Smuzhiyun #define RT5631_PWR_MIC2_BOOT_GAIN (0x1 << 4) 454*4882a593Smuzhiyun #define RT5631_PWR_MIC2_BOOT_GAIN_BIT 4 455*4882a593Smuzhiyun #define RT5631_PWR_MICBIAS1_VOL (0x1 << 3) 456*4882a593Smuzhiyun #define RT5631_PWR_MICBIAS1_VOL_BIT 3 457*4882a593Smuzhiyun #define RT5631_PWR_MICBIAS2_VOL (0x1 << 2) 458*4882a593Smuzhiyun #define RT5631_PWR_MICBIAS2_VOL_BIT 2 459*4882a593Smuzhiyun #define RT5631_PWR_PLL1 (0x1 << 1) 460*4882a593Smuzhiyun #define RT5631_PWR_PLL1_BIT 1 461*4882a593Smuzhiyun #define RT5631_PWR_PLL2 (0x1 << 0) 462*4882a593Smuzhiyun #define RT5631_PWR_PLL2_BIT 0 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun /* Power managment addition 3(0x3C) */ 465*4882a593Smuzhiyun #define RT5631_PWR_VREF (0x1 << 15) 466*4882a593Smuzhiyun #define RT5631_PWR_VREF_BIT 15 467*4882a593Smuzhiyun #define RT5631_PWR_FAST_VREF_CTRL (0x1 << 14) 468*4882a593Smuzhiyun #define RT5631_PWR_FAST_VREF_CTRL_BIT 14 469*4882a593Smuzhiyun #define RT5631_PWR_MAIN_BIAS (0x1 << 13) 470*4882a593Smuzhiyun #define RT5631_PWR_MAIN_BIAS_BIT 13 471*4882a593Smuzhiyun #define RT5631_PWR_AXO1MIXER (0x1 << 11) 472*4882a593Smuzhiyun #define RT5631_PWR_AXO1MIXER_BIT 11 473*4882a593Smuzhiyun #define RT5631_PWR_AXO2MIXER (0x1 << 10) 474*4882a593Smuzhiyun #define RT5631_PWR_AXO2MIXER_BIT 10 475*4882a593Smuzhiyun #define RT5631_PWR_MONOMIXER (0x1 << 9) 476*4882a593Smuzhiyun #define RT5631_PWR_MONOMIXER_BIT 9 477*4882a593Smuzhiyun #define RT5631_PWR_MONO_DEPOP_DIS (0x1 << 8) 478*4882a593Smuzhiyun #define RT5631_PWR_MONO_DEPOP_DIS_BIT 8 479*4882a593Smuzhiyun #define RT5631_PWR_MONO_AMP_EN (0x1 << 7) 480*4882a593Smuzhiyun #define RT5631_PWR_MONO_AMP_EN_BIT 7 481*4882a593Smuzhiyun #define RT5631_PWR_CHARGE_PUMP (0x1 << 4) 482*4882a593Smuzhiyun #define RT5631_PWR_CHARGE_PUMP_BIT 4 483*4882a593Smuzhiyun #define RT5631_PWR_HP_L_AMP (0x1 << 3) 484*4882a593Smuzhiyun #define RT5631_PWR_HP_L_AMP_BIT 3 485*4882a593Smuzhiyun #define RT5631_PWR_HP_R_AMP (0x1 << 2) 486*4882a593Smuzhiyun #define RT5631_PWR_HP_R_AMP_BIT 2 487*4882a593Smuzhiyun #define RT5631_PWR_HP_DEPOP_DIS (0x1 << 1) 488*4882a593Smuzhiyun #define RT5631_PWR_HP_DEPOP_DIS_BIT 1 489*4882a593Smuzhiyun #define RT5631_PWR_HP_AMP_DRIVING (0x1 << 0) 490*4882a593Smuzhiyun #define RT5631_PWR_HP_AMP_DRIVING_BIT 0 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun /* Power managment addition 4(0x3E) */ 493*4882a593Smuzhiyun #define RT5631_PWR_SPK_L_VOL (0x1 << 15) 494*4882a593Smuzhiyun #define RT5631_PWR_SPK_L_VOL_BIT 15 495*4882a593Smuzhiyun #define RT5631_PWR_SPK_R_VOL (0x1 << 14) 496*4882a593Smuzhiyun #define RT5631_PWR_SPK_R_VOL_BIT 14 497*4882a593Smuzhiyun #define RT5631_PWR_LOUT_VOL (0x1 << 13) 498*4882a593Smuzhiyun #define RT5631_PWR_LOUT_VOL_BIT 13 499*4882a593Smuzhiyun #define RT5631_PWR_ROUT_VOL (0x1 << 12) 500*4882a593Smuzhiyun #define RT5631_PWR_ROUT_VOL_BIT 12 501*4882a593Smuzhiyun #define RT5631_PWR_HP_L_OUT_VOL (0x1 << 11) 502*4882a593Smuzhiyun #define RT5631_PWR_HP_L_OUT_VOL_BIT 11 503*4882a593Smuzhiyun #define RT5631_PWR_HP_R_OUT_VOL (0x1 << 10) 504*4882a593Smuzhiyun #define RT5631_PWR_HP_R_OUT_VOL_BIT 10 505*4882a593Smuzhiyun #define RT5631_PWR_AXIL_IN_VOL (0x1 << 9) 506*4882a593Smuzhiyun #define RT5631_PWR_AXIL_IN_VOL_BIT 9 507*4882a593Smuzhiyun #define RT5631_PWR_AXIR_IN_VOL (0x1 << 8) 508*4882a593Smuzhiyun #define RT5631_PWR_AXIR_IN_VOL_BIT 8 509*4882a593Smuzhiyun #define RT5631_PWR_MONO_IN_P_VOL (0x1 << 7) 510*4882a593Smuzhiyun #define RT5631_PWR_MONO_IN_P_VOL_BIT 7 511*4882a593Smuzhiyun #define RT5631_PWR_MONO_IN_N_VOL (0x1 << 6) 512*4882a593Smuzhiyun #define RT5631_PWR_MONO_IN_N_VOL_BIT 6 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun /* General Purpose Control Register(0x40) */ 515*4882a593Smuzhiyun #define RT5631_SPK_AMP_AUTO_RATIO_EN (0x1 << 15) 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_MASK (0x7 << 12) 518*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_2_34 (0x0 << 12) /* 7.40DB */ 519*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_99 (0x1 << 12) /* 5.99DB */ 520*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_68 (0x2 << 12) /* 4.50DB */ 521*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_56 (0x3 << 12) /* 3.86DB */ 522*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_44 (0x4 << 12) /* 3.16DB */ 523*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_27 (0x5 << 12) /* 2.10DB */ 524*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_09 (0x6 << 12) /* 0.80DB */ 525*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_1_00 (0x7 << 12) /* 0.00DB */ 526*4882a593Smuzhiyun #define RT5631_SPK_AMP_RATIO_CTRL_SHIFT 12 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun #define RT5631_STEREO_DAC_HI_PASS_FILT_EN (0x1 << 11) 529*4882a593Smuzhiyun #define RT5631_STEREO_ADC_HI_PASS_FILT_EN (0x1 << 10) 530*4882a593Smuzhiyun /* Select ADC Wind Filter Clock type */ 531*4882a593Smuzhiyun #define RT5631_ADC_WIND_FILT_MASK (0x3 << 4) 532*4882a593Smuzhiyun #define RT5631_ADC_WIND_FILT_8_16_32K (0x0 << 4) /*8/16/32k*/ 533*4882a593Smuzhiyun #define RT5631_ADC_WIND_FILT_11_22_44K (0x1 << 4) /*11/22/44k*/ 534*4882a593Smuzhiyun #define RT5631_ADC_WIND_FILT_12_24_48K (0x2 << 4) /*12/24/48k*/ 535*4882a593Smuzhiyun #define RT5631_ADC_WIND_FILT_EN (0x1 << 3) 536*4882a593Smuzhiyun /* SelectADC Wind Filter Corner Frequency */ 537*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_MASK (0x7 << 0) 538*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_82_113_122 (0x0 << 0) /* 82/113/122 Hz */ 539*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_102_141_153 (0x1 << 0) /* 102/141/153 Hz */ 540*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_131_180_156 (0x2 << 0) /* 131/180/156 Hz */ 541*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_163_225_245 (0x3 << 0) /* 163/225/245 Hz */ 542*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_204_281_306 (0x4 << 0) /* 204/281/306 Hz */ 543*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_261_360_392 (0x5 << 0) /* 261/360/392 Hz */ 544*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_327_450_490 (0x6 << 0) /* 327/450/490 Hz */ 545*4882a593Smuzhiyun #define RT5631_ADC_WIND_CNR_FREQ_408_563_612 (0x7 << 0) /* 408/563/612 Hz */ 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /* Global Clock Control Register(0x42) */ 548*4882a593Smuzhiyun #define RT5631_SYSCLK_SOUR_SEL_MASK (0x3 << 14) 549*4882a593Smuzhiyun #define RT5631_SYSCLK_SOUR_SEL_MCLK (0x0 << 14) 550*4882a593Smuzhiyun #define RT5631_SYSCLK_SOUR_SEL_PLL (0x1 << 14) 551*4882a593Smuzhiyun #define RT5631_SYSCLK_SOUR_SEL_PLL_TCK (0x2 << 14) 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun #define RT5631_PLLCLK_SOUR_SEL_MASK (0x3 << 12) 554*4882a593Smuzhiyun #define RT5631_PLLCLK_SOUR_SEL_MCLK (0x0 << 12) 555*4882a593Smuzhiyun #define RT5631_PLLCLK_SOUR_SEL_BCLK (0x1 << 12) 556*4882a593Smuzhiyun #define RT5631_PLLCLK_SOUR_SEL_VBCLK (0x2 << 12) 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun #define RT5631_PLLCLK_PRE_DIV1 (0x0 << 11) 559*4882a593Smuzhiyun #define RT5631_PLLCLK_PRE_DIV2 (0x1 << 11) 560*4882a593Smuzhiyun 561*4882a593Smuzhiyun /* PLL Control(0x44) */ 562*4882a593Smuzhiyun #define RT5631_PLL_CTRL_M_VAL(m) ((m)&0xf) 563*4882a593Smuzhiyun #define RT5631_PLL_CTRL_K_VAL(k) (((k)&0x7) << 4) 564*4882a593Smuzhiyun #define RT5631_PLL_CTRL_N_VAL(n) (((n)&0xff) << 8) 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun /* Internal Status and IRQ Control2(0x4A) */ 567*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_MASK (0x3 << 14) 568*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_Disable (0x0 << 14) 569*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_MIC1 (0x1 << 14) 570*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_MIC1_SHIFT 14 571*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_MIC2 (0x2 << 14) 572*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_MIC2_SHIFT 15 573*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_STO (0x3 << 14) 574*4882a593Smuzhiyun #define RT5631_ADC_DATA_SEL_SHIFT 14 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun /* GPIO Pin Configuration(0x4C) */ 577*4882a593Smuzhiyun #define RT5631_GPIO_PIN_FUN_SEL_MASK (0x1 << 15) 578*4882a593Smuzhiyun #define RT5631_GPIO_PIN_FUN_SEL_IRQ (0x1 << 15) 579*4882a593Smuzhiyun #define RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC (0x0 << 15) 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun #define RT5631_GPIO_DMIC_FUN_SEL_MASK (0x1 << 3) 582*4882a593Smuzhiyun #define RT5631_GPIO_DMIC_FUN_SEL_DIMC (0x1 << 3) 583*4882a593Smuzhiyun #define RT5631_GPIO_DMIC_FUN_SEL_GPIO (0x0 << 3) 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun #define RT5631_GPIO_PIN_CON_MASK (0x1 << 2) 586*4882a593Smuzhiyun #define RT5631_GPIO_PIN_SET_INPUT (0x0 << 2) 587*4882a593Smuzhiyun #define RT5631_GPIO_PIN_SET_OUTPUT (0x1 << 2) 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun /* De-POP function Control 1(0x54) */ 590*4882a593Smuzhiyun #define RT5631_POW_ON_SOFT_GEN (0x1 << 15) 591*4882a593Smuzhiyun #define RT5631_EN_MUTE_UNMUTE_DEPOP (0x1 << 14) 592*4882a593Smuzhiyun #define RT5631_EN_DEPOP2_FOR_HP (0x1 << 7) 593*4882a593Smuzhiyun /* Power Down HPAMP_L Starts Up Signal */ 594*4882a593Smuzhiyun #define RT5631_PD_HPAMP_L_ST_UP (0x1 << 5) 595*4882a593Smuzhiyun /* Power Down HPAMP_R Starts Up Signal */ 596*4882a593Smuzhiyun #define RT5631_PD_HPAMP_R_ST_UP (0x1 << 4) 597*4882a593Smuzhiyun /* Enable left HP mute/unmute depop */ 598*4882a593Smuzhiyun #define RT5631_EN_HP_L_M_UN_MUTE_DEPOP (0x1 << 1) 599*4882a593Smuzhiyun /* Enable right HP mute/unmute depop */ 600*4882a593Smuzhiyun #define RT5631_EN_HP_R_M_UN_MUTE_DEPOP (0x1 << 0) 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun /* De-POP Fnction Control(0x56) */ 603*4882a593Smuzhiyun #define RT5631_EN_ONE_BIT_DEPOP (0x1 << 15) 604*4882a593Smuzhiyun #define RT5631_EN_CAP_FREE_DEPOP (0x1 << 14) 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun /* Jack Detect Control Register(0x5A) */ 607*4882a593Smuzhiyun #define RT5631_JD_USE_MASK (0x3 << 14) 608*4882a593Smuzhiyun #define RT5631_JD_USE_JD2 (0x3 << 14) 609*4882a593Smuzhiyun #define RT5631_JD_USE_JD1 (0x2 << 14) 610*4882a593Smuzhiyun #define RT5631_JD_USE_GPIO (0x1 << 14) 611*4882a593Smuzhiyun #define RT5631_JD_OFF (0x0 << 14) 612*4882a593Smuzhiyun /* JD trigger enable for HP */ 613*4882a593Smuzhiyun #define RT5631_JD_HP_EN (0x1 << 11) 614*4882a593Smuzhiyun #define RT5631_JD_HP_TRI_MASK (0x1 << 10) 615*4882a593Smuzhiyun #define RT5631_JD_HP_TRI_HI (0x1 << 10) 616*4882a593Smuzhiyun #define RT5631_JD_HP_TRI_LO (0x1 << 10) 617*4882a593Smuzhiyun /* JD trigger enable for speaker LP/LN */ 618*4882a593Smuzhiyun #define RT5631_JD_SPK_L_EN (0x1 << 9) 619*4882a593Smuzhiyun #define RT5631_JD_SPK_L_TRI_MASK (0x1 << 8) 620*4882a593Smuzhiyun #define RT5631_JD_SPK_L_TRI_HI (0x1 << 8) 621*4882a593Smuzhiyun #define RT5631_JD_SPK_L_TRI_LO (0x0 << 8) 622*4882a593Smuzhiyun /* JD trigger enable for speaker RP/RN */ 623*4882a593Smuzhiyun #define RT5631_JD_SPK_R_EN (0x1 << 7) 624*4882a593Smuzhiyun #define RT5631_JD_SPK_R_TRI_MASK (0x1 << 6) 625*4882a593Smuzhiyun #define RT5631_JD_SPK_R_TRI_HI (0x1 << 6) 626*4882a593Smuzhiyun #define RT5631_JD_SPK_R_TRI_LO (0x0 << 6) 627*4882a593Smuzhiyun /* JD trigger enable for monoout */ 628*4882a593Smuzhiyun #define RT5631_JD_MONO_EN (0x1 << 5) 629*4882a593Smuzhiyun #define RT5631_JD_MONO_TRI_MASK (0x1 << 4) 630*4882a593Smuzhiyun #define RT5631_JD_MONO_TRI_HI (0x1 << 4) 631*4882a593Smuzhiyun #define RT5631_JD_MONO_TRI_LO (0x0 << 4) 632*4882a593Smuzhiyun /* JD trigger enable for Lout */ 633*4882a593Smuzhiyun #define RT5631_JD_AUX_1_EN (0x1 << 3) 634*4882a593Smuzhiyun #define RT5631_JD_AUX_1_MASK (0x1 << 2) 635*4882a593Smuzhiyun #define RT5631_JD_AUX_1_TRI_HI (0x1 << 2) 636*4882a593Smuzhiyun #define RT5631_JD_AUX_1_TRI_LO (0x0 << 2) 637*4882a593Smuzhiyun /* JD trigger enable for Rout */ 638*4882a593Smuzhiyun #define RT5631_JD_AUX_2_EN (0x1 << 1) 639*4882a593Smuzhiyun #define RT5631_JD_AUX_2_MASK (0x1 << 0) 640*4882a593Smuzhiyun #define RT5631_JD_AUX_2_TRI_HI (0x1 << 0) 641*4882a593Smuzhiyun #define RT5631_JD_AUX_2_TRI_LO (0x0 << 0) 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun /* ALC CONTROL 1(0x64) */ 644*4882a593Smuzhiyun #define RT5631_ALC_ATTACK_RATE_MASK (0x1F << 8) 645*4882a593Smuzhiyun #define RT5631_ALC_RECOVERY_RATE_MASK (0x1F << 0) 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun /* ALC CONTROL 2(0x65) */ 648*4882a593Smuzhiyun /* select Compensation gain for Noise gate function */ 649*4882a593Smuzhiyun #define RT5631_ALC_COM_NOISE_GATE_MASK (0xF << 0) 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun /* ALC CONTROL 3(0x66) */ 652*4882a593Smuzhiyun #define RT5631_ALC_FUN_MASK (0x3 << 14) 653*4882a593Smuzhiyun #define RT5631_ALC_FUN_DIS (0x0 << 14) 654*4882a593Smuzhiyun #define RT5631_ALC_ENA_DAC_PATH (0x1 << 14) 655*4882a593Smuzhiyun #define RT5631_ALC_ENA_ADC_PATH (0x3 << 14) 656*4882a593Smuzhiyun #define RT5631_ALC_PARA_UPDATE (0x1 << 13) 657*4882a593Smuzhiyun #define RT5631_ALC_LIMIT_LEVEL_MASK (0x1F << 8) 658*4882a593Smuzhiyun #define RT5631_ALC_NOISE_GATE_FUN_MASK (0x1 << 7) 659*4882a593Smuzhiyun #define RT5631_ALC_NOISE_GATE_FUN_DIS (0x0 << 7) 660*4882a593Smuzhiyun #define RT5631_ALC_NOISE_GATE_FUN_ENA (0x1 << 7) 661*4882a593Smuzhiyun /* ALC noise gate hold data function */ 662*4882a593Smuzhiyun #define RT5631_ALC_NOISE_GATE_H_D_MASK (0x1 << 6) 663*4882a593Smuzhiyun #define RT5631_ALC_NOISE_GATE_H_D_DIS (0x0 << 6) 664*4882a593Smuzhiyun #define RT5631_ALC_NOISE_GATE_H_D_ENA (0x1 << 6) 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun /* Psedueo Stereo & Spatial Effect Block Control(0x68) */ 667*4882a593Smuzhiyun #define RT5631_SPATIAL_CTRL_EN (0x1 << 15) 668*4882a593Smuzhiyun #define RT5631_ALL_PASS_FILTER_EN (0x1 << 14) 669*4882a593Smuzhiyun #define RT5631_PSEUDO_STEREO_EN (0x1 << 13) 670*4882a593Smuzhiyun #define RT5631_STEREO_EXPENSION_EN (0x1 << 12) 671*4882a593Smuzhiyun /* 3D gain parameter */ 672*4882a593Smuzhiyun #define RT5631_GAIN_3D_PARA_MASK (0x3 << 6) 673*4882a593Smuzhiyun #define RT5631_GAIN_3D_PARA_1_00 (0x0 << 6) /* 3D gain 1.0 */ 674*4882a593Smuzhiyun #define RT5631_GAIN_3D_PARA_1_50 (0x1 << 6) /* 3D gain 1.5 */ 675*4882a593Smuzhiyun #define RT5631_GAIN_3D_PARA_2_00 (0x2 << 6) /* 3D gain 2.0 */ 676*4882a593Smuzhiyun /* 3D ratio parameter */ 677*4882a593Smuzhiyun #define RT5631_RATIO_3D_MASK (0x3 << 4) 678*4882a593Smuzhiyun #define RT5631_RATIO_3D_0_0 (0x0 << 4) /* 3D ratio 0.0 */ 679*4882a593Smuzhiyun #define RT5631_RATIO_3D_0_66 (0x1 << 4) /* 3D ratio 0.66 */ 680*4882a593Smuzhiyun #define RT5631_RATIO_3D_1_0 (0x2 << 4) /* 3D ratio 1.0 */ 681*4882a593Smuzhiyun /* select samplerate for all pass filter */ 682*4882a593Smuzhiyun #define RT5631_APF_FUN_SLE_MASK (0x3 << 0) 683*4882a593Smuzhiyun #define RT5631_APF_FUN_SEL_48K (0x3 << 0) 684*4882a593Smuzhiyun #define RT5631_APF_FUN_SEL_44_1K (0x2 << 0) 685*4882a593Smuzhiyun #define RT5631_APF_FUN_SEL_32K (0x1 << 0) 686*4882a593Smuzhiyun #define RT5631_APF_FUN_DIS (0x0 << 0) 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun /* EQ CONTROL 1(0x6E) */ 689*4882a593Smuzhiyun #define RT5631_HW_EQ_PATH_SEL_MASK (0x1 << 15) 690*4882a593Smuzhiyun #define RT5631_HW_EQ_PATH_SEL_DAC (0x0 << 15) 691*4882a593Smuzhiyun #define RT5631_HW_EQ_PATH_SEL_ADC (0x1 << 15) 692*4882a593Smuzhiyun #define RT5631_HW_EQ_UPDATE_CTRL (0x1 << 14) 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun #define RT5631_EN_HW_EQ_HPF2 (0x1 << 5) 695*4882a593Smuzhiyun #define RT5631_EN_HW_EQ_HPF1 (0x1 << 4) 696*4882a593Smuzhiyun #define RT5631_EN_HW_EQ_BP3 (0x1 << 3) 697*4882a593Smuzhiyun #define RT5631_EN_HW_EQ_BP2 (0x1 << 2) 698*4882a593Smuzhiyun #define RT5631_EN_HW_EQ_BP1 (0x1 << 1) 699*4882a593Smuzhiyun #define RT5631_EN_HW_EQ_LPF (0x1 << 0) 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun #endif /* __RTCODEC5631_H__ */ 703