1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This software is available to you under a choice of one of two 5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 8*4882a593Smuzhiyun * OpenIB.org BSD license below: 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 11*4882a593Smuzhiyun * without modification, are permitted provided that the following 12*4882a593Smuzhiyun * conditions are met: 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * - Redistributions of source code must retain the above 15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 16*4882a593Smuzhiyun * disclaimer. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 21*4882a593Smuzhiyun * provided with the distribution. 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30*4882a593Smuzhiyun * SOFTWARE. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* This file is mechanically generated from RTL. Any hand-edits will be lost! */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define QIB_6120_Revision_OFFS 0x0 36*4882a593Smuzhiyun #define QIB_6120_Revision_R_Simulator_LSB 0x3F 37*4882a593Smuzhiyun #define QIB_6120_Revision_R_Simulator_RMASK 0x1 38*4882a593Smuzhiyun #define QIB_6120_Revision_Reserved_LSB 0x28 39*4882a593Smuzhiyun #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF 40*4882a593Smuzhiyun #define QIB_6120_Revision_BoardID_LSB 0x20 41*4882a593Smuzhiyun #define QIB_6120_Revision_BoardID_RMASK 0xFF 42*4882a593Smuzhiyun #define QIB_6120_Revision_R_SW_LSB 0x18 43*4882a593Smuzhiyun #define QIB_6120_Revision_R_SW_RMASK 0xFF 44*4882a593Smuzhiyun #define QIB_6120_Revision_R_Arch_LSB 0x10 45*4882a593Smuzhiyun #define QIB_6120_Revision_R_Arch_RMASK 0xFF 46*4882a593Smuzhiyun #define QIB_6120_Revision_R_ChipRevMajor_LSB 0x8 47*4882a593Smuzhiyun #define QIB_6120_Revision_R_ChipRevMajor_RMASK 0xFF 48*4882a593Smuzhiyun #define QIB_6120_Revision_R_ChipRevMinor_LSB 0x0 49*4882a593Smuzhiyun #define QIB_6120_Revision_R_ChipRevMinor_RMASK 0xFF 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define QIB_6120_Control_OFFS 0x8 52*4882a593Smuzhiyun #define QIB_6120_Control_TxLatency_LSB 0x4 53*4882a593Smuzhiyun #define QIB_6120_Control_TxLatency_RMASK 0x1 54*4882a593Smuzhiyun #define QIB_6120_Control_PCIERetryBufDiagEn_LSB 0x3 55*4882a593Smuzhiyun #define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x1 56*4882a593Smuzhiyun #define QIB_6120_Control_LinkEn_LSB 0x2 57*4882a593Smuzhiyun #define QIB_6120_Control_LinkEn_RMASK 0x1 58*4882a593Smuzhiyun #define QIB_6120_Control_FreezeMode_LSB 0x1 59*4882a593Smuzhiyun #define QIB_6120_Control_FreezeMode_RMASK 0x1 60*4882a593Smuzhiyun #define QIB_6120_Control_SyncReset_LSB 0x0 61*4882a593Smuzhiyun #define QIB_6120_Control_SyncReset_RMASK 0x1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define QIB_6120_PageAlign_OFFS 0x10 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define QIB_6120_PortCnt_OFFS 0x18 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define QIB_6120_SendRegBase_OFFS 0x30 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define QIB_6120_UserRegBase_OFFS 0x38 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define QIB_6120_CntrRegBase_OFFS 0x40 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define QIB_6120_Scratch_OFFS 0x48 74*4882a593Smuzhiyun #define QIB_6120_Scratch_TopHalf_LSB 0x20 75*4882a593Smuzhiyun #define QIB_6120_Scratch_TopHalf_RMASK 0xFFFFFFFF 76*4882a593Smuzhiyun #define QIB_6120_Scratch_BottomHalf_LSB 0x0 77*4882a593Smuzhiyun #define QIB_6120_Scratch_BottomHalf_RMASK 0xFFFFFFFF 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define QIB_6120_IntBlocked_OFFS 0x60 80*4882a593Smuzhiyun #define QIB_6120_IntBlocked_ErrorIntBlocked_LSB 0x1F 81*4882a593Smuzhiyun #define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x1 82*4882a593Smuzhiyun #define QIB_6120_IntBlocked_PioSetIntBlocked_LSB 0x1E 83*4882a593Smuzhiyun #define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x1 84*4882a593Smuzhiyun #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_LSB 0x1D 85*4882a593Smuzhiyun #define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x1 86*4882a593Smuzhiyun #define QIB_6120_IntBlocked_assertGPIOIntBlocked_LSB 0x1C 87*4882a593Smuzhiyun #define QIB_6120_IntBlocked_assertGPIOIntBlocked_RMASK 0x1 88*4882a593Smuzhiyun #define QIB_6120_IntBlocked_Reserved_LSB 0xF 89*4882a593Smuzhiyun #define QIB_6120_IntBlocked_Reserved_RMASK 0x1FFF 90*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail4IntBlocked_LSB 0x10 91*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail4IntBlocked_RMASK 0x1 92*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail3IntBlocked_LSB 0xF 93*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail3IntBlocked_RMASK 0x1 94*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail2IntBlocked_LSB 0xE 95*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail2IntBlocked_RMASK 0x1 96*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail1IntBlocked_LSB 0xD 97*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail1IntBlocked_RMASK 0x1 98*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail0IntBlocked_LSB 0xC 99*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvAvail0IntBlocked_RMASK 0x1 100*4882a593Smuzhiyun #define QIB_6120_IntBlocked_Reserved1_LSB 0x5 101*4882a593Smuzhiyun #define QIB_6120_IntBlocked_Reserved1_RMASK 0x7F 102*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg4IntBlocked_LSB 0x4 103*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg4IntBlocked_RMASK 0x1 104*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg3IntBlocked_LSB 0x3 105*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg3IntBlocked_RMASK 0x1 106*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg2IntBlocked_LSB 0x2 107*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg2IntBlocked_RMASK 0x1 108*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg1IntBlocked_LSB 0x1 109*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg1IntBlocked_RMASK 0x1 110*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg0IntBlocked_LSB 0x0 111*4882a593Smuzhiyun #define QIB_6120_IntBlocked_RcvUrg0IntBlocked_RMASK 0x1 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define QIB_6120_IntMask_OFFS 0x68 114*4882a593Smuzhiyun #define QIB_6120_IntMask_ErrorIntMask_LSB 0x1F 115*4882a593Smuzhiyun #define QIB_6120_IntMask_ErrorIntMask_RMASK 0x1 116*4882a593Smuzhiyun #define QIB_6120_IntMask_PioSetIntMask_LSB 0x1E 117*4882a593Smuzhiyun #define QIB_6120_IntMask_PioSetIntMask_RMASK 0x1 118*4882a593Smuzhiyun #define QIB_6120_IntMask_PioBufAvailIntMask_LSB 0x1D 119*4882a593Smuzhiyun #define QIB_6120_IntMask_PioBufAvailIntMask_RMASK 0x1 120*4882a593Smuzhiyun #define QIB_6120_IntMask_assertGPIOIntMask_LSB 0x1C 121*4882a593Smuzhiyun #define QIB_6120_IntMask_assertGPIOIntMask_RMASK 0x1 122*4882a593Smuzhiyun #define QIB_6120_IntMask_Reserved_LSB 0x11 123*4882a593Smuzhiyun #define QIB_6120_IntMask_Reserved_RMASK 0x7FF 124*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail4IntMask_LSB 0x10 125*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail4IntMask_RMASK 0x1 126*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail3IntMask_LSB 0xF 127*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail3IntMask_RMASK 0x1 128*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail2IntMask_LSB 0xE 129*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail2IntMask_RMASK 0x1 130*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail1IntMask_LSB 0xD 131*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail1IntMask_RMASK 0x1 132*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail0IntMask_LSB 0xC 133*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvAvail0IntMask_RMASK 0x1 134*4882a593Smuzhiyun #define QIB_6120_IntMask_Reserved1_LSB 0x5 135*4882a593Smuzhiyun #define QIB_6120_IntMask_Reserved1_RMASK 0x7F 136*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg4IntMask_LSB 0x4 137*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg4IntMask_RMASK 0x1 138*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg3IntMask_LSB 0x3 139*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg3IntMask_RMASK 0x1 140*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg2IntMask_LSB 0x2 141*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg2IntMask_RMASK 0x1 142*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg1IntMask_LSB 0x1 143*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg1IntMask_RMASK 0x1 144*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg0IntMask_LSB 0x0 145*4882a593Smuzhiyun #define QIB_6120_IntMask_RcvUrg0IntMask_RMASK 0x1 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define QIB_6120_IntStatus_OFFS 0x70 148*4882a593Smuzhiyun #define QIB_6120_IntStatus_Error_LSB 0x1F 149*4882a593Smuzhiyun #define QIB_6120_IntStatus_Error_RMASK 0x1 150*4882a593Smuzhiyun #define QIB_6120_IntStatus_PioSent_LSB 0x1E 151*4882a593Smuzhiyun #define QIB_6120_IntStatus_PioSent_RMASK 0x1 152*4882a593Smuzhiyun #define QIB_6120_IntStatus_PioBufAvail_LSB 0x1D 153*4882a593Smuzhiyun #define QIB_6120_IntStatus_PioBufAvail_RMASK 0x1 154*4882a593Smuzhiyun #define QIB_6120_IntStatus_assertGPIO_LSB 0x1C 155*4882a593Smuzhiyun #define QIB_6120_IntStatus_assertGPIO_RMASK 0x1 156*4882a593Smuzhiyun #define QIB_6120_IntStatus_Reserved_LSB 0xF 157*4882a593Smuzhiyun #define QIB_6120_IntStatus_Reserved_RMASK 0x1FFF 158*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail4_LSB 0x10 159*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail4_RMASK 0x1 160*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail3_LSB 0xF 161*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail3_RMASK 0x1 162*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail2_LSB 0xE 163*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail2_RMASK 0x1 164*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail1_LSB 0xD 165*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail1_RMASK 0x1 166*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail0_LSB 0xC 167*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvAvail0_RMASK 0x1 168*4882a593Smuzhiyun #define QIB_6120_IntStatus_Reserved1_LSB 0x5 169*4882a593Smuzhiyun #define QIB_6120_IntStatus_Reserved1_RMASK 0x7F 170*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg4_LSB 0x4 171*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg4_RMASK 0x1 172*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg3_LSB 0x3 173*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg3_RMASK 0x1 174*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg2_LSB 0x2 175*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg2_RMASK 0x1 176*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg1_LSB 0x1 177*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg1_RMASK 0x1 178*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg0_LSB 0x0 179*4882a593Smuzhiyun #define QIB_6120_IntStatus_RcvUrg0_RMASK 0x1 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define QIB_6120_IntClear_OFFS 0x78 182*4882a593Smuzhiyun #define QIB_6120_IntClear_ErrorIntClear_LSB 0x1F 183*4882a593Smuzhiyun #define QIB_6120_IntClear_ErrorIntClear_RMASK 0x1 184*4882a593Smuzhiyun #define QIB_6120_IntClear_PioSetIntClear_LSB 0x1E 185*4882a593Smuzhiyun #define QIB_6120_IntClear_PioSetIntClear_RMASK 0x1 186*4882a593Smuzhiyun #define QIB_6120_IntClear_PioBufAvailIntClear_LSB 0x1D 187*4882a593Smuzhiyun #define QIB_6120_IntClear_PioBufAvailIntClear_RMASK 0x1 188*4882a593Smuzhiyun #define QIB_6120_IntClear_assertGPIOIntClear_LSB 0x1C 189*4882a593Smuzhiyun #define QIB_6120_IntClear_assertGPIOIntClear_RMASK 0x1 190*4882a593Smuzhiyun #define QIB_6120_IntClear_Reserved_LSB 0xF 191*4882a593Smuzhiyun #define QIB_6120_IntClear_Reserved_RMASK 0x1FFF 192*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail4IntClear_LSB 0x10 193*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail4IntClear_RMASK 0x1 194*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail3IntClear_LSB 0xF 195*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail3IntClear_RMASK 0x1 196*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail2IntClear_LSB 0xE 197*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail2IntClear_RMASK 0x1 198*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail1IntClear_LSB 0xD 199*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail1IntClear_RMASK 0x1 200*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail0IntClear_LSB 0xC 201*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvAvail0IntClear_RMASK 0x1 202*4882a593Smuzhiyun #define QIB_6120_IntClear_Reserved1_LSB 0x5 203*4882a593Smuzhiyun #define QIB_6120_IntClear_Reserved1_RMASK 0x7F 204*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg4IntClear_LSB 0x4 205*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg4IntClear_RMASK 0x1 206*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg3IntClear_LSB 0x3 207*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg3IntClear_RMASK 0x1 208*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg2IntClear_LSB 0x2 209*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg2IntClear_RMASK 0x1 210*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg1IntClear_LSB 0x1 211*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg1IntClear_RMASK 0x1 212*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg0IntClear_LSB 0x0 213*4882a593Smuzhiyun #define QIB_6120_IntClear_RcvUrg0IntClear_RMASK 0x1 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #define QIB_6120_ErrMask_OFFS 0x80 216*4882a593Smuzhiyun #define QIB_6120_ErrMask_Reserved_LSB 0x34 217*4882a593Smuzhiyun #define QIB_6120_ErrMask_Reserved_RMASK 0xFFF 218*4882a593Smuzhiyun #define QIB_6120_ErrMask_HardwareErrMask_LSB 0x33 219*4882a593Smuzhiyun #define QIB_6120_ErrMask_HardwareErrMask_RMASK 0x1 220*4882a593Smuzhiyun #define QIB_6120_ErrMask_ResetNegatedMask_LSB 0x32 221*4882a593Smuzhiyun #define QIB_6120_ErrMask_ResetNegatedMask_RMASK 0x1 222*4882a593Smuzhiyun #define QIB_6120_ErrMask_InvalidAddrErrMask_LSB 0x31 223*4882a593Smuzhiyun #define QIB_6120_ErrMask_InvalidAddrErrMask_RMASK 0x1 224*4882a593Smuzhiyun #define QIB_6120_ErrMask_IBStatusChangedMask_LSB 0x30 225*4882a593Smuzhiyun #define QIB_6120_ErrMask_IBStatusChangedMask_RMASK 0x1 226*4882a593Smuzhiyun #define QIB_6120_ErrMask_Reserved1_LSB 0x26 227*4882a593Smuzhiyun #define QIB_6120_ErrMask_Reserved1_RMASK 0x3FF 228*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendUnsupportedVLErrMask_LSB 0x25 229*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1 230*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_LSB 0x24 231*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1 232*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendPioArmLaunchErrMask_LSB 0x23 233*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1 234*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendDroppedDataPktErrMask_LSB 0x22 235*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1 236*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_LSB 0x21 237*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1 238*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendPktLenErrMask_LSB 0x20 239*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendPktLenErrMask_RMASK 0x1 240*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendUnderRunErrMask_LSB 0x1F 241*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendUnderRunErrMask_RMASK 0x1 242*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendMaxPktLenErrMask_LSB 0x1E 243*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendMaxPktLenErrMask_RMASK 0x1 244*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendMinPktLenErrMask_LSB 0x1D 245*4882a593Smuzhiyun #define QIB_6120_ErrMask_SendMinPktLenErrMask_RMASK 0x1 246*4882a593Smuzhiyun #define QIB_6120_ErrMask_Reserved2_LSB 0x12 247*4882a593Smuzhiyun #define QIB_6120_ErrMask_Reserved2_RMASK 0x7FF 248*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvIBLostLinkErrMask_LSB 0x11 249*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1 250*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvHdrErrMask_LSB 0x10 251*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvHdrErrMask_RMASK 0x1 252*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvHdrLenErrMask_LSB 0xF 253*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvHdrLenErrMask_RMASK 0x1 254*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvBadTidErrMask_LSB 0xE 255*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvBadTidErrMask_RMASK 0x1 256*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvHdrFullErrMask_LSB 0xD 257*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvHdrFullErrMask_RMASK 0x1 258*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvEgrFullErrMask_LSB 0xC 259*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvEgrFullErrMask_RMASK 0x1 260*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvBadVersionErrMask_LSB 0xB 261*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvBadVersionErrMask_RMASK 0x1 262*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvIBFlowErrMask_LSB 0xA 263*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvIBFlowErrMask_RMASK 0x1 264*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvEBPErrMask_LSB 0x9 265*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvEBPErrMask_RMASK 0x1 266*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_LSB 0x8 267*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1 268*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_LSB 0x7 269*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1 270*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvShortPktLenErrMask_LSB 0x6 271*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvShortPktLenErrMask_RMASK 0x1 272*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvLongPktLenErrMask_LSB 0x5 273*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvLongPktLenErrMask_RMASK 0x1 274*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvMaxPktLenErrMask_LSB 0x4 275*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1 276*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvMinPktLenErrMask_LSB 0x3 277*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvMinPktLenErrMask_RMASK 0x1 278*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvICRCErrMask_LSB 0x2 279*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvICRCErrMask_RMASK 0x1 280*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvVCRCErrMask_LSB 0x1 281*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvVCRCErrMask_RMASK 0x1 282*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvFormatErrMask_LSB 0x0 283*4882a593Smuzhiyun #define QIB_6120_ErrMask_RcvFormatErrMask_RMASK 0x1 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun #define QIB_6120_ErrStatus_OFFS 0x88 286*4882a593Smuzhiyun #define QIB_6120_ErrStatus_Reserved_LSB 0x34 287*4882a593Smuzhiyun #define QIB_6120_ErrStatus_Reserved_RMASK 0xFFF 288*4882a593Smuzhiyun #define QIB_6120_ErrStatus_HardwareErr_LSB 0x33 289*4882a593Smuzhiyun #define QIB_6120_ErrStatus_HardwareErr_RMASK 0x1 290*4882a593Smuzhiyun #define QIB_6120_ErrStatus_ResetNegated_LSB 0x32 291*4882a593Smuzhiyun #define QIB_6120_ErrStatus_ResetNegated_RMASK 0x1 292*4882a593Smuzhiyun #define QIB_6120_ErrStatus_InvalidAddrErr_LSB 0x31 293*4882a593Smuzhiyun #define QIB_6120_ErrStatus_InvalidAddrErr_RMASK 0x1 294*4882a593Smuzhiyun #define QIB_6120_ErrStatus_IBStatusChanged_LSB 0x30 295*4882a593Smuzhiyun #define QIB_6120_ErrStatus_IBStatusChanged_RMASK 0x1 296*4882a593Smuzhiyun #define QIB_6120_ErrStatus_Reserved1_LSB 0x26 297*4882a593Smuzhiyun #define QIB_6120_ErrStatus_Reserved1_RMASK 0x3FF 298*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendUnsupportedVLErr_LSB 0x25 299*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendUnsupportedVLErr_RMASK 0x1 300*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_LSB 0x24 301*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1 302*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendPioArmLaunchErr_LSB 0x23 303*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendPioArmLaunchErr_RMASK 0x1 304*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendDroppedDataPktErr_LSB 0x22 305*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendDroppedDataPktErr_RMASK 0x1 306*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendDroppedSmpPktErr_LSB 0x21 307*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1 308*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendPktLenErr_LSB 0x20 309*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendPktLenErr_RMASK 0x1 310*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendUnderRunErr_LSB 0x1F 311*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendUnderRunErr_RMASK 0x1 312*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendMaxPktLenErr_LSB 0x1E 313*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendMaxPktLenErr_RMASK 0x1 314*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendMinPktLenErr_LSB 0x1D 315*4882a593Smuzhiyun #define QIB_6120_ErrStatus_SendMinPktLenErr_RMASK 0x1 316*4882a593Smuzhiyun #define QIB_6120_ErrStatus_Reserved2_LSB 0x12 317*4882a593Smuzhiyun #define QIB_6120_ErrStatus_Reserved2_RMASK 0x7FF 318*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvIBLostLinkErr_LSB 0x11 319*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvIBLostLinkErr_RMASK 0x1 320*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvHdrErr_LSB 0x10 321*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvHdrErr_RMASK 0x1 322*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvHdrLenErr_LSB 0xF 323*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvHdrLenErr_RMASK 0x1 324*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvBadTidErr_LSB 0xE 325*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvBadTidErr_RMASK 0x1 326*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvHdrFullErr_LSB 0xD 327*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvHdrFullErr_RMASK 0x1 328*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvEgrFullErr_LSB 0xC 329*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvEgrFullErr_RMASK 0x1 330*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvBadVersionErr_LSB 0xB 331*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvBadVersionErr_RMASK 0x1 332*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvIBFlowErr_LSB 0xA 333*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvIBFlowErr_RMASK 0x1 334*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvEBPErr_LSB 0x9 335*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvEBPErr_RMASK 0x1 336*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvUnsupportedVLErr_LSB 0x8 337*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1 338*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvUnexpectedCharErr_LSB 0x7 339*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1 340*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvShortPktLenErr_LSB 0x6 341*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvShortPktLenErr_RMASK 0x1 342*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvLongPktLenErr_LSB 0x5 343*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvLongPktLenErr_RMASK 0x1 344*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvMaxPktLenErr_LSB 0x4 345*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvMaxPktLenErr_RMASK 0x1 346*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvMinPktLenErr_LSB 0x3 347*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvMinPktLenErr_RMASK 0x1 348*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvICRCErr_LSB 0x2 349*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvICRCErr_RMASK 0x1 350*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvVCRCErr_LSB 0x1 351*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvVCRCErr_RMASK 0x1 352*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvFormatErr_LSB 0x0 353*4882a593Smuzhiyun #define QIB_6120_ErrStatus_RcvFormatErr_RMASK 0x1 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun #define QIB_6120_ErrClear_OFFS 0x90 356*4882a593Smuzhiyun #define QIB_6120_ErrClear_Reserved_LSB 0x34 357*4882a593Smuzhiyun #define QIB_6120_ErrClear_Reserved_RMASK 0xFFF 358*4882a593Smuzhiyun #define QIB_6120_ErrClear_HardwareErrClear_LSB 0x33 359*4882a593Smuzhiyun #define QIB_6120_ErrClear_HardwareErrClear_RMASK 0x1 360*4882a593Smuzhiyun #define QIB_6120_ErrClear_ResetNegatedClear_LSB 0x32 361*4882a593Smuzhiyun #define QIB_6120_ErrClear_ResetNegatedClear_RMASK 0x1 362*4882a593Smuzhiyun #define QIB_6120_ErrClear_InvalidAddrErrClear_LSB 0x31 363*4882a593Smuzhiyun #define QIB_6120_ErrClear_InvalidAddrErrClear_RMASK 0x1 364*4882a593Smuzhiyun #define QIB_6120_ErrClear_IBStatusChangedClear_LSB 0x30 365*4882a593Smuzhiyun #define QIB_6120_ErrClear_IBStatusChangedClear_RMASK 0x1 366*4882a593Smuzhiyun #define QIB_6120_ErrClear_Reserved1_LSB 0x26 367*4882a593Smuzhiyun #define QIB_6120_ErrClear_Reserved1_RMASK 0x3FF 368*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendUnsupportedVLErrClear_LSB 0x25 369*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1 370*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_LSB 0x24 371*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1 372*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendPioArmLaunchErrClear_LSB 0x23 373*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1 374*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendDroppedDataPktErrClear_LSB 0x22 375*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1 376*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_LSB 0x21 377*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1 378*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendPktLenErrClear_LSB 0x20 379*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendPktLenErrClear_RMASK 0x1 380*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendUnderRunErrClear_LSB 0x1F 381*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendUnderRunErrClear_RMASK 0x1 382*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendMaxPktLenErrClear_LSB 0x1E 383*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendMaxPktLenErrClear_RMASK 0x1 384*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendMinPktLenErrClear_LSB 0x1D 385*4882a593Smuzhiyun #define QIB_6120_ErrClear_SendMinPktLenErrClear_RMASK 0x1 386*4882a593Smuzhiyun #define QIB_6120_ErrClear_Reserved2_LSB 0x12 387*4882a593Smuzhiyun #define QIB_6120_ErrClear_Reserved2_RMASK 0x7FF 388*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvIBLostLinkErrClear_LSB 0x11 389*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1 390*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvHdrErrClear_LSB 0x10 391*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvHdrErrClear_RMASK 0x1 392*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvHdrLenErrClear_LSB 0xF 393*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvHdrLenErrClear_RMASK 0x1 394*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvBadTidErrClear_LSB 0xE 395*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvBadTidErrClear_RMASK 0x1 396*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvHdrFullErrClear_LSB 0xD 397*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvHdrFullErrClear_RMASK 0x1 398*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvEgrFullErrClear_LSB 0xC 399*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvEgrFullErrClear_RMASK 0x1 400*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvBadVersionErrClear_LSB 0xB 401*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvBadVersionErrClear_RMASK 0x1 402*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvIBFlowErrClear_LSB 0xA 403*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvIBFlowErrClear_RMASK 0x1 404*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvEBPErrClear_LSB 0x9 405*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvEBPErrClear_RMASK 0x1 406*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_LSB 0x8 407*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1 408*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_LSB 0x7 409*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1 410*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvShortPktLenErrClear_LSB 0x6 411*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvShortPktLenErrClear_RMASK 0x1 412*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvLongPktLenErrClear_LSB 0x5 413*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvLongPktLenErrClear_RMASK 0x1 414*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvMaxPktLenErrClear_LSB 0x4 415*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1 416*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvMinPktLenErrClear_LSB 0x3 417*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvMinPktLenErrClear_RMASK 0x1 418*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvICRCErrClear_LSB 0x2 419*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvICRCErrClear_RMASK 0x1 420*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvVCRCErrClear_LSB 0x1 421*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvVCRCErrClear_RMASK 0x1 422*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvFormatErrClear_LSB 0x0 423*4882a593Smuzhiyun #define QIB_6120_ErrClear_RcvFormatErrClear_RMASK 0x1 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun #define QIB_6120_HwErrMask_OFFS 0x98 426*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_LSB 0x3F 427*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1 428*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_LSB 0x3E 429*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1 430*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved_LSB 0x3D 431*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved_RMASK 0x1 432*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_LSB 0x3C 433*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1 434*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_LSB 0x3B 435*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1 436*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_LSB 0x3A 437*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1 438*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved1_LSB 0x39 439*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved1_RMASK 0x1 440*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBPLLrfSlipMask_LSB 0x38 441*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBPLLrfSlipMask_RMASK 0x1 442*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBPLLfbSlipMask_LSB 0x37 443*4882a593Smuzhiyun #define QIB_6120_HwErrMask_IBPLLfbSlipMask_RMASK 0x1 444*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PowerOnBISTFailedMask_LSB 0x36 445*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1 446*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved2_LSB 0x33 447*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved2_RMASK 0x7 448*4882a593Smuzhiyun #define QIB_6120_HwErrMask_RXEMemParityErrMask_LSB 0x2C 449*4882a593Smuzhiyun #define QIB_6120_HwErrMask_RXEMemParityErrMask_RMASK 0x7F 450*4882a593Smuzhiyun #define QIB_6120_HwErrMask_TXEMemParityErrMask_LSB 0x28 451*4882a593Smuzhiyun #define QIB_6120_HwErrMask_TXEMemParityErrMask_RMASK 0xF 452*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved3_LSB 0x22 453*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved3_RMASK 0x3F 454*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIeBusParityErrMask_LSB 0x1F 455*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIeBusParityErrMask_RMASK 0x7 456*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PcieCplTimeoutMask_LSB 0x1E 457*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PcieCplTimeoutMask_RMASK 0x1 458*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PoisonedTLPMask_LSB 0x1D 459*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PoisonedTLPMask_RMASK 0x1 460*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved4_LSB 0x6 461*4882a593Smuzhiyun #define QIB_6120_HwErrMask_Reserved4_RMASK 0x7FFFFF 462*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIeMemParityErrMask_LSB 0x0 463*4882a593Smuzhiyun #define QIB_6120_HwErrMask_PCIeMemParityErrMask_RMASK 0x3F 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_OFFS 0xA0 466*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_LSB 0x3F 467*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1 468*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_LSB 0x3E 469*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1 470*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved_LSB 0x3D 471*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved_RMASK 0x1 472*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_LSB 0x3C 473*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1 474*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_LSB 0x3B 475*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1 476*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_LSB 0x3A 477*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1 478*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved1_LSB 0x39 479*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved1_RMASK 0x1 480*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBPLLrfSlip_LSB 0x38 481*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBPLLrfSlip_RMASK 0x1 482*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBPLLfbSlip_LSB 0x37 483*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_IBPLLfbSlip_RMASK 0x1 484*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PowerOnBISTFailed_LSB 0x36 485*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PowerOnBISTFailed_RMASK 0x1 486*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved2_LSB 0x33 487*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved2_RMASK 0x7 488*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_RXEMemParity_LSB 0x2C 489*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_RXEMemParity_RMASK 0x7F 490*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_TXEMemParity_LSB 0x28 491*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_TXEMemParity_RMASK 0xF 492*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved3_LSB 0x22 493*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved3_RMASK 0x3F 494*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIeBusParity_LSB 0x1F 495*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIeBusParity_RMASK 0x7 496*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PcieCplTimeout_LSB 0x1E 497*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PcieCplTimeout_RMASK 0x1 498*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PoisenedTLP_LSB 0x1D 499*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PoisenedTLP_RMASK 0x1 500*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved4_LSB 0x6 501*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_Reserved4_RMASK 0x7FFFFF 502*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIeMemParity_LSB 0x0 503*4882a593Smuzhiyun #define QIB_6120_HwErrStatus_PCIeMemParity_RMASK 0x3F 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun #define QIB_6120_HwErrClear_OFFS 0xA8 506*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_LSB 0x3F 507*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1 508*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_LSB 0x3E 509*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1 510*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved_LSB 0x3D 511*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved_RMASK 0x1 512*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_LSB 0x3C 513*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1 514*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_LSB 0x3B 515*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1 516*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_LSB 0x3A 517*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1 518*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved1_LSB 0x39 519*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved1_RMASK 0x1 520*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBPLLrfSlipClear_LSB 0x38 521*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBPLLrfSlipClear_RMASK 0x1 522*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBPLLfbSlipClear_LSB 0x37 523*4882a593Smuzhiyun #define QIB_6120_HwErrClear_IBPLLfbSlipClear_RMASK 0x1 524*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PowerOnBISTFailedClear_LSB 0x36 525*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1 526*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved2_LSB 0x33 527*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved2_RMASK 0x7 528*4882a593Smuzhiyun #define QIB_6120_HwErrClear_RXEMemParityClear_LSB 0x2C 529*4882a593Smuzhiyun #define QIB_6120_HwErrClear_RXEMemParityClear_RMASK 0x7F 530*4882a593Smuzhiyun #define QIB_6120_HwErrClear_TXEMemParityClear_LSB 0x28 531*4882a593Smuzhiyun #define QIB_6120_HwErrClear_TXEMemParityClear_RMASK 0xF 532*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved3_LSB 0x22 533*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved3_RMASK 0x3F 534*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIeBusParityClr_LSB 0x1F 535*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIeBusParityClr_RMASK 0x7 536*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PcieCplTimeoutClear_LSB 0x1E 537*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PcieCplTimeoutClear_RMASK 0x1 538*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PoisonedTLPClear_LSB 0x1D 539*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PoisonedTLPClear_RMASK 0x1 540*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved4_LSB 0x6 541*4882a593Smuzhiyun #define QIB_6120_HwErrClear_Reserved4_RMASK 0x7FFFFF 542*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIeMemParityClr_LSB 0x0 543*4882a593Smuzhiyun #define QIB_6120_HwErrClear_PCIeMemParityClr_RMASK 0x3F 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_OFFS 0xB0 546*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_LSB 0x3F 547*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1 548*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_LSB 0x3E 549*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1 550*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_CounterWrEnable_LSB 0x3D 551*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_CounterWrEnable_RMASK 0x1 552*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_CounterDisable_LSB 0x3C 553*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_CounterDisable_RMASK 0x1 554*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_Reserved_LSB 0x33 555*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_Reserved_RMASK 0x1FF 556*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceRxMemParityErr_LSB 0x2C 557*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceRxMemParityErr_RMASK 0x7F 558*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceTxMemparityErr_LSB 0x28 559*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_ForceTxMemparityErr_RMASK 0xF 560*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_Reserved1_LSB 0x23 561*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_Reserved1_RMASK 0x1F 562*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F 563*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF 564*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_Reserved2_LSB 0x6 565*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_Reserved2_RMASK 0x1FFFFFF 566*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_forcePCIeMemParity_LSB 0x0 567*4882a593Smuzhiyun #define QIB_6120_HwDiagCtrl_forcePCIeMemParity_RMASK 0x3F 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun #define QIB_6120_IBCStatus_OFFS 0xC0 570*4882a593Smuzhiyun #define QIB_6120_IBCStatus_TxCreditOk_LSB 0x1F 571*4882a593Smuzhiyun #define QIB_6120_IBCStatus_TxCreditOk_RMASK 0x1 572*4882a593Smuzhiyun #define QIB_6120_IBCStatus_TxReady_LSB 0x1E 573*4882a593Smuzhiyun #define QIB_6120_IBCStatus_TxReady_RMASK 0x1 574*4882a593Smuzhiyun #define QIB_6120_IBCStatus_Reserved_LSB 0x7 575*4882a593Smuzhiyun #define QIB_6120_IBCStatus_Reserved_RMASK 0x7FFFFF 576*4882a593Smuzhiyun #define QIB_6120_IBCStatus_LinkState_LSB 0x4 577*4882a593Smuzhiyun #define QIB_6120_IBCStatus_LinkState_RMASK 0x7 578*4882a593Smuzhiyun #define QIB_6120_IBCStatus_LinkTrainingState_LSB 0x0 579*4882a593Smuzhiyun #define QIB_6120_IBCStatus_LinkTrainingState_RMASK 0xF 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_OFFS 0xC8 582*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_Loopback_LSB 0x3F 583*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_Loopback_RMASK 0x1 584*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_LinkDownDefaultState_LSB 0x3E 585*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_LinkDownDefaultState_RMASK 0x1 586*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_Reserved_LSB 0x2B 587*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_Reserved_RMASK 0x7FFFF 588*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_CreditScale_LSB 0x28 589*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_CreditScale_RMASK 0x7 590*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_OverrunThreshold_LSB 0x24 591*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_OverrunThreshold_RMASK 0xF 592*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_PhyerrThreshold_LSB 0x20 593*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_PhyerrThreshold_RMASK 0xF 594*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_Reserved1_LSB 0x1F 595*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_Reserved1_RMASK 0x1 596*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_MaxPktLen_LSB 0x14 597*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_MaxPktLen_RMASK 0x7FF 598*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_LinkCmd_LSB 0x12 599*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_LinkCmd_RMASK 0x3 600*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_LinkInitCmd_LSB 0x10 601*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_LinkInitCmd_RMASK 0x3 602*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_FlowCtrlWaterMark_LSB 0x8 603*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_FlowCtrlWaterMark_RMASK 0xFF 604*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_FlowCtrlPeriod_LSB 0x0 605*4882a593Smuzhiyun #define QIB_6120_IBCCtrl_FlowCtrlPeriod_RMASK 0xFF 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun #define QIB_6120_EXTStatus_OFFS 0xD0 608*4882a593Smuzhiyun #define QIB_6120_EXTStatus_GPIOIn_LSB 0x30 609*4882a593Smuzhiyun #define QIB_6120_EXTStatus_GPIOIn_RMASK 0xFFFF 610*4882a593Smuzhiyun #define QIB_6120_EXTStatus_Reserved_LSB 0x20 611*4882a593Smuzhiyun #define QIB_6120_EXTStatus_Reserved_RMASK 0xFFFF 612*4882a593Smuzhiyun #define QIB_6120_EXTStatus_Reserved1_LSB 0x10 613*4882a593Smuzhiyun #define QIB_6120_EXTStatus_Reserved1_RMASK 0xFFFF 614*4882a593Smuzhiyun #define QIB_6120_EXTStatus_MemBISTFoundErr_LSB 0xF 615*4882a593Smuzhiyun #define QIB_6120_EXTStatus_MemBISTFoundErr_RMASK 0x1 616*4882a593Smuzhiyun #define QIB_6120_EXTStatus_MemBISTEndTest_LSB 0xE 617*4882a593Smuzhiyun #define QIB_6120_EXTStatus_MemBISTEndTest_RMASK 0x1 618*4882a593Smuzhiyun #define QIB_6120_EXTStatus_Reserved2_LSB 0x0 619*4882a593Smuzhiyun #define QIB_6120_EXTStatus_Reserved2_RMASK 0x3FFF 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_OFFS 0xD8 622*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_GPIOOe_LSB 0x30 623*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_GPIOOe_RMASK 0xFFFF 624*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_GPIOInvert_LSB 0x20 625*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_GPIOInvert_RMASK 0xFFFF 626*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_Reserved_LSB 0x4 627*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_Reserved_RMASK 0xFFFFFFF 628*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDPriPortGreenOn_LSB 0x3 629*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1 630*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDPriPortYellowOn_LSB 0x2 631*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1 632*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDGblOkGreenOn_LSB 0x1 633*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1 634*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDGblErrRedOff_LSB 0x0 635*4882a593Smuzhiyun #define QIB_6120_EXTCtrl_LEDGblErrRedOff_RMASK 0x1 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun #define QIB_6120_GPIOOut_OFFS 0xE0 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun #define QIB_6120_GPIOMask_OFFS 0xE8 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun #define QIB_6120_GPIOStatus_OFFS 0xF0 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun #define QIB_6120_GPIOClear_OFFS 0xF8 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_OFFS 0x100 646*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_TailUpd_LSB 0x1F 647*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_TailUpd_RMASK 0x1 648*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_LSB 0x1E 649*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1 650*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_Reserved_LSB 0x15 651*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_Reserved_RMASK 0x1FF 652*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_IntrAvail_LSB 0x10 653*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_IntrAvail_RMASK 0x1F 654*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_Reserved1_LSB 0x9 655*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_Reserved1_RMASK 0x7F 656*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_Reserved2_LSB 0x5 657*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_Reserved2_RMASK 0xF 658*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_PortEnable_LSB 0x0 659*4882a593Smuzhiyun #define QIB_6120_RcvCtrl_PortEnable_RMASK 0x1F 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_OFFS 0x108 662*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_BTHQP_Mask_LSB 0x1E 663*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_BTHQP_Mask_RMASK 0x3 664*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_Reserved_LSB 0x18 665*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_Reserved_RMASK 0x3F 666*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_RcvBTHQP_LSB 0x0 667*4882a593Smuzhiyun #define QIB_6120_RcvBTHQP_RcvBTHQP_RMASK 0xFFFFFF 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun #define QIB_6120_RcvHdrSize_OFFS 0x110 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun #define QIB_6120_RcvHdrCnt_OFFS 0x118 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun #define QIB_6120_RcvHdrEntSize_OFFS 0x120 674*4882a593Smuzhiyun 675*4882a593Smuzhiyun #define QIB_6120_RcvTIDBase_OFFS 0x128 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun #define QIB_6120_RcvTIDCnt_OFFS 0x130 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun #define QIB_6120_RcvEgrBase_OFFS 0x138 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun #define QIB_6120_RcvEgrCnt_OFFS 0x140 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun #define QIB_6120_RcvBufBase_OFFS 0x148 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun #define QIB_6120_RcvBufSize_OFFS 0x150 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun #define QIB_6120_RxIntMemBase_OFFS 0x158 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun #define QIB_6120_RxIntMemSize_OFFS 0x160 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun #define QIB_6120_RcvPartitionKey_OFFS 0x168 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun #define QIB_6120_RcvPktLEDCnt_OFFS 0x178 694*4882a593Smuzhiyun #define QIB_6120_RcvPktLEDCnt_ONperiod_LSB 0x20 695*4882a593Smuzhiyun #define QIB_6120_RcvPktLEDCnt_ONperiod_RMASK 0xFFFFFFFF 696*4882a593Smuzhiyun #define QIB_6120_RcvPktLEDCnt_OFFperiod_LSB 0x0 697*4882a593Smuzhiyun #define QIB_6120_RcvPktLEDCnt_OFFperiod_RMASK 0xFFFFFFFF 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun #define QIB_6120_SendCtrl_OFFS 0x1C0 700*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Disarm_LSB 0x1F 701*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Disarm_RMASK 0x1 702*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Reserved_LSB 0x17 703*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Reserved_RMASK 0xFF 704*4882a593Smuzhiyun #define QIB_6120_SendCtrl_DisarmPIOBuf_LSB 0x10 705*4882a593Smuzhiyun #define QIB_6120_SendCtrl_DisarmPIOBuf_RMASK 0x7F 706*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Reserved1_LSB 0x4 707*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Reserved1_RMASK 0xFFF 708*4882a593Smuzhiyun #define QIB_6120_SendCtrl_PIOEnable_LSB 0x3 709*4882a593Smuzhiyun #define QIB_6120_SendCtrl_PIOEnable_RMASK 0x1 710*4882a593Smuzhiyun #define QIB_6120_SendCtrl_PIOBufAvailUpd_LSB 0x2 711*4882a593Smuzhiyun #define QIB_6120_SendCtrl_PIOBufAvailUpd_RMASK 0x1 712*4882a593Smuzhiyun #define QIB_6120_SendCtrl_PIOIntBufAvail_LSB 0x1 713*4882a593Smuzhiyun #define QIB_6120_SendCtrl_PIOIntBufAvail_RMASK 0x1 714*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Abort_LSB 0x0 715*4882a593Smuzhiyun #define QIB_6120_SendCtrl_Abort_RMASK 0x1 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_OFFS 0x1C8 718*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_Reserved_LSB 0x35 719*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_Reserved_RMASK 0x7FF 720*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_BaseAddr_LargePIO_LSB 0x20 721*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF 722*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_Reserved1_LSB 0x15 723*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_Reserved1_RMASK 0x7FF 724*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_BaseAddr_SmallPIO_LSB 0x0 725*4882a593Smuzhiyun #define QIB_6120_SendPIOBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_OFFS 0x1D0 728*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Reserved_LSB 0x2D 729*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Reserved_RMASK 0xFFFFF 730*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Size_LargePIO_LSB 0x20 731*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Size_LargePIO_RMASK 0x1FFF 732*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Reserved1_LSB 0xC 733*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Reserved1_RMASK 0xFFFFF 734*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Size_SmallPIO_LSB 0x0 735*4882a593Smuzhiyun #define QIB_6120_SendPIOSize_Size_SmallPIO_RMASK 0xFFF 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_OFFS 0x1D8 738*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Reserved_LSB 0x24 739*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Reserved_RMASK 0xFFFFFFF 740*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Num_LargePIO_LSB 0x20 741*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Num_LargePIO_RMASK 0xF 742*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Reserved1_LSB 0x9 743*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Reserved1_RMASK 0x7FFFFF 744*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Num_SmallPIO_LSB 0x0 745*4882a593Smuzhiyun #define QIB_6120_SendPIOBufCnt_Num_SmallPIO_RMASK 0x1FF 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun #define QIB_6120_SendPIOAvailAddr_OFFS 0x1E0 748*4882a593Smuzhiyun #define QIB_6120_SendPIOAvailAddr_SendPIOAvailAddr_LSB 0x6 749*4882a593Smuzhiyun #define QIB_6120_SendPIOAvailAddr_SendPIOAvailAddr_RMASK 0x3FFFFFFFF 750*4882a593Smuzhiyun #define QIB_6120_SendPIOAvailAddr_Reserved_LSB 0x0 751*4882a593Smuzhiyun #define QIB_6120_SendPIOAvailAddr_Reserved_RMASK 0x3F 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun #define QIB_6120_SendBufErr0_OFFS 0x240 754*4882a593Smuzhiyun #define QIB_6120_SendBufErr0_SendBufErrPIO_63_0_LSB 0x0 755*4882a593Smuzhiyun #define QIB_6120_SendBufErr0_SendBufErrPIO_63_0_RMASK 0x0 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun #define QIB_6120_RcvHdrAddr0_OFFS 0x280 758*4882a593Smuzhiyun #define QIB_6120_RcvHdrAddr0_RcvHdrAddr0_LSB 0x2 759*4882a593Smuzhiyun #define QIB_6120_RcvHdrAddr0_RcvHdrAddr0_RMASK 0x3FFFFFFFFF 760*4882a593Smuzhiyun #define QIB_6120_RcvHdrAddr0_Reserved_LSB 0x0 761*4882a593Smuzhiyun #define QIB_6120_RcvHdrAddr0_Reserved_RMASK 0x3 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun #define QIB_6120_RcvHdrTailAddr0_OFFS 0x300 764*4882a593Smuzhiyun #define QIB_6120_RcvHdrTailAddr0_RcvHdrTailAddr0_LSB 0x2 765*4882a593Smuzhiyun #define QIB_6120_RcvHdrTailAddr0_RcvHdrTailAddr0_RMASK 0x3FFFFFFFFF 766*4882a593Smuzhiyun #define QIB_6120_RcvHdrTailAddr0_Reserved_LSB 0x0 767*4882a593Smuzhiyun #define QIB_6120_RcvHdrTailAddr0_Reserved_RMASK 0x3 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_OFFS 0x3C0 770*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_LSB 0x3F 771*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_RMASK 0x1 772*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_Reserved_LSB 0x38 773*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_Reserved_RMASK 0x7F 774*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxEqCtl_LSB 0x36 775*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxEqCtl_RMASK 0x3 776*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TxTermAdj_LSB 0x34 777*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TxTermAdj_RMASK 0x3 778*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxTermAdj_LSB 0x32 779*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxTermAdj_RMASK 0x3 780*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TermAdj1_LSB 0x31 781*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TermAdj1_RMASK 0x1 782*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TermAdj0_LSB 0x30 783*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TermAdj0_RMASK 0x1 784*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKA_LSB 0x2F 785*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKA_RMASK 0x1 786*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKB_LSB 0x2E 787*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKB_RMASK 0x1 788*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKC_LSB 0x2D 789*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKC_RMASK 0x1 790*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKD_LSB 0x2C 791*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_LPBKD_RMASK 0x1 792*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_PW_LSB 0x2B 793*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_PW_RMASK 0x1 794*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RefSel_LSB 0x29 795*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RefSel_RMASK 0x3 796*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ParReset_LSB 0x28 797*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ParReset_RMASK 0x1 798*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ParLPBK_LSB 0x27 799*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ParLPBK_RMASK 0x1 800*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_OffsetEn_LSB 0x26 801*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_OffsetEn_RMASK 0x1 802*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_Offset_LSB 0x1E 803*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_Offset_RMASK 0xFF 804*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L2PwrDn_LSB 0x1D 805*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L2PwrDn_RMASK 0x1 806*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetPLL_LSB 0x1C 807*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetPLL_RMASK 0x1 808*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxTermEnX_LSB 0x18 809*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxTermEnX_RMASK 0xF 810*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_BeaconTxEnX_LSB 0x14 811*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_BeaconTxEnX_RMASK 0xF 812*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxDetEnX_LSB 0x10 813*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxDetEnX_RMASK 0xF 814*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TxIdeEnX_LSB 0xC 815*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_TxIdeEnX_RMASK 0xF 816*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxIdleEnX_LSB 0x8 817*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_RxIdleEnX_RMASK 0xF 818*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnA_LSB 0x7 819*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnA_RMASK 0x1 820*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnB_LSB 0x6 821*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnB_RMASK 0x1 822*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnC_LSB 0x5 823*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnC_RMASK 0x1 824*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnD_LSB 0x4 825*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_L1PwrDnD_RMASK 0x1 826*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetA_LSB 0x3 827*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetA_RMASK 0x1 828*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetB_LSB 0x2 829*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetB_RMASK 0x1 830*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetC_LSB 0x1 831*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetC_RMASK 0x1 832*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetD_LSB 0x0 833*4882a593Smuzhiyun #define QIB_6120_SerdesCfg0_ResetD_RMASK 0x1 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun #define QIB_6120_SerdesStat_OFFS 0x3D0 836*4882a593Smuzhiyun #define QIB_6120_SerdesStat_Reserved_LSB 0xC 837*4882a593Smuzhiyun #define QIB_6120_SerdesStat_Reserved_RMASK 0xFFFFFFFFFFFFF 838*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetA_LSB 0xB 839*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetA_RMASK 0x1 840*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetB_LSB 0xA 841*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetB_RMASK 0x1 842*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetC_LSB 0x9 843*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetC_RMASK 0x1 844*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetD_LSB 0x8 845*4882a593Smuzhiyun #define QIB_6120_SerdesStat_BeaconDetD_RMASK 0x1 846*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetA_LSB 0x7 847*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetA_RMASK 0x1 848*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetB_LSB 0x6 849*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetB_RMASK 0x1 850*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetC_LSB 0x5 851*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetC_RMASK 0x1 852*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetD_LSB 0x4 853*4882a593Smuzhiyun #define QIB_6120_SerdesStat_RxDetD_RMASK 0x1 854*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetA_LSB 0x3 855*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetA_RMASK 0x1 856*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetB_LSB 0x2 857*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetB_RMASK 0x1 858*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetC_LSB 0x1 859*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetC_RMASK 0x1 860*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetD_LSB 0x0 861*4882a593Smuzhiyun #define QIB_6120_SerdesStat_TxIdleDetD_RMASK 0x1 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_OFFS 0x3D8 864*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_LSB 0x3F 865*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_RMASK 0x1 866*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_Reserved_LSB 0x17 867*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_Reserved_RMASK 0xFFFFFFFFFF 868*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_polarity_inv_LSB 0x13 869*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_polarity_inv_RMASK 0xF 870*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_link_sync_mask_LSB 0x9 871*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_link_sync_mask_RMASK 0x3FF 872*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_port_addr_LSB 0x4 873*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_port_addr_RMASK 0x1F 874*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_mdd_30_LSB 0x3 875*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_mdd_30_RMASK 0x1 876*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_xcv_resetn_LSB 0x2 877*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_xcv_resetn_RMASK 0x1 878*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_Reserved1_LSB 0x1 879*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_Reserved1_RMASK 0x1 880*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_tx_rx_resetn_LSB 0x0 881*4882a593Smuzhiyun #define QIB_6120_XGXSCfg_tx_rx_resetn_RMASK 0x1 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun #define QIB_6120_LBIntCnt_OFFS 0x12000 884*4882a593Smuzhiyun 885*4882a593Smuzhiyun #define QIB_6120_LBFlowStallCnt_OFFS 0x12008 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun #define QIB_6120_TxUnsupVLErrCnt_OFFS 0x12018 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun #define QIB_6120_TxDataPktCnt_OFFS 0x12020 890*4882a593Smuzhiyun 891*4882a593Smuzhiyun #define QIB_6120_TxFlowPktCnt_OFFS 0x12028 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun #define QIB_6120_TxDwordCnt_OFFS 0x12030 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun #define QIB_6120_TxLenErrCnt_OFFS 0x12038 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun #define QIB_6120_TxMaxMinLenErrCnt_OFFS 0x12040 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun #define QIB_6120_TxUnderrunCnt_OFFS 0x12048 900*4882a593Smuzhiyun 901*4882a593Smuzhiyun #define QIB_6120_TxFlowStallCnt_OFFS 0x12050 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun #define QIB_6120_TxDroppedPktCnt_OFFS 0x12058 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun #define QIB_6120_RxDroppedPktCnt_OFFS 0x12060 906*4882a593Smuzhiyun 907*4882a593Smuzhiyun #define QIB_6120_RxDataPktCnt_OFFS 0x12068 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun #define QIB_6120_RxFlowPktCnt_OFFS 0x12070 910*4882a593Smuzhiyun 911*4882a593Smuzhiyun #define QIB_6120_RxDwordCnt_OFFS 0x12078 912*4882a593Smuzhiyun 913*4882a593Smuzhiyun #define QIB_6120_RxLenErrCnt_OFFS 0x12080 914*4882a593Smuzhiyun 915*4882a593Smuzhiyun #define QIB_6120_RxMaxMinLenErrCnt_OFFS 0x12088 916*4882a593Smuzhiyun 917*4882a593Smuzhiyun #define QIB_6120_RxICRCErrCnt_OFFS 0x12090 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun #define QIB_6120_RxVCRCErrCnt_OFFS 0x12098 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun #define QIB_6120_RxFlowCtrlErrCnt_OFFS 0x120A0 922*4882a593Smuzhiyun 923*4882a593Smuzhiyun #define QIB_6120_RxBadFormatCnt_OFFS 0x120A8 924*4882a593Smuzhiyun 925*4882a593Smuzhiyun #define QIB_6120_RxLinkProblemCnt_OFFS 0x120B0 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun #define QIB_6120_RxEBPCnt_OFFS 0x120B8 928*4882a593Smuzhiyun 929*4882a593Smuzhiyun #define QIB_6120_RxLPCRCErrCnt_OFFS 0x120C0 930*4882a593Smuzhiyun 931*4882a593Smuzhiyun #define QIB_6120_RxBufOvflCnt_OFFS 0x120C8 932*4882a593Smuzhiyun 933*4882a593Smuzhiyun #define QIB_6120_RxTIDFullErrCnt_OFFS 0x120D0 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun #define QIB_6120_RxTIDValidErrCnt_OFFS 0x120D8 936*4882a593Smuzhiyun 937*4882a593Smuzhiyun #define QIB_6120_RxPKeyMismatchCnt_OFFS 0x120E0 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun #define QIB_6120_RxP0HdrEgrOvflCnt_OFFS 0x120E8 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun #define QIB_6120_IBStatusChangeCnt_OFFS 0x12140 942*4882a593Smuzhiyun 943*4882a593Smuzhiyun #define QIB_6120_IBLinkErrRecoveryCnt_OFFS 0x12148 944*4882a593Smuzhiyun 945*4882a593Smuzhiyun #define QIB_6120_IBLinkDownedCnt_OFFS 0x12150 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun #define QIB_6120_IBSymbolErrCnt_OFFS 0x12158 948*4882a593Smuzhiyun 949*4882a593Smuzhiyun #define QIB_6120_PcieRetryBufDiagQwordCnt_OFFS 0x12170 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun #define QIB_6120_RcvEgrArray0_OFFS 0x14000 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun #define QIB_6120_RcvTIDArray0_OFFS 0x54000 954*4882a593Smuzhiyun 955*4882a593Smuzhiyun #define QIB_6120_PIOLaunchFIFO_OFFS 0x64000 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun #define QIB_6120_SendPIOpbcCache_OFFS 0x64800 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun #define QIB_6120_RcvBuf1_OFFS 0x72000 960*4882a593Smuzhiyun 961*4882a593Smuzhiyun #define QIB_6120_RcvBuf2_OFFS 0x75000 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun #define QIB_6120_RcvFlags_OFFS 0x77000 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun #define QIB_6120_RcvLookupBuf1_OFFS 0x79000 966*4882a593Smuzhiyun 967*4882a593Smuzhiyun #define QIB_6120_RcvDMABuf_OFFS 0x7B000 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun #define QIB_6120_MiscRXEIntMem_OFFS 0x7C000 970*4882a593Smuzhiyun 971*4882a593Smuzhiyun #define QIB_6120_PCIERcvBuf_OFFS 0x80000 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun #define QIB_6120_PCIERetryBuf_OFFS 0x82000 974*4882a593Smuzhiyun 975*4882a593Smuzhiyun #define QIB_6120_PCIERcvBufRdToWrAddr_OFFS 0x84000 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun #define QIB_6120_PIOBuf0_MA_OFFS 0x100000 978