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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Ddesignware-pcie.txt4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
[all …]
H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 Documentation/devicetree/bindings/pci/designware-pcie.txt.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: "pci-ep.yaml#"
23 const: socionext,uniphier-pro5-pcie-ep
29 reg-names:
31 - items:
[all …]
H A Dpci-keystone.txt6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
24 (required if the compatible is "ti,keystone-pcie")
25 msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
[all …]
H A Dti-pci.txt4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
15 - num-lanes as specified in ../designware-pcie.txt
[all …]
H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in designware-pcie.txt.
9 - power-domains: A phandle to the node that controls power to the respective
19 "include/dt-bindings/power/tegra194-powergate.h" file.
20 - reg: A list of physical base address and length pairs for each set of
21 controller registers. Must contain an entry for each entry in the reg-names
23 - reg-names: Must include the following entries:
25 "config": As per the definition in designware-pcie.txt
31 - interrupts: A list of interrupt outputs of the controller. Must contain an
32 entry for each entry in the interrupt-names property.
33 - interrupt-names: Must include the following entries:
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy-snps-pcie3.h>
8 #include "rk3588-vccio3-pinctrl.dtsi"
20 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
23 clock-names = "ref", "suspend", "bus";
24 #address-cells = <2>;
25 #size-cells = <2>;
33 power-domains = <&power RK3588_PD_USB>;
35 reset-names = "usb3-otg";
38 phy-names = "usb2-phy";
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/rk3568-power.h>
18 interrupt-parent = <&gic>;
[all …]
H A Drk3588s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3588-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3588-power.h>
11 #include <dt-bindings/gpio/gpio.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A D.OK3568-C.dtb.dts.tmp
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Drk3528.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3528-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3528-power.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/soc/rockchip-system-status.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/pci/controller/dwc/
H A Dpcie-designware-ep.c1 // SPDX-License-Identifier: GPL-2.0
11 #include "pcie-designware.h"
12 #include <linux/pci-epc.h>
13 #include <linux/pci-epf.h>
19 struct pci_epc *epc = ep->epc; in dw_pcie_ep_linkup()
27 struct pci_epc *epc = ep->epc; in dw_pcie_ep_init_notify()
38 list_for_each_entry(ep_func, &ep->func_list, list) { in dw_pcie_ep_get_func_from_ep()
39 if (ep_func->func_no == func_no) in dw_pcie_ep_get_func_from_ep()
50 if (ep->ops->func_conf_select) in dw_pcie_ep_func_select()
51 func_offset = ep->ops->func_conf_select(ep, func_no); in dw_pcie_ep_func_select()
[all …]
H A Dpcie-dw-ep-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
23 #include <uapi/linux/rk-pcie-ep.h>
25 #include "../rockchip-pcie-dma.h"
26 #include "pcie-designware.h"
27 #include "pcie-dw-dmatest.h"
36 #define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
149 .compatible = "rockchip,rk3568-pcie-std-ep",
152 .compatible = "rockchip,rk3588-pcie-std-ep",
[all …]
H A Dpcie-dw-rockchip.c1 // SPDX-License-Identifier: GPL-2.0
6 * http://www.rock-chips.com
8 * Author: Simon Xue <xxm@rock-chips.com>
39 #include <linux/rfkill-wlan.h>
43 #include <linux/pci-epf.h>
45 #include "pcie-designware.h"
47 #include "../rockchip-pcie-dma.h"
48 #include "pcie-dw-dmatest.h"
202 #define to_rk_pcie(x) dev_get_drvdata((x)->dev)
206 if ((uintptr_t)addr & (size - 1)) { in rk_pcie_read()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a72";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy-snps-pcie3.h>
8 #include "rk3588-vccio3-pinctrl.dtsi"
30 rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
31 compatible = "rockchip,rkcif-mipi-lvds";
37 rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf {
38 compatible = "rockchip,rkcif-sditf";
43 rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 {
44 compatible = "rockchip,rkcif-sditf";
49 rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 {
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/power/rk3568-power.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3568.h>
[all …]
H A Drk3528.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3528-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/power/rk3528-power.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/soc/rockchip-system-status.h>
[all …]
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/soc/rockchip-system-status.h>
14 #include <dt-bindings/suspend/rockchip-rk3562.h>
[all …]
H A Drk1808.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include <dt-bindings/clock/rk1808-cru.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/power/rk1808-power.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
11 #include <dt-bindings/soc/rockchip-system-status.h>
12 #include <dt-bindings/suspend/rockchip-rk1808.h>
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
H A Duniphier-pro5.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
[all …]
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]

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