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/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/
H A Dimmap_5445x.h76 u16 sbfsr; /* Serial Boot Facility Status Register */
78 u16 sbfcr; /* Serial Boot Facility Control Register */
90 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
93 u16 cir; /* Chip Identification Register (Read-only) */
95 u16 misccr; /* Miscellaneous Control Register */
96 u16 cdr; /* Clock Divider Register */
97 u16 uocsr; /* USB On-the-Go Controller Status Register */
102 u8 podr_fec0h; /* FEC0 High Port Output Data Register */
103 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
104 u8 podr_ssi; /* SSI Port Output Data Register */
[all …]
/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Des8396.h11 /* THE REGISTER DEFINITION FORMAT */
14 /* write 0x01 to Register 0x00 will reset all registers of codec.
15 * Register 0x00 must be cleared before normal
19 /* Clock Scheme Register definition */
20 /* Register 0x01 for MCLK source selection */
22 /* Register 0x02 for PLL power down/up, reset, divider and divider dither */
24 /* Register 0x03 for PLL low power mode and PLL power supply selection */
26 /* Register 0x04 for PLL N cofficient, must be in 5 to 13 range*/
28 /* Register 0x05-0x07 for PLL k cofficient*/
32 /* Register 0x08 for ADC,DAC CHARGE PUMP and CLASS D clock switch*/
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
39 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
[all …]
H A Dprocessor.h13 /* Machine State Register (MSR) Fields */
60 /* Floating Point Status and Control Register (FPSCR) Fields */
92 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
94 #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
96 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
97 #define SPRN_CTR 0x009 /* Count Register */
98 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
106 #define SPRN_DAR 0x013 /* Data Address Register */
107 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
108 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
[all …]
/OK3568_Linux_fs/kernel/include/video/
H A Ds1d13xxxfb.h20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
33 #define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/
H A Dpinctrl-at91.h12 #define PIO_PER 0x00 /* Enable Register */
13 #define PIO_PDR 0x04 /* Disable Register */
14 #define PIO_PSR 0x08 /* Status Register */
15 #define PIO_OER 0x10 /* Output Enable Register */
16 #define PIO_ODR 0x14 /* Output Disable Register */
17 #define PIO_OSR 0x18 /* Output Status Register */
21 #define PIO_SODR 0x30 /* Set Output Data Register */
22 #define PIO_CODR 0x34 /* Clear Output Data Register */
23 #define PIO_ODSR 0x38 /* Output Data Status Register */
24 #define PIO_PDSR 0x3c /* Pin Data Status Register */
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-sa1100/
H A Djornada720.c56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
62 {0x0010,0x01}, // Memory Clock Configuration Register
63 {0x0014,0x11}, // LCD Pixel Clock Configuration Register
64 {0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register
65 {0x001C,0x01}, // MediaPlug Clock Configuration Register
[all …]
/OK3568_Linux_fs/u-boot/include/linux/
H A Dimmap_qe.h41 u32 iadd; /* I-RAM Address Register */
42 u32 idata; /* I-RAM Data Register */
73 u32 cecr; /* QE command register */
74 u32 ceccr; /* QE controller configuration register */
75 u32 cecdr; /* QE command data register */
77 u16 ceter; /* QE timer event register */
79 u16 cetmr; /* QE timers mask register */
80 u32 cetscr; /* QE time-stamp timer control register */
81 u32 cetsr1; /* QE time-stamp register 1 */
82 u32 cetsr2; /* QE time-stamp register 2 */
[all …]
/OK3568_Linux_fs/kernel/include/linux/fsl/
H A Dguts.h3 * Freecale 85xx and 86xx Global Utilties register set
21 * you are expected to know whether a given register actually exists on your
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
32 * Control Register
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
39 * Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
[all …]
/OK3568_Linux_fs/kernel/include/soc/fsl/qe/
H A Dimmap_qe.h23 __be32 iadd; /* I-RAM Address Register */
24 __be32 idata; /* I-RAM Data Register */
26 __be32 iready; /* I-RAM Ready Register */
55 __be32 cecr; /* QE command register */
56 __be32 ceccr; /* QE controller configuration register */
57 __be32 cecdr; /* QE command data register */
59 __be16 ceter; /* QE timer event register */
61 __be16 cetmr; /* QE timers mask register */
62 __be32 cetscr; /* QE time-stamp timer control register */
63 __be32 cetsr1; /* QE time-stamp register 1 */
[all …]
/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_mc_static.h12 {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */
14 {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */
16 {0x00001404, 0x3630b800}, /*Dunit Control Low Register */
17 {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */
18 /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
19 {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */
22 {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */
24 {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */
27 {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */
28 {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt16 - leds : Contain the led nodes and initial register values in property
17 "led-control". Number of register depends of used IC, for MC13783 is 6,
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-pxa/
H A Dpxa27x-udc.h9 #define UDCCR __REG(0x40600000) /* UDC Control Register */
48 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
49 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
57 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
85 #define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
86 #define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
104 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
114 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
115 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
116 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
[all …]
/OK3568_Linux_fs/kernel/drivers/crypto/ux500/cryp/
H A Dcryp_irqp.h20 * 00h | CRYP_CR | Configuration register
22 * 04h | CRYP_SR | Status register
24 * 08h | CRYP_DIN | Data In register
26 * 0ch | CRYP_DOUT | Data out register
28 * 10h | CRYP_DMACR | DMA control register
41 * Refer data structure for other register map
46 * @cr - Configuration register
47 * @status - Status register
48 * @din - Data input register
49 * @din_size - Data input size register
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/da9052/
H A Dreg.h3 * Register declarations for DA9052 PMICs.
23 /* PARK REGISTER */
178 /* STATUS REGISTER A BITS */
188 /* STATUS REGISTER B BITS */
198 /* STATUS REGISTER C BITS */
208 /* STATUS REGISTER D BITS */
218 /* EVENT REGISTER A BITS */
228 /* EVENT REGISTER B BITS */
238 /* EVENT REGISTER C BITS */
248 /* EVENT REGISTER D BITS */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/sun/
H A Dsungem.h12 #define GREG_SEBSTATE 0x0000UL /* SEB State Register */
13 #define GREG_CFG 0x0004UL /* Configuration Register */
14 #define GREG_STAT 0x000CUL /* Status Register */
15 #define GREG_IMASK 0x0010UL /* Interrupt Mask Register */
16 #define GREG_IACK 0x0014UL /* Interrupt ACK Register */
18 #define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */
19 #define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */
20 #define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */
21 #define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */
22 #define GREG_SWRST 0x1010UL /* Software Reset Register */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun9i.h2 * Sun8i platform dram controller register and constant defines
17 u32 ccr; /* 0x04 controller configuration register */
42 u32 mstr; /* 0x00 master register */
43 u32 stat; /* 0x04 operating mode status register */
45 u32 mrctrl[2]; /* 0x10 mode register read/write control reg */
46 u32 mstat; /* 0x18 mode register read/write status reg */
48 u32 derateen; /* 0x20 temperature derate enable register */
49 u32 derateint; /* 0x24 temperature derate interval register */
51 u32 pwrctl; /* 0x30 low power control register */
52 u32 pwrtmg; /* 0x34 low power timing register */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h96 #define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */
102 #define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */
103 #define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */
104 #define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */
105 #define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/aic7xxx/
H A Daic79xx.reg2 * Aic79xx register and scratch ram definitions.
50 /* Register window Modes */
88 * is added to the register which is referenced in the driver.
89 * Unreferenced register with no dont_generate_debug_code will result
96 * as the source and destination of any register accesses in our
97 * register window.
99 register MODE_PTR {
114 register INTSTAT {
131 register SEQINTCODE {
211 register CLRINT {
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/atmel/
H A Datmel-isc-regs.h7 /* ISC Control Enable Register 0 */
10 /* ISC Control Disable Register 0 */
13 /* ISC Control Status Register 0 */
21 /* ISC Parallel Front End Configuration 0 Register */
43 /* ISC Parallel Front End Configuration 1 Register */
51 /* ISC Parallel Front End Configuration 2 Register */
59 /* ISC Clock Enable Register */
62 /* ISC Clock Disable Register */
65 /* ISC Clock Status Register */
71 /* ISC Clock Configuration Register */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Dclk.h18 u32 boot_map; /* Boot Map Control Register */
20 u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */
22 u32 start_er_int; /* Start Enable Register */
23 u32 start_rsr_int; /* Start Raw Status Register */
24 u32 start_sr_int; /* Start Status Register */
25 u32 start_apr_int; /* Start Activation Polarity Register */
27 u32 start_er_pin; /* Start Enable Register */
28 u32 start_rsr_pin; /* Start Raw Status Register */
29 u32 start_sr_pin; /* Start Status Register */
30 u32 start_apr_pin; /* Start Activation Polarity Register */
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_pio.h40 u32 per; /* 0x00 PIO Enable Register */
41 u32 pdr; /* 0x04 PIO Disable Register */
42 u32 psr; /* 0x08 PIO Status Register */
44 u32 oer; /* 0x10 Output Enable Register */
46 u32 osr; /* 0x18 Output Status Register */
48 u32 ifer; /* 0x20 Input Filter Enable Register */
49 u32 ifdr; /* 0x24 Input Filter Disable Register */
50 u32 ifsr; /* 0x28 Input Filter Status Register */
52 u32 sodr; /* 0x30 Set Output Data Register */
53 u32 codr; /* 0x34 Clear Output Data Register */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/
H A Dbcmpcispi.h2 * Broadcom PCI-SPI Host Controller Register Definitions
42 uint32 spih_ctrl; /* 0x00 SPI Control Register */
43 uint32 spih_stat; /* 0x04 SPI Status Register */
44 uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
45 uint32 spih_ext; /* 0x0C SPI Extension Register */
48 uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
49 uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
52 uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
53 uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
66 uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/
H A Dbcmpcispi.h2 * Broadcom PCI-SPI Host Controller Register Definitions
42 uint32 spih_ctrl; /* 0x00 SPI Control Register */
43 uint32 spih_stat; /* 0x04 SPI Status Register */
44 uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
45 uint32 spih_ext; /* 0x0C SPI Extension Register */
48 uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
49 uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
52 uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
53 uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
66 uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/
H A Dbcmpcispi.h3 * Broadcom PCI-SPI Host Controller Register Definitions
42 uint32 spih_ctrl; /* 0x00 SPI Control Register */
43 uint32 spih_stat; /* 0x04 SPI Status Register */
44 uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
45 uint32 spih_ext; /* 0x0C SPI Extension Register */
48 uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
49 uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
52 uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
53 uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
66 uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */
[all …]

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