1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ES8396.h -- ES8396 ALSA SoC Audio Codec 4 * 5 * Based on alc5632.h by Arnaud Patard 6 */ 7 8 #ifndef _ES8396_H 9 #define _ES8396_H 10 11 /* THE REGISTER DEFINITION FORMAT */ 12 /* ES8396_REGISTER NAME_REG_REGISTER ADDRESS */ 13 14 /* write 0x01 to Register 0x00 will reset all registers of codec. 15 * Register 0x00 must be cleared before normal 16 */ 17 #define ES8396_RESET_REG00 0x00 18 19 /* Clock Scheme Register definition */ 20 /* Register 0x01 for MCLK source selection */ 21 #define ES8396_CLK_SRC_SEL_REG01 0x01 22 /* Register 0x02 for PLL power down/up, reset, divider and divider dither */ 23 #define ES8396_PLL_CTRL_1_REG02 0x02 24 /* Register 0x03 for PLL low power mode and PLL power supply selection */ 25 #define ES8396_PLL_CTRL_2_REG03 0x03 26 /* Register 0x04 for PLL N cofficient, must be in 5 to 13 range*/ 27 #define ES8396_PLL_N_REG04 0x04 28 /* Register 0x05-0x07 for PLL k cofficient*/ 29 #define ES8396_PLL_K2_REG05 0x05 30 #define ES8396_PLL_K1_REG06 0x06 31 #define ES8396_PLL_K0_REG07 0x07 32 /* Register 0x08 for ADC,DAC CHARGE PUMP and CLASS D clock switch*/ 33 #define ES8396_CLK_CTRL_REG08 0x08 34 /* Register 0x09 for ADC MCLK divider*/ 35 #define ES8396_ADC_CLK_DIV_REG09 0x09 36 /* Register 0x0A for DAC MCLK divider*/ 37 #define ES8396_DAC_CLK_DIV_REG0A 0x0A 38 /* Register 0x0B for CHARGE PUMP CLOCK divider*/ 39 #define ES8396_CP_CLK_DIV_REG0B 0x0B 40 /* Register 0x0C for CLASS D Amplifier Clock divider*/ 41 #define ES8396_DAMP_CLK_DIV_REG0C 0x0C 42 /* Register 0x0D for DLL control and DAC MCLK SELECTION*/ 43 #define ES8396_DLL_CTRL_REG0D 0x0D 44 /* Register 0x0E for BCLK divider1 in I2S BUS Master mode*/ 45 #define ES8396_BCLK_DIV_M1_REG0E 0x0E 46 /* Register 0x0F for BCLK divider2 in I2S BUS Master mode*/ 47 #define ES8396_BCLK_DIV_M2_REG0F 0x0F 48 /* Register 0x10 for LRCK divider3 in I2S BUS Master mode*/ 49 #define ES8396_LRCK_DIV_M3_REG10 0x10 50 /* Register 0x11 for LRCK divider4 in I2S BUS Master mode*/ 51 #define ES8396_LRCK_DIV_M4_REG11 0x11 52 53 /* PAD MUX REGISTER DEFINITION */ 54 /* Register 0x12 for SDP1 Master or slave mode*/ 55 #define ES8396_SDP_1_MS_REG12 0x12 56 /* Register 0x13 for SDP2 Master or slave mode*/ 57 #define ES8396_SDP_2_MS_REG13 0x13 58 /* Register 0x14 for SDP1 Master or slave mode*/ 59 #define ES8396_SDP_3_MS_REG14 0x14 60 /* Register 0x15 for ADLRCK or GPIO control*/ 61 #define ES8396_ALRCK_GPIO_SEL_REG15 0x15 62 63 /* GPIO REGISTER DEFINITION */ 64 /* Register 0x16 for GPIO interrupt*/ 65 #define ES8396_GPIO_IRQ_REG16 0x16 66 /* Register 0x17 for GPIO STATUS*/ 67 #define ES8396_GPIO_STA_REG17 0x17 68 69 /* Digital Mixer Register Definition */ 70 /* Register 0x18 for Digital Mixer Source*/ 71 #define ES8396_DMIX_SRC_1_REG18 0x18 72 /* Register 0x19 for Digital Mixer Source*/ 73 #define ES8396_DMIX_SRC_2_REG19 0x19 74 /* Register 0x1A for DAC Digital Source and SDP1 Digital Output Source*/ 75 #define ES8396_DAC_SRC_SDP1O_SRC_REG1A 0x1A 76 /* Register 0x1B for SDP2 and SDP3 Digital Output Source*/ 77 #define ES8396_SDP2O_SDP3O_SRC_REG1B 0x1B 78 /* Register 0x1C for EQ CLOCK and OSR Selection*/ 79 #define ES8396_EQ_CLK_OSR_SEL_REG1C 0x1C 80 /* Register 0x1D for Address of shared register map*/ 81 #define ES8396_SHARED_ADDR_REG1D 0x1D 82 /* Register 0x1E for DATA of shared register map*/ 83 #define ES8396_SHARED_DATA_REG1E 0x1E 84 85 /* Serial AUDIO Interface Register Definition */ 86 /* Register 0x1F for SDP1 INPUT FORMAT*/ 87 #define ES8396_SDP1_IN_FMT_REG1F 0x1F 88 /* Register 0x20 for SDP1 OUTPUT FORMAT*/ 89 #define ES8396_SDP1_OUT_FMT_REG20 0x20 90 /* Register 0x21 for SDP1 Digital GAIN AND TDM MODE*/ 91 #define ES8396_SDP1_DGAIN_TDM_REG21 0x21 92 /* Register 0x22 for SDP2 INPUT FORMAT*/ 93 #define ES8396_SDP2_IN_FMT_REG22 0x22 94 /* Register 0x23 for SDP2 OUTPUT FORMAT*/ 95 #define ES8396_SDP2_OUT_FMT_REG23 0x23 96 /* Register 0x24 for SDP3 INPUT FORMAT*/ 97 #define ES8396_SDP3_IN_FMT_REG24 0x24 98 /* Register 0x25 for SDP3 OUTPUT FORMAT*/ 99 #define ES8396_SDP3_OUT_FMT_REG25 0x25 100 101 /* SPEAKER MIXER Register Definition */ 102 /* Register 0x26 for SPK MIXER*/ 103 #define ES8396_SPK_MIXER_REG26 0x26 104 /* Register 0x27 for SPK MIXER BOOST GAIN*/ 105 #define ES8396_SPK_MIXER_BOOST_REG27 0x27 106 /* Register 0x28 for SPK MIXER VOLUME*/ 107 #define ES8396_SPK_MIXER_VOL_REG28 0x28 108 /* Register 0x29 for SPK MIXER REFERENCE AND LOW POWER MODE*/ 109 #define ES8396_SPK_MIXER_REF_LP_REG29 0x29 110 111 /* HP MIXER Register Definition */ 112 /* Register 0x2A for HP MIXER*/ 113 #define ES8396_HP_MIXER_REG2A 0x2A 114 /* Register 0x2B for HP MIXER BOOST GAIN*/ 115 #define ES8396_HP_MIXER_BOOST_REG2B 0x2B 116 /* Register 0x2C for HP MIXER VOLUME*/ 117 #define ES8396_HP_MIXER_VOL_REG2C 0x2C 118 /* Register 0x2D for HP MIXER REFERENCE AND LOW POWER MODE*/ 119 #define ES8396_HP_MIXER_REF_LP_REG2D 0x2D 120 121 /* AX MIXER Register Definition */ 122 /* Register 0x2E for AX MIXER*/ 123 #define ES8396_AX_MIXER_REG2E 0x2E 124 /* Register 0x2F for AX MIXER BOOST GAIN*/ 125 #define ES8396_AX_MIXER_BOOST_REG2F 0x2F 126 /* Register 0x30 for AX MIXER VOLUME*/ 127 #define ES8396_AX_MIXER_VOL_REG30 0x30 128 /* Register 0x31 for AX MIXER REFERENCE AND LOW POWER MODE*/ 129 #define ES8396_AX_MIXER_REF_LP_REG31 0x31 130 131 /* LN MIXER Register Definition */ 132 /* Register 0x32 for LN MIXER*/ 133 #define ES8396_LN_MIXER_REG32 0x32 134 /* Register 0x33 for LN MIXER BOOST GAIN*/ 135 #define ES8396_LN_MIXER_BOOST_REG33 0x33 136 /* Register 0x34 for LN MIXER VOLUME*/ 137 #define ES8396_LN_MIXER_VOL_REG34 0x34 138 /* Register 0x35 for LN MIXER REFERENCE AND LOW POWER MODE*/ 139 #define ES8396_LN_MIXER_REF_LP_REG35 0x35 140 141 /* MN MIXER Register Definition */ 142 /* Register 0x36 for MN MIXER*/ 143 #define ES8396_MN_MIXER_REG36 0x36 144 /* Register 0x37 for MN MIXER BOOST GAIN*/ 145 #define ES8396_MN_MIXER_BOOST_REG37 0x37 146 /* Register 0x38 for MN MIXER VOLUME*/ 147 #define ES8396_MN_MIXER_VOL_REG38 0x38 148 /* Register 0x39 for MN MIXER REFERENCE AND LOW POWER MODE*/ 149 #define ES8396_MN_MIXER_REF_LP_REG39 0x39 150 151 /* SPKD Register Definition */ 152 /* Register 0x3A for CLASS D control and SOURCE SELECTION*/ 153 #define ES8396_SPK_CTRL_SRC_REG3A 0x3A 154 /* Register 0x3B for CLASS D Enabled and Volume Control*/ 155 #define ES8396_SPK_EN_VOL_REG3B 0x3B 156 /* Register 0x3C for CLASS D CONTROL */ 157 #define ES8396_SPK_CTRL_1_REG3C 0x3C 158 /* Register 0x3D for CLASS D CONTROL*/ 159 #define ES8396_SPK_CTRL_2_REG3D 0x3D 160 161 /* CPHP Register Definition */ 162 /* Register 0x3E for CPHP HPL ICAL VALUE*/ 163 #define ES8396_CPHP_HPL_ICAL_REG3E 0x3E 164 /* Register 0x3F for CPHP HPR ICAL VALUE*/ 165 #define ES8396_CPHP_HPR_ICAL_REG3F 0x3F 166 /* Register 0x40 for CPHP ENABLE */ 167 #define ES8396_CPHP_ENABLE_REG40 0x40 168 /* Register 0x41 for CPHP VOLUME AND ICAL ENABLE*/ 169 #define ES8396_CPHP_ICAL_VOL_REG41 0x41 170 /* Register 0x42 for CPHP CONTROL */ 171 #define ES8396_CPHP_CTRL_1_REG42 0x42 172 /* Register 0x43 for CPHP CONTROL*/ 173 #define ES8396_CPHP_CTRL_2_REG43 0x43 174 /* Register 0x44 for CPHP CONTROL*/ 175 #define ES8396_CPHP_CTRL_3_REG44 0x44 176 177 /* MONOHP Register Definition */ 178 /* Register 0x45 for MONOHP REFERENCE AND LOW POWER MODE*/ 179 #define ES8396_MONOHP_REF_LP_REG45 0x45 180 /* Register 0x46 for MONOHP N MIXER*/ 181 #define ES8396_MONOHP_N_MIXER_REG46 0x46 182 /* Register 0x47 for MONOHP P MIXER */ 183 #define ES8396_MONOHP_P_MIXER_REG47 0x47 184 /* Register 0x48 for MONOHP P BOOST AND MUTE CONTROL*/ 185 #define ES8396_MONOHP_P_BOOST_MUTE_REG48 0x48 186 /* Register 0x49 for MONOHP N BOOST AND MUTE CONTROL */ 187 #define ES8396_MONOHP_N_BOOST_MUTE_REG49 0x49 188 189 /* LNOUT Register Definition */ 190 /* Register 0x4A for LNOUT LOUT1 ENABLE AND MIXER*/ 191 #define ES8396_LNOUT_LO1EN_LO1MIX_REG4A 0x4A 192 /* Register 0x4B for LNOUT ROUT1 ENABLE AND MIXER*/ 193 #define ES8396_LNOUT_RO1EN_RO1MIX_REG4B 0x4B 194 /* Register 0x4C for LNOUT LOUT2 ENABLE AND MIXER*/ 195 #define ES8396_LNOUT_LO2EN_LO2MIX_REG4C 0x4C 196 /* Register 0x4D for LNOUT ROUT2 ENABLE AND MIXER*/ 197 #define ES8396_LNOUT_RO2EN_RO2MIX_REG4D 0x4D 198 /* Register 0x4E for LNOUT LOUT1 GAIN CONTROL */ 199 #define ES8396_LNOUT_LO1_GAIN_CTRL_REG4E 0x4E 200 /* Register 0x4F for LNOUT ROUT1 GAIN CONTROL */ 201 #define ES8396_LNOUT_RO1_GAIN_CTRL_REG4F 0x4F 202 /* Register 0x50 for LNOUT LOUT2 GAIN CONTROL */ 203 #define ES8396_LNOUT_LO2_GAIN_CTRL_REG50 0x50 204 /* Register 0x51 for LNOUT ROUT2 GAIN CONTROL */ 205 #define ES8396_LNOUT_RO2_GAIN_CTRL_REG51 0x51 206 /* Register 0x52 for LNOUT REFERENCE */ 207 #define ES8396_LNOUT_REFERENCE_REG52 0x52 208 209 /* ADC Register Definition */ 210 /* Register 0x53 for ADC CHIP STATE MACHINE and Digital Control*/ 211 #define ES8396_ADC_CSM_REG53 0x53 212 /* Register 0x54 for ADC DMIC and Ramp Rate*/ 213 #define ES8396_ADC_DMIC_RAMPRATE_REG54 0x54 214 /* Register 0x55 for ADC HIGH PASS FILTER,U-LAW/A-LAW COMPMODE,DATA SELECTION*/ 215 #define ES8396_ADC_HPF_COMP_DASEL_REG55 0x55 216 /* Register 0x56 for ADC LEFT ADC VOLUME*/ 217 #define ES8396_ADC_LADC_VOL_REG56 0x56 218 /* Register 0x57 for ADC RIGHT ADC VOLUME */ 219 #define ES8396_ADC_RADC_VOL_REG57 0x57 220 /* Register 0x58 for ADC ALC CONTROL 1*/ 221 #define ES8396_ADC_ALC_CTRL_1_REG58 0x58 222 /* Register 0x59 for ADC ALC CONTROL 2 */ 223 #define ES8396_ADC_ALC_CTRL_2_REG59 0x59 224 /* Register 0x5A for ADC ALC CONTROL 3 */ 225 #define ES8396_ADC_ALC_CTRL_3_REG5A 0x5A 226 /* Register 0x5B for ADC ALC CONTROL 4 */ 227 #define ES8396_ADC_ALC_CTRL_4_REG5B 0x5B 228 /* Register 0x5C for ADC ALC CONTROL 5*/ 229 #define ES8396_ADC_ALC_CTRL_5_REG5C 0x5C 230 /* Register 0x5D for ADC ALC CONTROL 6*/ 231 #define ES8396_ADC_ALC_CTRL_6_REG5D 0x5D 232 /* Register 0x5E for ADC ANALOG CONTROL*/ 233 #define ES8396_ADC_ANALOG_CTRL_REG5E 0x5E 234 /* Register 0x5F for ADC LOW POWER MODE AND REFERENCE*/ 235 #define ES8396_ADC_LP_REFERENCE_REG5F 0x5F 236 /* Register 0x60 for ADC MIC BOOST */ 237 #define ES8396_ADC_MICBOOST_REG60 0x60 238 /* Register 0x61 for ADC L/R PGA GAIN */ 239 #define ES8396_ADC_PGA_GAIN_REG61 0x61 240 /* Register 0x62 for ADC LPGA MIXER */ 241 #define ES8396_ADC_LPGA_MIXER_REG62 0x62 242 /* Register 0x63 for ADC RPGA MIXER */ 243 #define ES8396_ADC_RPGA_MIXER_REG63 0x63 244 /* Register 0x64 for ADC LNMUX */ 245 #define ES8396_ADC_LN_MUX_REG64 0x64 246 /* Register 0x65 for ADC AXMUX */ 247 #define ES8396_ADC_AX_MUX_REG65 0x65 248 249 /* DAC Register Definition */ 250 /* Register 0x66 for DAC CHIP STATE MACHINE AND MUTE CONTROL*/ 251 #define ES8396_DAC_CSM_REG66 0x66 252 /* Register 0x67 for DAC RAMPE RATE AND MONO/ZERO CONTROL*/ 253 #define ES8396_DAC_RAMP_RATE_REG67 0x67 254 /* Register 0x68 for DAC STEREO ENHANCEMENT */ 255 #define ES8396_DAC_STEREO_ENHANCE_REG68 0x68 256 /* Register 0x69 for DAC JACK DETECTION AND U/A-LAW COMPRESS */ 257 #define ES8396_DAC_JACK_DET_COMP_REG69 0x69 258 /* Register 0x6A for DAC LEFT DAC VOLUME */ 259 #define ES8396_DAC_LDAC_VOL_REG6A 0x6A 260 /* Register 0x6B for DAC RIGHT DAC VOLUME */ 261 #define ES8396_DAC_RDAC_VOL_REG6B 0x6B 262 /* Register 0x6C for DAC LIMITER CONTROL 1 */ 263 #define ES8396_DAC_DPL_CTRL_1_REG6C 0x6C 264 /* Register 0x6D for DAC LIMITER CONTROL 2 */ 265 #define ES8396_DAC_DPL_CTRL_2_REG6D 0x6D 266 /* Register 0x6E for DAC REFERENCE AND POWER CONTROL */ 267 #define ES8396_DAC_REF_PWR_CTRL_REG6E 0x6E 268 /* Register 0x6F for DAC DC OFFSET CALIBRATION */ 269 #define ES8396_DAC_OFFSET_CALI_REG6F 0x6F 270 271 /* SYSTEM Register Definition */ 272 /* Register 0x70 for CHIP ANALOG CONTROL, 273 * SUCH AS ANALOG POWER CONTROL, AVDDLDO POWER CONTROL */ 274 #define ES8396_SYS_CHIP_ANA_CTL_REG70 0x70 275 /* Register 0x71 for VMID SELECTION AND REFERENCE */ 276 #define ES8396_SYS_VMID_REF_REG71 0x71 277 /* Register 0x72 for VSEL 1 */ 278 #define ES8396_SYS_VSEL_1_REG72 0x72 279 /* Register 0x73 for VSEL 2 */ 280 #define ES8396_SYS_VSEL_2_REG73 0x73 281 /* Register 0x74 for MICBIAS CONTROL */ 282 #define ES8396_SYS_MICBIAS_CTRL_REG74 0x74 283 /* Register 0x75 for MIC ENABLE AND IBIASGEN SELECTION*/ 284 #define ES8396_SYS_MIC_IBIAS_EN_REG75 0x75 285 286 /* undocumented */ 287 /* Write 0XA0 TO REG0X76 to ENABLE TEST MODE*/ 288 #define ES8396_TEST_MODE_REG76 0x76 289 #define ES8396_ADC_FORCE_REG77 0x77 290 #define ES8396_NGTH_REG7A 0X7A 291 #define ES8396_MAX_REGISTER 0x7F 292 293 #define NO_EVENT 0 294 #define JD_EVENT 1 295 #define BOT_EVENT 2 296 297 #define DET_HEADPHONE 1 298 #define DET_HEADSET 2 299 300 #define BOT_NULL 0 301 #define BOT_DWN 1 302 303 #define MICBIAS_3V 7 304 #define MICBIAS_2_8V 6 305 #define MICBIAS_2_5V 1 306 #define MICBIAS_2_3V 2 307 #define MICBIAS_2V 4 308 #define MICBIAS_1_5V 0 309 310 #define MIC_AMIC 0 311 #define MIC_DMIC 1 312 313 #define ANA_LDO_3V 3 314 #define ANA_LDO_2_9V 2 315 #define ANA_LDO_2_8V 1 316 #define ANA_LDO_2_7V 0 317 #define ANA_LDO_2_4V 7 318 #define ANA_LDO_2_3V 6 319 #define ANA_LDO_2_2V 5 320 #define ANA_LDO_2_1V 4 321 322 #define SPK_LDO_3_3V 3 323 #define SPK_LDO_3_2V 2 324 #define SPK_LDO_3V 1 325 #define SPK_LDO_2_9V 0 326 #define SPK_LDO_2_8V 7 327 #define SPK_LDO_2_6V 6 328 #define SPK_LDO_2_5V 5 329 #define SPK_LDO_2_4V 4 330 331 #define ES8396_AIF_MUTE 0x40 332 333 #define ES8396_SDP1 0 334 #define ES8396_SDP2 1 335 #define ES8396_SDP3 2 336 /* 337 * es8396 System clock derived from MCLK or BCLK 338 */ 339 #define ES8396_CLKID_MCLK 0 340 #define ES8396_CLKID_BCLK 1 341 #define ES8396_CLKID_PLLO 2 342 /* 343 * PLL clock source 344 */ 345 #define ES8396_PLL 0 346 347 #define ES8396_PLL_NO_SRC_0 0 348 #define ES8396_PLL_SRC_FRM_MCLK 1 349 #define ES8396_PLL_NO_SRC_1 2 350 #define ES8396_PLL_SRC_FRM_BCLK 3 351 352 #define MS_MASTER (0x24) 353 354 #endif 355