1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Register declarations for DA9052 PMICs. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright(c) 2011 Dialog Semiconductor Ltd. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: David Dajun Chen <dchen@diasemi.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __LINUX_MFD_DA9052_REG_H 11*4882a593Smuzhiyun #define __LINUX_MFD_DA9052_REG_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* PAGE REGISTERS */ 14*4882a593Smuzhiyun #define DA9052_PAGE0_CON_REG 0 15*4882a593Smuzhiyun #define DA9052_PAGE1_CON_REG 128 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* STATUS REGISTERS */ 18*4882a593Smuzhiyun #define DA9052_STATUS_A_REG 1 19*4882a593Smuzhiyun #define DA9052_STATUS_B_REG 2 20*4882a593Smuzhiyun #define DA9052_STATUS_C_REG 3 21*4882a593Smuzhiyun #define DA9052_STATUS_D_REG 4 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* PARK REGISTER */ 24*4882a593Smuzhiyun #define DA9052_PARK_REGISTER DA9052_STATUS_D_REG 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* EVENT REGISTERS */ 27*4882a593Smuzhiyun #define DA9052_EVENT_A_REG 5 28*4882a593Smuzhiyun #define DA9052_EVENT_B_REG 6 29*4882a593Smuzhiyun #define DA9052_EVENT_C_REG 7 30*4882a593Smuzhiyun #define DA9052_EVENT_D_REG 8 31*4882a593Smuzhiyun #define DA9052_FAULTLOG_REG 9 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* IRQ REGISTERS */ 34*4882a593Smuzhiyun #define DA9052_IRQ_MASK_A_REG 10 35*4882a593Smuzhiyun #define DA9052_IRQ_MASK_B_REG 11 36*4882a593Smuzhiyun #define DA9052_IRQ_MASK_C_REG 12 37*4882a593Smuzhiyun #define DA9052_IRQ_MASK_D_REG 13 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* CONTROL REGISTERS */ 40*4882a593Smuzhiyun #define DA9052_CONTROL_A_REG 14 41*4882a593Smuzhiyun #define DA9052_CONTROL_B_REG 15 42*4882a593Smuzhiyun #define DA9052_CONTROL_C_REG 16 43*4882a593Smuzhiyun #define DA9052_CONTROL_D_REG 17 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define DA9052_PDDIS_REG 18 46*4882a593Smuzhiyun #define DA9052_INTERFACE_REG 19 47*4882a593Smuzhiyun #define DA9052_RESET_REG 20 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* GPIO REGISTERS */ 50*4882a593Smuzhiyun #define DA9052_GPIO_0_1_REG 21 51*4882a593Smuzhiyun #define DA9052_GPIO_2_3_REG 22 52*4882a593Smuzhiyun #define DA9052_GPIO_4_5_REG 23 53*4882a593Smuzhiyun #define DA9052_GPIO_6_7_REG 24 54*4882a593Smuzhiyun #define DA9052_GPIO_8_9_REG 25 55*4882a593Smuzhiyun #define DA9052_GPIO_10_11_REG 26 56*4882a593Smuzhiyun #define DA9052_GPIO_12_13_REG 27 57*4882a593Smuzhiyun #define DA9052_GPIO_14_15_REG 28 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* POWER SEQUENCER CONTROL REGISTERS */ 60*4882a593Smuzhiyun #define DA9052_ID_0_1_REG 29 61*4882a593Smuzhiyun #define DA9052_ID_2_3_REG 30 62*4882a593Smuzhiyun #define DA9052_ID_4_5_REG 31 63*4882a593Smuzhiyun #define DA9052_ID_6_7_REG 32 64*4882a593Smuzhiyun #define DA9052_ID_8_9_REG 33 65*4882a593Smuzhiyun #define DA9052_ID_10_11_REG 34 66*4882a593Smuzhiyun #define DA9052_ID_12_13_REG 35 67*4882a593Smuzhiyun #define DA9052_ID_14_15_REG 36 68*4882a593Smuzhiyun #define DA9052_ID_16_17_REG 37 69*4882a593Smuzhiyun #define DA9052_ID_18_19_REG 38 70*4882a593Smuzhiyun #define DA9052_ID_20_21_REG 39 71*4882a593Smuzhiyun #define DA9052_SEQ_STATUS_REG 40 72*4882a593Smuzhiyun #define DA9052_SEQ_A_REG 41 73*4882a593Smuzhiyun #define DA9052_SEQ_B_REG 42 74*4882a593Smuzhiyun #define DA9052_SEQ_TIMER_REG 43 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* LDO AND BUCK REGISTERS */ 77*4882a593Smuzhiyun #define DA9052_BUCKA_REG 44 78*4882a593Smuzhiyun #define DA9052_BUCKB_REG 45 79*4882a593Smuzhiyun #define DA9052_BUCKCORE_REG 46 80*4882a593Smuzhiyun #define DA9052_BUCKPRO_REG 47 81*4882a593Smuzhiyun #define DA9052_BUCKMEM_REG 48 82*4882a593Smuzhiyun #define DA9052_BUCKPERI_REG 49 83*4882a593Smuzhiyun #define DA9052_LDO1_REG 50 84*4882a593Smuzhiyun #define DA9052_LDO2_REG 51 85*4882a593Smuzhiyun #define DA9052_LDO3_REG 52 86*4882a593Smuzhiyun #define DA9052_LDO4_REG 53 87*4882a593Smuzhiyun #define DA9052_LDO5_REG 54 88*4882a593Smuzhiyun #define DA9052_LDO6_REG 55 89*4882a593Smuzhiyun #define DA9052_LDO7_REG 56 90*4882a593Smuzhiyun #define DA9052_LDO8_REG 57 91*4882a593Smuzhiyun #define DA9052_LDO9_REG 58 92*4882a593Smuzhiyun #define DA9052_LDO10_REG 59 93*4882a593Smuzhiyun #define DA9052_SUPPLY_REG 60 94*4882a593Smuzhiyun #define DA9052_PULLDOWN_REG 61 95*4882a593Smuzhiyun #define DA9052_CHGBUCK_REG 62 96*4882a593Smuzhiyun #define DA9052_WAITCONT_REG 63 97*4882a593Smuzhiyun #define DA9052_ISET_REG 64 98*4882a593Smuzhiyun #define DA9052_BATCHG_REG 65 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* BATTERY CONTROL REGISTRS */ 101*4882a593Smuzhiyun #define DA9052_CHG_CONT_REG 66 102*4882a593Smuzhiyun #define DA9052_INPUT_CONT_REG 67 103*4882a593Smuzhiyun #define DA9052_CHG_TIME_REG 68 104*4882a593Smuzhiyun #define DA9052_BBAT_CONT_REG 69 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* LED CONTROL REGISTERS */ 107*4882a593Smuzhiyun #define DA9052_BOOST_REG 70 108*4882a593Smuzhiyun #define DA9052_LED_CONT_REG 71 109*4882a593Smuzhiyun #define DA9052_LEDMIN123_REG 72 110*4882a593Smuzhiyun #define DA9052_LED1_CONF_REG 73 111*4882a593Smuzhiyun #define DA9052_LED2_CONF_REG 74 112*4882a593Smuzhiyun #define DA9052_LED3_CONF_REG 75 113*4882a593Smuzhiyun #define DA9052_LED1CONT_REG 76 114*4882a593Smuzhiyun #define DA9052_LED2CONT_REG 77 115*4882a593Smuzhiyun #define DA9052_LED3CONT_REG 78 116*4882a593Smuzhiyun #define DA9052_LED_CONT_4_REG 79 117*4882a593Smuzhiyun #define DA9052_LED_CONT_5_REG 80 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* ADC CONTROL REGISTERS */ 120*4882a593Smuzhiyun #define DA9052_ADC_MAN_REG 81 121*4882a593Smuzhiyun #define DA9052_ADC_CONT_REG 82 122*4882a593Smuzhiyun #define DA9052_ADC_RES_L_REG 83 123*4882a593Smuzhiyun #define DA9052_ADC_RES_H_REG 84 124*4882a593Smuzhiyun #define DA9052_VDD_RES_REG 85 125*4882a593Smuzhiyun #define DA9052_VDD_MON_REG 86 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define DA9052_ICHG_AV_REG 87 128*4882a593Smuzhiyun #define DA9052_ICHG_THD_REG 88 129*4882a593Smuzhiyun #define DA9052_ICHG_END_REG 89 130*4882a593Smuzhiyun #define DA9052_TBAT_RES_REG 90 131*4882a593Smuzhiyun #define DA9052_TBAT_HIGHP_REG 91 132*4882a593Smuzhiyun #define DA9052_TBAT_HIGHN_REG 92 133*4882a593Smuzhiyun #define DA9052_TBAT_LOW_REG 93 134*4882a593Smuzhiyun #define DA9052_T_OFFSET_REG 94 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define DA9052_ADCIN4_RES_REG 95 137*4882a593Smuzhiyun #define DA9052_AUTO4_HIGH_REG 96 138*4882a593Smuzhiyun #define DA9052_AUTO4_LOW_REG 97 139*4882a593Smuzhiyun #define DA9052_ADCIN5_RES_REG 98 140*4882a593Smuzhiyun #define DA9052_AUTO5_HIGH_REG 99 141*4882a593Smuzhiyun #define DA9052_AUTO5_LOW_REG 100 142*4882a593Smuzhiyun #define DA9052_ADCIN6_RES_REG 101 143*4882a593Smuzhiyun #define DA9052_AUTO6_HIGH_REG 102 144*4882a593Smuzhiyun #define DA9052_AUTO6_LOW_REG 103 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define DA9052_TJUNC_RES_REG 104 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* TSI CONTROL REGISTERS */ 149*4882a593Smuzhiyun #define DA9052_TSI_CONT_A_REG 105 150*4882a593Smuzhiyun #define DA9052_TSI_CONT_B_REG 106 151*4882a593Smuzhiyun #define DA9052_TSI_X_MSB_REG 107 152*4882a593Smuzhiyun #define DA9052_TSI_Y_MSB_REG 108 153*4882a593Smuzhiyun #define DA9052_TSI_LSB_REG 109 154*4882a593Smuzhiyun #define DA9052_TSI_Z_MSB_REG 110 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* RTC COUNT REGISTERS */ 157*4882a593Smuzhiyun #define DA9052_COUNT_S_REG 111 158*4882a593Smuzhiyun #define DA9052_COUNT_MI_REG 112 159*4882a593Smuzhiyun #define DA9052_COUNT_H_REG 113 160*4882a593Smuzhiyun #define DA9052_COUNT_D_REG 114 161*4882a593Smuzhiyun #define DA9052_COUNT_MO_REG 115 162*4882a593Smuzhiyun #define DA9052_COUNT_Y_REG 116 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* RTC CONTROL REGISTERS */ 165*4882a593Smuzhiyun #define DA9052_ALARM_MI_REG 117 166*4882a593Smuzhiyun #define DA9052_ALARM_H_REG 118 167*4882a593Smuzhiyun #define DA9052_ALARM_D_REG 119 168*4882a593Smuzhiyun #define DA9052_ALARM_MO_REG 120 169*4882a593Smuzhiyun #define DA9052_ALARM_Y_REG 121 170*4882a593Smuzhiyun #define DA9052_SECOND_A_REG 122 171*4882a593Smuzhiyun #define DA9052_SECOND_B_REG 123 172*4882a593Smuzhiyun #define DA9052_SECOND_C_REG 124 173*4882a593Smuzhiyun #define DA9052_SECOND_D_REG 125 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* PAGE CONFIGURATION BIT */ 176*4882a593Smuzhiyun #define DA9052_PAGE_CONF 0X80 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* STATUS REGISTER A BITS */ 179*4882a593Smuzhiyun #define DA9052_STATUSA_VDATDET 0X80 180*4882a593Smuzhiyun #define DA9052_STATUSA_VBUSSEL 0X40 181*4882a593Smuzhiyun #define DA9052_STATUSA_DCINSEL 0X20 182*4882a593Smuzhiyun #define DA9052_STATUSA_VBUSDET 0X10 183*4882a593Smuzhiyun #define DA9052_STATUSA_DCINDET 0X08 184*4882a593Smuzhiyun #define DA9052_STATUSA_IDGND 0X04 185*4882a593Smuzhiyun #define DA9052_STATUSA_IDFLOAT 0X02 186*4882a593Smuzhiyun #define DA9052_STATUSA_NONKEY 0X01 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* STATUS REGISTER B BITS */ 189*4882a593Smuzhiyun #define DA9052_STATUSB_COMPDET 0X80 190*4882a593Smuzhiyun #define DA9052_STATUSB_SEQUENCING 0X40 191*4882a593Smuzhiyun #define DA9052_STATUSB_GPFB2 0X20 192*4882a593Smuzhiyun #define DA9052_STATUSB_CHGTO 0X10 193*4882a593Smuzhiyun #define DA9052_STATUSB_CHGEND 0X08 194*4882a593Smuzhiyun #define DA9052_STATUSB_CHGLIM 0X04 195*4882a593Smuzhiyun #define DA9052_STATUSB_CHGPRE 0X02 196*4882a593Smuzhiyun #define DA9052_STATUSB_CHGATT 0X01 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* STATUS REGISTER C BITS */ 199*4882a593Smuzhiyun #define DA9052_STATUSC_GPI7 0X80 200*4882a593Smuzhiyun #define DA9052_STATUSC_GPI6 0X40 201*4882a593Smuzhiyun #define DA9052_STATUSC_GPI5 0X20 202*4882a593Smuzhiyun #define DA9052_STATUSC_GPI4 0X10 203*4882a593Smuzhiyun #define DA9052_STATUSC_GPI3 0X08 204*4882a593Smuzhiyun #define DA9052_STATUSC_GPI2 0X04 205*4882a593Smuzhiyun #define DA9052_STATUSC_GPI1 0X02 206*4882a593Smuzhiyun #define DA9052_STATUSC_GPI0 0X01 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* STATUS REGISTER D BITS */ 209*4882a593Smuzhiyun #define DA9052_STATUSD_GPI15 0X80 210*4882a593Smuzhiyun #define DA9052_STATUSD_GPI14 0X40 211*4882a593Smuzhiyun #define DA9052_STATUSD_GPI13 0X20 212*4882a593Smuzhiyun #define DA9052_STATUSD_GPI12 0X10 213*4882a593Smuzhiyun #define DA9052_STATUSD_GPI11 0X08 214*4882a593Smuzhiyun #define DA9052_STATUSD_GPI10 0X04 215*4882a593Smuzhiyun #define DA9052_STATUSD_GPI9 0X02 216*4882a593Smuzhiyun #define DA9052_STATUSD_GPI8 0X01 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* EVENT REGISTER A BITS */ 219*4882a593Smuzhiyun #define DA9052_EVENTA_ECOMP1V2 0X80 220*4882a593Smuzhiyun #define DA9052_EVENTA_ESEQRDY 0X40 221*4882a593Smuzhiyun #define DA9052_EVENTA_EALRAM 0X20 222*4882a593Smuzhiyun #define DA9052_EVENTA_EVDDLOW 0X10 223*4882a593Smuzhiyun #define DA9052_EVENTA_EVBUSREM 0X08 224*4882a593Smuzhiyun #define DA9052_EVENTA_EDCINREM 0X04 225*4882a593Smuzhiyun #define DA9052_EVENTA_EVBUSDET 0X02 226*4882a593Smuzhiyun #define DA9052_EVENTA_EDCINDET 0X01 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* EVENT REGISTER B BITS */ 229*4882a593Smuzhiyun #define DA9052_EVENTB_ETSIREADY 0X80 230*4882a593Smuzhiyun #define DA9052_EVENTB_EPENDOWN 0X40 231*4882a593Smuzhiyun #define DA9052_EVENTB_EADCEOM 0X20 232*4882a593Smuzhiyun #define DA9052_EVENTB_ETBAT 0X10 233*4882a593Smuzhiyun #define DA9052_EVENTB_ECHGEND 0X08 234*4882a593Smuzhiyun #define DA9052_EVENTB_EIDGND 0X04 235*4882a593Smuzhiyun #define DA9052_EVENTB_EIDFLOAT 0X02 236*4882a593Smuzhiyun #define DA9052_EVENTB_ENONKEY 0X01 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /* EVENT REGISTER C BITS */ 239*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI7 0X80 240*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI6 0X40 241*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI5 0X20 242*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI4 0X10 243*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI3 0X08 244*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI2 0X04 245*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI1 0X02 246*4882a593Smuzhiyun #define DA9052_EVENTC_EGPI0 0X01 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun /* EVENT REGISTER D BITS */ 249*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI15 0X80 250*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI14 0X40 251*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI13 0X20 252*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI12 0X10 253*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI11 0X08 254*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI10 0X04 255*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI9 0X02 256*4882a593Smuzhiyun #define DA9052_EVENTD_EGPI8 0X01 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /* IRQ MASK REGISTERS BITS */ 259*4882a593Smuzhiyun #define DA9052_M_NONKEY 0X0100 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /* TSI EVENT REGISTERS BITS */ 262*4882a593Smuzhiyun #define DA9052_E_PEN_DOWN 0X4000 263*4882a593Smuzhiyun #define DA9052_E_TSI_READY 0X8000 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun /* FAULT LOG REGISTER BITS */ 266*4882a593Smuzhiyun #define DA9052_FAULTLOG_WAITSET 0X80 267*4882a593Smuzhiyun #define DA9052_FAULTLOG_NSDSET 0X40 268*4882a593Smuzhiyun #define DA9052_FAULTLOG_KEYSHUT 0X20 269*4882a593Smuzhiyun #define DA9052_FAULTLOG_TEMPOVER 0X08 270*4882a593Smuzhiyun #define DA9052_FAULTLOG_VDDSTART 0X04 271*4882a593Smuzhiyun #define DA9052_FAULTLOG_VDDFAULT 0X02 272*4882a593Smuzhiyun #define DA9052_FAULTLOG_TWDERROR 0X01 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* CONTROL REGISTER A BITS */ 275*4882a593Smuzhiyun #define DA9052_CONTROLA_GPIV 0X80 276*4882a593Smuzhiyun #define DA9052_CONTROLA_PMOTYPE 0X20 277*4882a593Smuzhiyun #define DA9052_CONTROLA_PMOV 0X10 278*4882a593Smuzhiyun #define DA9052_CONTROLA_PMIV 0X08 279*4882a593Smuzhiyun #define DA9052_CONTROLA_PMIFV 0X08 280*4882a593Smuzhiyun #define DA9052_CONTROLA_PWR1EN 0X04 281*4882a593Smuzhiyun #define DA9052_CONTROLA_PWREN 0X02 282*4882a593Smuzhiyun #define DA9052_CONTROLA_SYSEN 0X01 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun /* CONTROL REGISTER B BITS */ 285*4882a593Smuzhiyun #define DA9052_CONTROLB_SHUTDOWN 0X80 286*4882a593Smuzhiyun #define DA9052_CONTROLB_DEEPSLEEP 0X40 287*4882a593Smuzhiyun #define DA9052_CONTROL_B_WRITEMODE 0X20 288*4882a593Smuzhiyun #define DA9052_CONTROLB_BBATEN 0X10 289*4882a593Smuzhiyun #define DA9052_CONTROLB_OTPREADEN 0X08 290*4882a593Smuzhiyun #define DA9052_CONTROLB_AUTOBOOT 0X04 291*4882a593Smuzhiyun #define DA9052_CONTROLB_ACTDIODE 0X02 292*4882a593Smuzhiyun #define DA9052_CONTROLB_BUCKMERGE 0X01 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* CONTROL REGISTER C BITS */ 295*4882a593Smuzhiyun #define DA9052_CONTROLC_BLINKDUR 0X80 296*4882a593Smuzhiyun #define DA9052_CONTROLC_BLINKFRQ 0X60 297*4882a593Smuzhiyun #define DA9052_CONTROLC_DEBOUNCING 0X1C 298*4882a593Smuzhiyun #define DA9052_CONTROLC_PMFB2PIN 0X02 299*4882a593Smuzhiyun #define DA9052_CONTROLC_PMFB1PIN 0X01 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* CONTROL REGISTER D BITS */ 302*4882a593Smuzhiyun #define DA9052_CONTROLD_WATCHDOG 0X80 303*4882a593Smuzhiyun #define DA9052_CONTROLD_ACCDETEN 0X40 304*4882a593Smuzhiyun #define DA9052_CONTROLD_GPI1415SD 0X20 305*4882a593Smuzhiyun #define DA9052_CONTROLD_NONKEYSD 0X10 306*4882a593Smuzhiyun #define DA9052_CONTROLD_KEEPACTEN 0X08 307*4882a593Smuzhiyun #define DA9052_CONTROLD_TWDSCALE 0X07 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* POWER DOWN DISABLE REGISTER BITS */ 310*4882a593Smuzhiyun #define DA9052_PDDIS_PMCONTPD 0X80 311*4882a593Smuzhiyun #define DA9052_PDDIS_OUT32KPD 0X40 312*4882a593Smuzhiyun #define DA9052_PDDIS_CHGBBATPD 0X20 313*4882a593Smuzhiyun #define DA9052_PDDIS_CHGPD 0X10 314*4882a593Smuzhiyun #define DA9052_PDDIS_HS2WIREPD 0X08 315*4882a593Smuzhiyun #define DA9052_PDDIS_PMIFPD 0X04 316*4882a593Smuzhiyun #define DA9052_PDDIS_GPADCPD 0X02 317*4882a593Smuzhiyun #define DA9052_PDDIS_GPIOPD 0X01 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* CONTROL REGISTER D BITS */ 320*4882a593Smuzhiyun #define DA9052_INTERFACE_IFBASEADDR 0XE0 321*4882a593Smuzhiyun #define DA9052_INTERFACE_NCSPOL 0X10 322*4882a593Smuzhiyun #define DA9052_INTERFACE_RWPOL 0X08 323*4882a593Smuzhiyun #define DA9052_INTERFACE_CPHA 0X04 324*4882a593Smuzhiyun #define DA9052_INTERFACE_CPOL 0X02 325*4882a593Smuzhiyun #define DA9052_INTERFACE_IFTYPE 0X01 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun /* CONTROL REGISTER D BITS */ 328*4882a593Smuzhiyun #define DA9052_RESET_RESETEVENT 0XC0 329*4882a593Smuzhiyun #define DA9052_RESET_RESETTIMER 0X3F 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* GPIO REGISTERS */ 332*4882a593Smuzhiyun /* GPIO CONTROL REGISTER BITS */ 333*4882a593Smuzhiyun #define DA9052_GPIO_EVEN_PORT_PIN 0X03 334*4882a593Smuzhiyun #define DA9052_GPIO_EVEN_PORT_TYPE 0X04 335*4882a593Smuzhiyun #define DA9052_GPIO_EVEN_PORT_MODE 0X08 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun #define DA9052_GPIO_ODD_PORT_PIN 0X30 338*4882a593Smuzhiyun #define DA9052_GPIO_ODD_PORT_TYPE 0X40 339*4882a593Smuzhiyun #define DA9052_GPIO_ODD_PORT_MODE 0X80 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun /*POWER SEQUENCER REGISTER BITS */ 342*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */ 343*4882a593Smuzhiyun #define DA9052_ID01_LDO1STEP 0XF0 344*4882a593Smuzhiyun #define DA9052_ID01_SYSPRE 0X04 345*4882a593Smuzhiyun #define DA9052_ID01_DEFSUPPLY 0X02 346*4882a593Smuzhiyun #define DA9052_ID01_NRESMODE 0X01 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */ 349*4882a593Smuzhiyun #define DA9052_ID23_LDO3STEP 0XF0 350*4882a593Smuzhiyun #define DA9052_ID23_LDO2STEP 0X0F 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */ 353*4882a593Smuzhiyun #define DA9052_ID45_LDO5STEP 0XF0 354*4882a593Smuzhiyun #define DA9052_ID45_LDO4STEP 0X0F 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */ 357*4882a593Smuzhiyun #define DA9052_ID67_LDO7STEP 0XF0 358*4882a593Smuzhiyun #define DA9052_ID67_LDO6STEP 0X0F 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */ 361*4882a593Smuzhiyun #define DA9052_ID89_LDO9STEP 0XF0 362*4882a593Smuzhiyun #define DA9052_ID89_LDO8STEP 0X0F 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */ 365*4882a593Smuzhiyun #define DA9052_ID1011_PDDISSTEP 0XF0 366*4882a593Smuzhiyun #define DA9052_ID1011_LDO10STEP 0X0F 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */ 369*4882a593Smuzhiyun #define DA9052_ID1213_VMEMSWSTEP 0XF0 370*4882a593Smuzhiyun #define DA9052_ID1213_VPERISWSTEP 0X0F 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */ 373*4882a593Smuzhiyun #define DA9052_ID1415_BUCKPROSTEP 0XF0 374*4882a593Smuzhiyun #define DA9052_ID1415_BUCKCORESTEP 0X0F 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */ 377*4882a593Smuzhiyun #define DA9052_ID1617_BUCKPERISTEP 0XF0 378*4882a593Smuzhiyun #define DA9052_ID1617_BUCKMEMSTEP 0X0F 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */ 381*4882a593Smuzhiyun #define DA9052_ID1819_GPRISE2STEP 0XF0 382*4882a593Smuzhiyun #define DA9052_ID1819_GPRISE1STEP 0X0F 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun /* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */ 385*4882a593Smuzhiyun #define DA9052_ID2021_GPFALL2STEP 0XF0 386*4882a593Smuzhiyun #define DA9052_ID2021_GPFALL1STEP 0X0F 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* POWER SEQ STATUS REGISTER BITS */ 389*4882a593Smuzhiyun #define DA9052_SEQSTATUS_SEQPOINTER 0XF0 390*4882a593Smuzhiyun #define DA9052_SEQSTATUS_WAITSTEP 0X0F 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun /* POWER SEQ A REGISTER BITS */ 393*4882a593Smuzhiyun #define DA9052_SEQA_POWEREND 0XF0 394*4882a593Smuzhiyun #define DA9052_SEQA_SYSTEMEND 0X0F 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun /* POWER SEQ B REGISTER BITS */ 397*4882a593Smuzhiyun #define DA9052_SEQB_PARTDOWN 0XF0 398*4882a593Smuzhiyun #define DA9052_SEQB_MAXCOUNT 0X0F 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun /* POWER SEQ TIMER REGISTER BITS */ 401*4882a593Smuzhiyun #define DA9052_SEQTIMER_SEQDUMMY 0XF0 402*4882a593Smuzhiyun #define DA9052_SEQTIMER_SEQTIME 0X0F 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun /*POWER SUPPLY CONTROL REGISTER BITS */ 405*4882a593Smuzhiyun /* BUCK REGISTER A BITS */ 406*4882a593Smuzhiyun #define DA9052_BUCKA_BPROILIM 0XC0 407*4882a593Smuzhiyun #define DA9052_BUCKA_BPROMODE 0X30 408*4882a593Smuzhiyun #define DA9052_BUCKA_BCOREILIM 0X0C 409*4882a593Smuzhiyun #define DA9052_BUCKA_BCOREMODE 0X03 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun /* BUCK REGISTER B BITS */ 412*4882a593Smuzhiyun #define DA9052_BUCKB_BERIILIM 0XC0 413*4882a593Smuzhiyun #define DA9052_BUCKB_BPERIMODE 0X30 414*4882a593Smuzhiyun #define DA9052_BUCKB_BMEMILIM 0X0C 415*4882a593Smuzhiyun #define DA9052_BUCKB_BMEMMODE 0X03 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun /* BUCKCORE REGISTER BITS */ 418*4882a593Smuzhiyun #define DA9052_BUCKCORE_BCORECONF 0X80 419*4882a593Smuzhiyun #define DA9052_BUCKCORE_BCOREEN 0X40 420*4882a593Smuzhiyun #define DA9052_BUCKCORE_VBCORE 0X3F 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun /* BUCKPRO REGISTER BITS */ 423*4882a593Smuzhiyun #define DA9052_BUCKPRO_BPROCONF 0X80 424*4882a593Smuzhiyun #define DA9052_BUCKPRO_BPROEN 0X40 425*4882a593Smuzhiyun #define DA9052_BUCKPRO_VBPRO 0X3F 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun /* BUCKMEM REGISTER BITS */ 428*4882a593Smuzhiyun #define DA9052_BUCKMEM_BMEMCONF 0X80 429*4882a593Smuzhiyun #define DA9052_BUCKMEM_BMEMEN 0X40 430*4882a593Smuzhiyun #define DA9052_BUCKMEM_VBMEM 0X3F 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun /* BUCKPERI REGISTER BITS */ 433*4882a593Smuzhiyun #define DA9052_BUCKPERI_BPERICONF 0X80 434*4882a593Smuzhiyun #define DA9052_BUCKPERI_BPERIEN 0X40 435*4882a593Smuzhiyun #define DA9052_BUCKPERI_BPERIHS 0X20 436*4882a593Smuzhiyun #define DA9052_BUCKPERI_VBPERI 0X1F 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun /* LDO1 REGISTER BITS */ 439*4882a593Smuzhiyun #define DA9052_LDO1_LDO1CONF 0X80 440*4882a593Smuzhiyun #define DA9052_LDO1_LDO1EN 0X40 441*4882a593Smuzhiyun #define DA9052_LDO1_VLDO1 0X1F 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun /* LDO2 REGISTER BITS */ 444*4882a593Smuzhiyun #define DA9052_LDO2_LDO2CONF 0X80 445*4882a593Smuzhiyun #define DA9052_LDO2_LDO2EN 0X40 446*4882a593Smuzhiyun #define DA9052_LDO2_VLDO2 0X3F 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun /* LDO3 REGISTER BITS */ 449*4882a593Smuzhiyun #define DA9052_LDO3_LDO3CONF 0X80 450*4882a593Smuzhiyun #define DA9052_LDO3_LDO3EN 0X40 451*4882a593Smuzhiyun #define DA9052_LDO3_VLDO3 0X3F 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun /* LDO4 REGISTER BITS */ 454*4882a593Smuzhiyun #define DA9052_LDO4_LDO4CONF 0X80 455*4882a593Smuzhiyun #define DA9052_LDO4_LDO4EN 0X40 456*4882a593Smuzhiyun #define DA9052_LDO4_VLDO4 0X3F 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /* LDO5 REGISTER BITS */ 459*4882a593Smuzhiyun #define DA9052_LDO5_LDO5CONF 0X80 460*4882a593Smuzhiyun #define DA9052_LDO5_LDO5EN 0X40 461*4882a593Smuzhiyun #define DA9052_LDO5_VLDO5 0X3F 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun /* LDO6 REGISTER BITS */ 464*4882a593Smuzhiyun #define DA9052_LDO6_LDO6CONF 0X80 465*4882a593Smuzhiyun #define DA9052_LDO6_LDO6EN 0X40 466*4882a593Smuzhiyun #define DA9052_LDO6_VLDO6 0X3F 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun /* LDO7 REGISTER BITS */ 469*4882a593Smuzhiyun #define DA9052_LDO7_LDO7CONF 0X80 470*4882a593Smuzhiyun #define DA9052_LDO7_LDO7EN 0X40 471*4882a593Smuzhiyun #define DA9052_LDO7_VLDO7 0X3F 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun /* LDO8 REGISTER BITS */ 474*4882a593Smuzhiyun #define DA9052_LDO8_LDO8CONF 0X80 475*4882a593Smuzhiyun #define DA9052_LDO8_LDO8EN 0X40 476*4882a593Smuzhiyun #define DA9052_LDO8_VLDO8 0X3F 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun /* LDO9 REGISTER BITS */ 479*4882a593Smuzhiyun #define DA9052_LDO9_LDO9CONF 0X80 480*4882a593Smuzhiyun #define DA9052_LDO9_LDO9EN 0X40 481*4882a593Smuzhiyun #define DA9052_LDO9_VLDO9 0X3F 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun /* LDO10 REGISTER BITS */ 484*4882a593Smuzhiyun #define DA9052_LDO10_LDO10CONF 0X80 485*4882a593Smuzhiyun #define DA9052_LDO10_LDO10EN 0X40 486*4882a593Smuzhiyun #define DA9052_LDO10_VLDO10 0X3F 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun /* SUPPLY REGISTER BITS */ 489*4882a593Smuzhiyun #define DA9052_SUPPLY_VLOCK 0X80 490*4882a593Smuzhiyun #define DA9052_SUPPLY_VMEMSWEN 0X40 491*4882a593Smuzhiyun #define DA9052_SUPPLY_VPERISWEN 0X20 492*4882a593Smuzhiyun #define DA9052_SUPPLY_VLDO3GO 0X10 493*4882a593Smuzhiyun #define DA9052_SUPPLY_VLDO2GO 0X08 494*4882a593Smuzhiyun #define DA9052_SUPPLY_VBMEMGO 0X04 495*4882a593Smuzhiyun #define DA9052_SUPPLY_VBPROGO 0X02 496*4882a593Smuzhiyun #define DA9052_SUPPLY_VBCOREGO 0X01 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun /* PULLDOWN REGISTER BITS */ 499*4882a593Smuzhiyun #define DA9052_PULLDOWN_LDO5PDDIS 0X20 500*4882a593Smuzhiyun #define DA9052_PULLDOWN_LDO2PDDIS 0X10 501*4882a593Smuzhiyun #define DA9052_PULLDOWN_LDO1PDDIS 0X08 502*4882a593Smuzhiyun #define DA9052_PULLDOWN_MEMPDDIS 0X04 503*4882a593Smuzhiyun #define DA9052_PULLDOWN_PROPDDIS 0X02 504*4882a593Smuzhiyun #define DA9052_PULLDOWN_COREPDDIS 0X01 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* BAT CHARGER REGISTER BITS */ 507*4882a593Smuzhiyun /* CHARGER BUCK REGISTER BITS */ 508*4882a593Smuzhiyun #define DA9052_CHGBUCK_CHGTEMP 0X80 509*4882a593Smuzhiyun #define DA9052_CHGBUCK_CHGUSBILIM 0X40 510*4882a593Smuzhiyun #define DA9052_CHGBUCK_CHGBUCKLP 0X20 511*4882a593Smuzhiyun #define DA9052_CHGBUCK_CHGBUCKEN 0X10 512*4882a593Smuzhiyun #define DA9052_CHGBUCK_ISETBUCK 0X0F 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun /* WAIT COUNTER REGISTER BITS */ 515*4882a593Smuzhiyun #define DA9052_WAITCONT_WAITDIR 0X80 516*4882a593Smuzhiyun #define DA9052_WAITCONT_RTCCLOCK 0X40 517*4882a593Smuzhiyun #define DA9052_WAITCONT_WAITMODE 0X20 518*4882a593Smuzhiyun #define DA9052_WAITCONT_EN32KOUT 0X10 519*4882a593Smuzhiyun #define DA9052_WAITCONT_DELAYTIME 0X0F 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun /* ISET CONTROL REGISTER BITS */ 522*4882a593Smuzhiyun #define DA9052_ISET_ISETDCIN 0XF0 523*4882a593Smuzhiyun #define DA9052_ISET_ISETVBUS 0X0F 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun /* BATTERY CHARGER CONTROL REGISTER BITS */ 526*4882a593Smuzhiyun #define DA9052_BATCHG_ICHGPRE 0XC0 527*4882a593Smuzhiyun #define DA9052_BATCHG_ICHGBAT 0X3F 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun /* CHARGER COUNTER REGISTER BITS */ 530*4882a593Smuzhiyun #define DA9052_CHG_CONT_VCHG_BAT 0XF8 531*4882a593Smuzhiyun #define DA9052_CHG_CONT_TCTR 0X07 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun /* INPUT CONTROL REGISTER BITS */ 534*4882a593Smuzhiyun #define DA9052_INPUT_CONT_TCTR_MODE 0X80 535*4882a593Smuzhiyun #define DA9052_INPUT_CONT_VBUS_SUSP 0X10 536*4882a593Smuzhiyun #define DA9052_INPUT_CONT_DCIN_SUSP 0X08 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun /* CHARGING TIME REGISTER BITS */ 539*4882a593Smuzhiyun #define DA9052_CHGTIME_CHGTIME 0XFF 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun /* BACKUP BATTERY CONTROL REGISTER BITS */ 542*4882a593Smuzhiyun #define DA9052_BBATCONT_BCHARGERISET 0XF0 543*4882a593Smuzhiyun #define DA9052_BBATCONT_BCHARGERVSET 0X0F 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun /* LED REGISTERS BITS */ 546*4882a593Smuzhiyun /* LED BOOST REGISTER BITS */ 547*4882a593Smuzhiyun #define DA9052_BOOST_EBFAULT 0X80 548*4882a593Smuzhiyun #define DA9052_BOOST_MBFAULT 0X40 549*4882a593Smuzhiyun #define DA9052_BOOST_BOOSTFRQ 0X20 550*4882a593Smuzhiyun #define DA9052_BOOST_BOOSTILIM 0X10 551*4882a593Smuzhiyun #define DA9052_BOOST_LED3INEN 0X08 552*4882a593Smuzhiyun #define DA9052_BOOST_LED2INEN 0X04 553*4882a593Smuzhiyun #define DA9052_BOOST_LED1INEN 0X02 554*4882a593Smuzhiyun #define DA9052_BOOST_BOOSTEN 0X01 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun /* LED CONTROL REGISTER BITS */ 557*4882a593Smuzhiyun #define DA9052_LEDCONT_SELLEDMODE 0X80 558*4882a593Smuzhiyun #define DA9052_LEDCONT_LED3ICONT 0X40 559*4882a593Smuzhiyun #define DA9052_LEDCONT_LED3RAMP 0X20 560*4882a593Smuzhiyun #define DA9052_LEDCONT_LED3EN 0X10 561*4882a593Smuzhiyun #define DA9052_LEDCONT_LED2RAMP 0X08 562*4882a593Smuzhiyun #define DA9052_LEDCONT_LED2EN 0X04 563*4882a593Smuzhiyun #define DA9052_LEDCONT_LED1RAMP 0X02 564*4882a593Smuzhiyun #define DA9052_LEDCONT_LED1EN 0X01 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun /* LEDMIN123 REGISTER BIT */ 567*4882a593Smuzhiyun #define DA9052_LEDMIN123_LEDMINCURRENT 0XFF 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun /* LED1CONF REGISTER BIT */ 570*4882a593Smuzhiyun #define DA9052_LED1CONF_LED1CURRENT 0XFF 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun /* LED2CONF REGISTER BIT */ 573*4882a593Smuzhiyun #define DA9052_LED2CONF_LED2CURRENT 0XFF 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun /* LED3CONF REGISTER BIT */ 576*4882a593Smuzhiyun #define DA9052_LED3CONF_LED3CURRENT 0XFF 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun /* LED COUNT REGISTER BIT */ 579*4882a593Smuzhiyun #define DA9052_LED_CONT_DIM 0X80 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun /* ADC MAN REGISTERS BITS */ 582*4882a593Smuzhiyun #define DA9052_ADC_MAN_MAN_CONV 0X10 583*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00 584*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_ICH 0X01 585*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_TBAT 0X02 586*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_VBAT 0X03 587*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_AD4 0X04 588*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_AD5 0X05 589*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_AD6 0X06 590*4882a593Smuzhiyun #define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun /* ADC CONTROL REGSISTERS BITS */ 593*4882a593Smuzhiyun #define DA9052_ADCCONT_COMP1V2EN 0X80 594*4882a593Smuzhiyun #define DA9052_ADCCONT_ADCMODE 0X40 595*4882a593Smuzhiyun #define DA9052_ADCCONT_TBATISRCEN 0X20 596*4882a593Smuzhiyun #define DA9052_ADCCONT_AD4ISRCEN 0X10 597*4882a593Smuzhiyun #define DA9052_ADCCONT_AUTOAD6EN 0X08 598*4882a593Smuzhiyun #define DA9052_ADCCONT_AUTOAD5EN 0X04 599*4882a593Smuzhiyun #define DA9052_ADCCONT_AUTOAD4EN 0X02 600*4882a593Smuzhiyun #define DA9052_ADCCONT_AUTOVDDEN 0X01 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun /* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */ 603*4882a593Smuzhiyun #define DA9052_ADC_RES_LSB 0X03 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun /* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */ 606*4882a593Smuzhiyun #define DA9052_ADCRESH_ADCRESMSB 0XFF 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun /* VDD RES REGSISTER BIT*/ 609*4882a593Smuzhiyun #define DA9052_VDDRES_VDDOUTRES 0XFF 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun /* VDD MON REGSISTER BIT */ 612*4882a593Smuzhiyun #define DA9052_VDDMON_VDDOUTMON 0XFF 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun /* ICHG_AV REGSISTER BIT */ 615*4882a593Smuzhiyun #define DA9052_ICHGAV_ICHGAV 0XFF 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun /* ICHG_THD REGSISTER BIT */ 618*4882a593Smuzhiyun #define DA9052_ICHGTHD_ICHGTHD 0XFF 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun /* ICHG_END REGSISTER BIT */ 621*4882a593Smuzhiyun #define DA9052_ICHGEND_ICHGEND 0XFF 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun /* TBAT_RES REGSISTER BIT */ 624*4882a593Smuzhiyun #define DA9052_TBATRES_TBATRES 0XFF 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun /* TBAT_HIGHP REGSISTER BIT */ 627*4882a593Smuzhiyun #define DA9052_TBATHIGHP_TBATHIGHP 0XFF 628*4882a593Smuzhiyun 629*4882a593Smuzhiyun /* TBAT_HIGHN REGSISTER BIT */ 630*4882a593Smuzhiyun #define DA9052_TBATHIGHN_TBATHIGHN 0XFF 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun /* TBAT_LOW REGSISTER BIT */ 633*4882a593Smuzhiyun #define DA9052_TBATLOW_TBATLOW 0XFF 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun /* T_OFFSET REGSISTER BIT */ 636*4882a593Smuzhiyun #define DA9052_TOFFSET_TOFFSET 0XFF 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun /* ADCIN4_RES REGSISTER BIT */ 639*4882a593Smuzhiyun #define DA9052_ADCIN4RES_ADCIN4RES 0XFF 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun /* ADCIN4_HIGH REGSISTER BIT */ 642*4882a593Smuzhiyun #define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun /* ADCIN4_LOW REGSISTER BIT */ 645*4882a593Smuzhiyun #define DA9052_AUTO4LOW_AUTO4LOW 0XFF 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun /* ADCIN5_RES REGSISTER BIT */ 648*4882a593Smuzhiyun #define DA9052_ADCIN5RES_ADCIN5RES 0XFF 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun /* ADCIN5_HIGH REGSISTER BIT */ 651*4882a593Smuzhiyun #define DA9052_AUTO5HIGH_AUTOHIGH 0XFF 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun /* ADCIN5_LOW REGSISTER BIT */ 654*4882a593Smuzhiyun #define DA9052_AUTO5LOW_AUTO5LOW 0XFF 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun /* ADCIN6_RES REGSISTER BIT */ 657*4882a593Smuzhiyun #define DA9052_ADCIN6RES_ADCIN6RES 0XFF 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun /* ADCIN6_HIGH REGSISTER BIT */ 660*4882a593Smuzhiyun #define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun /* ADCIN6_LOW REGSISTER BIT */ 663*4882a593Smuzhiyun #define DA9052_AUTO6LOW_AUTO6LOW 0XFF 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun /* TJUNC_RES REGSISTER BIT*/ 666*4882a593Smuzhiyun #define DA9052_TJUNCRES_TJUNCRES 0XFF 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun /* TSI REGISTER */ 669*4882a593Smuzhiyun /* TSI CONTROL REGISTER A BITS */ 670*4882a593Smuzhiyun #define DA9052_TSICONTA_TSIDELAY 0XC0 671*4882a593Smuzhiyun #define DA9052_TSICONTA_TSISKIP 0X38 672*4882a593Smuzhiyun #define DA9052_TSICONTA_TSIMODE 0X04 673*4882a593Smuzhiyun #define DA9052_TSICONTA_PENDETEN 0X02 674*4882a593Smuzhiyun #define DA9052_TSICONTA_AUTOTSIEN 0X01 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun /* TSI CONTROL REGISTER B BITS */ 677*4882a593Smuzhiyun #define DA9052_TSICONTB_ADCREF 0X80 678*4882a593Smuzhiyun #define DA9052_TSICONTB_TSIMAN 0X40 679*4882a593Smuzhiyun #define DA9052_TSICONTB_TSIMUX_XP 0X00 680*4882a593Smuzhiyun #define DA9052_TSICONTB_TSIMUX_YP 0X10 681*4882a593Smuzhiyun #define DA9052_TSICONTB_TSIMUX_XN 0X20 682*4882a593Smuzhiyun #define DA9052_TSICONTB_TSIMUX_YN 0X30 683*4882a593Smuzhiyun #define DA9052_TSICONTB_TSISEL3 0X08 684*4882a593Smuzhiyun #define DA9052_TSICONTB_TSISEL2 0X04 685*4882a593Smuzhiyun #define DA9052_TSICONTB_TSISEL1 0X02 686*4882a593Smuzhiyun #define DA9052_TSICONTB_TSISEL0 0X01 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun /* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */ 689*4882a593Smuzhiyun #define DA9052_TSIXMSB_TSIXM 0XFF 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun /* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */ 692*4882a593Smuzhiyun #define DA9052_TSIYMSB_TSIYM 0XFF 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun /* TSI CO-ORDINATE LSB RESULT REGISTER BITS */ 695*4882a593Smuzhiyun #define DA9052_TSILSB_PENDOWN 0X40 696*4882a593Smuzhiyun #define DA9052_TSILSB_TSIZL 0X30 697*4882a593Smuzhiyun #define DA9052_TSILSB_TSIZL_SHIFT 4 698*4882a593Smuzhiyun #define DA9052_TSILSB_TSIZL_BITS 2 699*4882a593Smuzhiyun #define DA9052_TSILSB_TSIYL 0X0C 700*4882a593Smuzhiyun #define DA9052_TSILSB_TSIYL_SHIFT 2 701*4882a593Smuzhiyun #define DA9052_TSILSB_TSIYL_BITS 2 702*4882a593Smuzhiyun #define DA9052_TSILSB_TSIXL 0X03 703*4882a593Smuzhiyun #define DA9052_TSILSB_TSIXL_SHIFT 0 704*4882a593Smuzhiyun #define DA9052_TSILSB_TSIXL_BITS 2 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun /* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */ 707*4882a593Smuzhiyun #define DA9052_TSIZMSB_TSIZM 0XFF 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun /* RTC REGISTER */ 710*4882a593Smuzhiyun /* RTC TIMER SECONDS REGISTER BITS */ 711*4882a593Smuzhiyun #define DA9052_COUNTS_MONITOR 0X40 712*4882a593Smuzhiyun #define DA9052_RTC_SEC 0X3F 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun /* RTC TIMER MINUTES REGISTER BIT */ 715*4882a593Smuzhiyun #define DA9052_RTC_MIN 0X3F 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun /* RTC TIMER HOUR REGISTER BIT */ 718*4882a593Smuzhiyun #define DA9052_RTC_HOUR 0X1F 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun /* RTC TIMER DAYS REGISTER BIT */ 721*4882a593Smuzhiyun #define DA9052_RTC_DAY 0X1F 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun /* RTC TIMER MONTHS REGISTER BIT */ 724*4882a593Smuzhiyun #define DA9052_RTC_MONTH 0X0F 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun /* RTC TIMER YEARS REGISTER BIT */ 727*4882a593Smuzhiyun #define DA9052_RTC_YEAR 0X3F 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun /* RTC ALARM MINUTES REGISTER BITS */ 730*4882a593Smuzhiyun #define DA9052_ALARMM_I_TICK_TYPE 0X80 731*4882a593Smuzhiyun #define DA9052_ALARMMI_ALARMTYPE 0X40 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun /* RTC ALARM YEARS REGISTER BITS */ 734*4882a593Smuzhiyun #define DA9052_ALARM_Y_TICK_ON 0X80 735*4882a593Smuzhiyun #define DA9052_ALARM_Y_ALARM_ON 0X40 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun /* RTC SECONDS REGISTER A BITS */ 738*4882a593Smuzhiyun #define DA9052_SECONDA_SECONDSA 0XFF 739*4882a593Smuzhiyun 740*4882a593Smuzhiyun /* RTC SECONDS REGISTER B BITS */ 741*4882a593Smuzhiyun #define DA9052_SECONDB_SECONDSB 0XFF 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun /* RTC SECONDS REGISTER C BITS */ 744*4882a593Smuzhiyun #define DA9052_SECONDC_SECONDSC 0XFF 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun /* RTC SECONDS REGISTER D BITS */ 747*4882a593Smuzhiyun #define DA9052_SECONDD_SECONDSD 0XFF 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun #endif 750*4882a593Smuzhiyun /* __LINUX_MFD_DA9052_REG_H */ 751