1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /** 3*4882a593Smuzhiyun * Copyright (C) ST-Ericsson SA 2010 4*4882a593Smuzhiyun * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson. 5*4882a593Smuzhiyun * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson. 6*4882a593Smuzhiyun * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson. 7*4882a593Smuzhiyun * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson. 8*4882a593Smuzhiyun * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __CRYP_IRQP_H_ 12*4882a593Smuzhiyun #define __CRYP_IRQP_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include "cryp_irq.h" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /** 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * CRYP Registers - Offset mapping 19*4882a593Smuzhiyun * +-----------------+ 20*4882a593Smuzhiyun * 00h | CRYP_CR | Configuration register 21*4882a593Smuzhiyun * +-----------------+ 22*4882a593Smuzhiyun * 04h | CRYP_SR | Status register 23*4882a593Smuzhiyun * +-----------------+ 24*4882a593Smuzhiyun * 08h | CRYP_DIN | Data In register 25*4882a593Smuzhiyun * +-----------------+ 26*4882a593Smuzhiyun * 0ch | CRYP_DOUT | Data out register 27*4882a593Smuzhiyun * +-----------------+ 28*4882a593Smuzhiyun * 10h | CRYP_DMACR | DMA control register 29*4882a593Smuzhiyun * +-----------------+ 30*4882a593Smuzhiyun * 14h | CRYP_IMSC | IMSC 31*4882a593Smuzhiyun * +-----------------+ 32*4882a593Smuzhiyun * 18h | CRYP_RIS | Raw interrupt status 33*4882a593Smuzhiyun * +-----------------+ 34*4882a593Smuzhiyun * 1ch | CRYP_MIS | Masked interrupt status. 35*4882a593Smuzhiyun * +-----------------+ 36*4882a593Smuzhiyun * Key registers 37*4882a593Smuzhiyun * IVR registers 38*4882a593Smuzhiyun * Peripheral 39*4882a593Smuzhiyun * Cell IDs 40*4882a593Smuzhiyun * 41*4882a593Smuzhiyun * Refer data structure for other register map 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /** 45*4882a593Smuzhiyun * struct cryp_register 46*4882a593Smuzhiyun * @cr - Configuration register 47*4882a593Smuzhiyun * @status - Status register 48*4882a593Smuzhiyun * @din - Data input register 49*4882a593Smuzhiyun * @din_size - Data input size register 50*4882a593Smuzhiyun * @dout - Data output register 51*4882a593Smuzhiyun * @dout_size - Data output size register 52*4882a593Smuzhiyun * @dmacr - Dma control register 53*4882a593Smuzhiyun * @imsc - Interrupt mask set/clear register 54*4882a593Smuzhiyun * @ris - Raw interrupt status 55*4882a593Smuzhiyun * @mis - Masked interrupt statu register 56*4882a593Smuzhiyun * @key_1_l - Key register 1 L 57*4882a593Smuzhiyun * @key_1_r - Key register 1 R 58*4882a593Smuzhiyun * @key_2_l - Key register 2 L 59*4882a593Smuzhiyun * @key_2_r - Key register 2 R 60*4882a593Smuzhiyun * @key_3_l - Key register 3 L 61*4882a593Smuzhiyun * @key_3_r - Key register 3 R 62*4882a593Smuzhiyun * @key_4_l - Key register 4 L 63*4882a593Smuzhiyun * @key_4_r - Key register 4 R 64*4882a593Smuzhiyun * @init_vect_0_l - init vector 0 L 65*4882a593Smuzhiyun * @init_vect_0_r - init vector 0 R 66*4882a593Smuzhiyun * @init_vect_1_l - init vector 1 L 67*4882a593Smuzhiyun * @init_vect_1_r - init vector 1 R 68*4882a593Smuzhiyun * @cryp_unused1 - unused registers 69*4882a593Smuzhiyun * @itcr - Integration test control register 70*4882a593Smuzhiyun * @itip - Integration test input register 71*4882a593Smuzhiyun * @itop - Integration test output register 72*4882a593Smuzhiyun * @cryp_unused2 - unused registers 73*4882a593Smuzhiyun * @periphId0 - FE0 CRYP Peripheral Identication Register 74*4882a593Smuzhiyun * @periphId1 - FE4 75*4882a593Smuzhiyun * @periphId2 - FE8 76*4882a593Smuzhiyun * @periphId3 - FEC 77*4882a593Smuzhiyun * @pcellId0 - FF0 CRYP PCell Identication Register 78*4882a593Smuzhiyun * @pcellId1 - FF4 79*4882a593Smuzhiyun * @pcellId2 - FF8 80*4882a593Smuzhiyun * @pcellId3 - FFC 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun struct cryp_register { 83*4882a593Smuzhiyun u32 cr; /* Configuration register */ 84*4882a593Smuzhiyun u32 sr; /* Status register */ 85*4882a593Smuzhiyun u32 din; /* Data input register */ 86*4882a593Smuzhiyun u32 din_size; /* Data input size register */ 87*4882a593Smuzhiyun u32 dout; /* Data output register */ 88*4882a593Smuzhiyun u32 dout_size; /* Data output size register */ 89*4882a593Smuzhiyun u32 dmacr; /* Dma control register */ 90*4882a593Smuzhiyun u32 imsc; /* Interrupt mask set/clear register */ 91*4882a593Smuzhiyun u32 ris; /* Raw interrupt status */ 92*4882a593Smuzhiyun u32 mis; /* Masked interrupt statu register */ 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun u32 key_1_l; /*Key register 1 L */ 95*4882a593Smuzhiyun u32 key_1_r; /*Key register 1 R */ 96*4882a593Smuzhiyun u32 key_2_l; /*Key register 2 L */ 97*4882a593Smuzhiyun u32 key_2_r; /*Key register 2 R */ 98*4882a593Smuzhiyun u32 key_3_l; /*Key register 3 L */ 99*4882a593Smuzhiyun u32 key_3_r; /*Key register 3 R */ 100*4882a593Smuzhiyun u32 key_4_l; /*Key register 4 L */ 101*4882a593Smuzhiyun u32 key_4_r; /*Key register 4 R */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun u32 init_vect_0_l; /*init vector 0 L */ 104*4882a593Smuzhiyun u32 init_vect_0_r; /*init vector 0 R */ 105*4882a593Smuzhiyun u32 init_vect_1_l; /*init vector 1 L */ 106*4882a593Smuzhiyun u32 init_vect_1_r; /*init vector 1 R */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun u32 cryp_unused1[(0x80 - 0x58) / sizeof(u32)]; /* unused registers */ 109*4882a593Smuzhiyun u32 itcr; /*Integration test control register */ 110*4882a593Smuzhiyun u32 itip; /*Integration test input register */ 111*4882a593Smuzhiyun u32 itop; /*Integration test output register */ 112*4882a593Smuzhiyun u32 cryp_unused2[(0xFE0 - 0x8C) / sizeof(u32)]; /* unused registers */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun u32 periphId0; /* FE0 CRYP Peripheral Identication Register */ 115*4882a593Smuzhiyun u32 periphId1; /* FE4 */ 116*4882a593Smuzhiyun u32 periphId2; /* FE8 */ 117*4882a593Smuzhiyun u32 periphId3; /* FEC */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun u32 pcellId0; /* FF0 CRYP PCell Identication Register */ 120*4882a593Smuzhiyun u32 pcellId1; /* FF4 */ 121*4882a593Smuzhiyun u32 pcellId2; /* FF8 */ 122*4882a593Smuzhiyun u32 pcellId3; /* FFC */ 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #endif 126