1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ATMEL_ISC_REGS_H 3*4882a593Smuzhiyun #define __ATMEL_ISC_REGS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/bitops.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* ISC Control Enable Register 0 */ 8*4882a593Smuzhiyun #define ISC_CTRLEN 0x00000000 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* ISC Control Disable Register 0 */ 11*4882a593Smuzhiyun #define ISC_CTRLDIS 0x00000004 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* ISC Control Status Register 0 */ 14*4882a593Smuzhiyun #define ISC_CTRLSR 0x00000008 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define ISC_CTRL_CAPTURE BIT(0) 17*4882a593Smuzhiyun #define ISC_CTRL_UPPRO BIT(1) 18*4882a593Smuzhiyun #define ISC_CTRL_HISREQ BIT(2) 19*4882a593Smuzhiyun #define ISC_CTRL_HISCLR BIT(3) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* ISC Parallel Front End Configuration 0 Register */ 22*4882a593Smuzhiyun #define ISC_PFE_CFG0 0x0000000c 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define ISC_PFE_CFG0_HPOL_LOW BIT(0) 25*4882a593Smuzhiyun #define ISC_PFE_CFG0_VPOL_LOW BIT(1) 26*4882a593Smuzhiyun #define ISC_PFE_CFG0_PPOL_LOW BIT(2) 27*4882a593Smuzhiyun #define ISC_PFE_CFG0_CCIR656 BIT(9) 28*4882a593Smuzhiyun #define ISC_PFE_CFG0_CCIR_CRC BIT(10) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) 31*4882a593Smuzhiyun #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define ISC_PFE_CFG0_BPS_EIGHT (0x4 << 28) 34*4882a593Smuzhiyun #define ISC_PFG_CFG0_BPS_NINE (0x3 << 28) 35*4882a593Smuzhiyun #define ISC_PFG_CFG0_BPS_TEN (0x2 << 28) 36*4882a593Smuzhiyun #define ISC_PFG_CFG0_BPS_ELEVEN (0x1 << 28) 37*4882a593Smuzhiyun #define ISC_PFG_CFG0_BPS_TWELVE (0x0 << 28) 38*4882a593Smuzhiyun #define ISC_PFE_CFG0_BPS_MASK GENMASK(30, 28) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define ISC_PFE_CFG0_COLEN BIT(12) 41*4882a593Smuzhiyun #define ISC_PFE_CFG0_ROWEN BIT(13) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* ISC Parallel Front End Configuration 1 Register */ 44*4882a593Smuzhiyun #define ISC_PFE_CFG1 0x00000010 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define ISC_PFE_CFG1_COLMIN(v) ((v)) 47*4882a593Smuzhiyun #define ISC_PFE_CFG1_COLMIN_MASK GENMASK(15, 0) 48*4882a593Smuzhiyun #define ISC_PFE_CFG1_COLMAX(v) ((v) << 16) 49*4882a593Smuzhiyun #define ISC_PFE_CFG1_COLMAX_MASK GENMASK(31, 16) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* ISC Parallel Front End Configuration 2 Register */ 52*4882a593Smuzhiyun #define ISC_PFE_CFG2 0x00000014 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define ISC_PFE_CFG2_ROWMIN(v) ((v)) 55*4882a593Smuzhiyun #define ISC_PFE_CFG2_ROWMIN_MASK GENMASK(15, 0) 56*4882a593Smuzhiyun #define ISC_PFE_CFG2_ROWMAX(v) ((v) << 16) 57*4882a593Smuzhiyun #define ISC_PFE_CFG2_ROWMAX_MASK GENMASK(31, 16) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* ISC Clock Enable Register */ 60*4882a593Smuzhiyun #define ISC_CLKEN 0x00000018 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* ISC Clock Disable Register */ 63*4882a593Smuzhiyun #define ISC_CLKDIS 0x0000001c 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* ISC Clock Status Register */ 66*4882a593Smuzhiyun #define ISC_CLKSR 0x00000020 67*4882a593Smuzhiyun #define ISC_CLKSR_SIP BIT(31) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define ISC_CLK(n) BIT(n) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* ISC Clock Configuration Register */ 72*4882a593Smuzhiyun #define ISC_CLKCFG 0x00000024 73*4882a593Smuzhiyun #define ISC_CLKCFG_DIV_SHIFT(n) ((n)*16) 74*4882a593Smuzhiyun #define ISC_CLKCFG_DIV_MASK(n) GENMASK(((n)*16 + 7), (n)*16) 75*4882a593Smuzhiyun #define ISC_CLKCFG_SEL_SHIFT(n) ((n)*16 + 8) 76*4882a593Smuzhiyun #define ISC_CLKCFG_SEL_MASK(n) GENMASK(((n)*17 + 8), ((n)*16 + 8)) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* ISC Interrupt Enable Register */ 79*4882a593Smuzhiyun #define ISC_INTEN 0x00000028 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* ISC Interrupt Disable Register */ 82*4882a593Smuzhiyun #define ISC_INTDIS 0x0000002c 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* ISC Interrupt Mask Register */ 85*4882a593Smuzhiyun #define ISC_INTMASK 0x00000030 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* ISC Interrupt Status Register */ 88*4882a593Smuzhiyun #define ISC_INTSR 0x00000034 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define ISC_INT_DDONE BIT(8) 91*4882a593Smuzhiyun #define ISC_INT_HISDONE BIT(12) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* ISC White Balance Control Register */ 94*4882a593Smuzhiyun #define ISC_WB_CTRL 0x00000058 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* ISC White Balance Configuration Register */ 97*4882a593Smuzhiyun #define ISC_WB_CFG 0x0000005c 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* ISC White Balance Offset for R, GR Register */ 100*4882a593Smuzhiyun #define ISC_WB_O_RGR 0x00000060 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* ISC White Balance Offset for B, GB Register */ 103*4882a593Smuzhiyun #define ISC_WB_O_BGB 0x00000064 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* ISC White Balance Gain for R, GR Register */ 106*4882a593Smuzhiyun #define ISC_WB_G_RGR 0x00000068 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* ISC White Balance Gain for B, GB Register */ 109*4882a593Smuzhiyun #define ISC_WB_G_BGB 0x0000006c 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* ISC Color Filter Array Control Register */ 112*4882a593Smuzhiyun #define ISC_CFA_CTRL 0x00000070 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* ISC Color Filter Array Configuration Register */ 115*4882a593Smuzhiyun #define ISC_CFA_CFG 0x00000074 116*4882a593Smuzhiyun #define ISC_CFA_CFG_EITPOL BIT(4) 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define ISC_BAY_CFG_GRGR 0x0 119*4882a593Smuzhiyun #define ISC_BAY_CFG_RGRG 0x1 120*4882a593Smuzhiyun #define ISC_BAY_CFG_GBGB 0x2 121*4882a593Smuzhiyun #define ISC_BAY_CFG_BGBG 0x3 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* ISC Color Correction Control Register */ 124*4882a593Smuzhiyun #define ISC_CC_CTRL 0x00000078 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* ISC Color Correction RR RG Register */ 127*4882a593Smuzhiyun #define ISC_CC_RR_RG 0x0000007c 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* ISC Color Correction RB OR Register */ 130*4882a593Smuzhiyun #define ISC_CC_RB_OR 0x00000080 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* ISC Color Correction GR GG Register */ 133*4882a593Smuzhiyun #define ISC_CC_GR_GG 0x00000084 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* ISC Color Correction GB OG Register */ 136*4882a593Smuzhiyun #define ISC_CC_GB_OG 0x00000088 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* ISC Color Correction BR BG Register */ 139*4882a593Smuzhiyun #define ISC_CC_BR_BG 0x0000008c 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* ISC Color Correction BB OB Register */ 142*4882a593Smuzhiyun #define ISC_CC_BB_OB 0x00000090 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* ISC Gamma Correction Control Register */ 145*4882a593Smuzhiyun #define ISC_GAM_CTRL 0x00000094 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* ISC_Gamma Correction Blue Entry Register */ 148*4882a593Smuzhiyun #define ISC_GAM_BENTRY 0x00000098 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* ISC_Gamma Correction Green Entry Register */ 151*4882a593Smuzhiyun #define ISC_GAM_GENTRY 0x00000198 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* ISC_Gamma Correction Green Entry Register */ 154*4882a593Smuzhiyun #define ISC_GAM_RENTRY 0x00000298 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* Color Space Conversion Control Register */ 157*4882a593Smuzhiyun #define ISC_CSC_CTRL 0x00000398 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* Color Space Conversion YR YG Register */ 160*4882a593Smuzhiyun #define ISC_CSC_YR_YG 0x0000039c 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* Color Space Conversion YB OY Register */ 163*4882a593Smuzhiyun #define ISC_CSC_YB_OY 0x000003a0 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* Color Space Conversion CBR CBG Register */ 166*4882a593Smuzhiyun #define ISC_CSC_CBR_CBG 0x000003a4 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* Color Space Conversion CBB OCB Register */ 169*4882a593Smuzhiyun #define ISC_CSC_CBB_OCB 0x000003a8 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* Color Space Conversion CRR CRG Register */ 172*4882a593Smuzhiyun #define ISC_CSC_CRR_CRG 0x000003ac 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* Color Space Conversion CRB OCR Register */ 175*4882a593Smuzhiyun #define ISC_CSC_CRB_OCR 0x000003b0 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* Contrast And Brightness Control Register */ 178*4882a593Smuzhiyun #define ISC_CBC_CTRL 0x000003b4 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* Contrast And Brightness Configuration Register */ 181*4882a593Smuzhiyun #define ISC_CBC_CFG 0x000003b8 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* Brightness Register */ 184*4882a593Smuzhiyun #define ISC_CBC_BRIGHT 0x000003bc 185*4882a593Smuzhiyun #define ISC_CBC_BRIGHT_MASK GENMASK(10, 0) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* Contrast Register */ 188*4882a593Smuzhiyun #define ISC_CBC_CONTRAST 0x000003c0 189*4882a593Smuzhiyun #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* Subsampling 4:4:4 to 4:2:2 Control Register */ 192*4882a593Smuzhiyun #define ISC_SUB422_CTRL 0x000003c4 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* Subsampling 4:2:2 to 4:2:0 Control Register */ 195*4882a593Smuzhiyun #define ISC_SUB420_CTRL 0x000003cc 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* Rounding, Limiting and Packing Configuration Register */ 198*4882a593Smuzhiyun #define ISC_RLP_CFG 0x000003d0 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DAT8 0x0 201*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DAT9 0x1 202*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DAT10 0x2 203*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DAT11 0x3 204*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DAT12 0x4 205*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DATY8 0x5 206*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_DATY10 0x6 207*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_ARGB444 0x7 208*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_ARGB555 0x8 209*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_RGB565 0x9 210*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_ARGB32 0xa 211*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_YYCC 0xb 212*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc 213*4882a593Smuzhiyun #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* Histogram Control Register */ 216*4882a593Smuzhiyun #define ISC_HIS_CTRL 0x000003d4 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun #define ISC_HIS_CTRL_EN BIT(0) 219*4882a593Smuzhiyun #define ISC_HIS_CTRL_DIS 0x0 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* Histogram Configuration Register */ 222*4882a593Smuzhiyun #define ISC_HIS_CFG 0x000003d8 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_GR 0x0 225*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_R 0x1 226*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_GB 0x2 227*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_B 0x3 228*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_Y 0x4 229*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_RAW 0x5 230*4882a593Smuzhiyun #define ISC_HIS_CFG_MODE_YCCIR656 0x6 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #define ISC_HIS_CFG_BAYSEL_SHIFT 4 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun #define ISC_HIS_CFG_RAR BIT(8) 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun /* DMA Configuration Register */ 237*4882a593Smuzhiyun #define ISC_DCFG 0x000003e0 238*4882a593Smuzhiyun #define ISC_DCFG_IMODE_PACKED8 0x0 239*4882a593Smuzhiyun #define ISC_DCFG_IMODE_PACKED16 0x1 240*4882a593Smuzhiyun #define ISC_DCFG_IMODE_PACKED32 0x2 241*4882a593Smuzhiyun #define ISC_DCFG_IMODE_YC422SP 0x3 242*4882a593Smuzhiyun #define ISC_DCFG_IMODE_YC422P 0x4 243*4882a593Smuzhiyun #define ISC_DCFG_IMODE_YC420SP 0x5 244*4882a593Smuzhiyun #define ISC_DCFG_IMODE_YC420P 0x6 245*4882a593Smuzhiyun #define ISC_DCFG_IMODE_MASK GENMASK(2, 0) 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #define ISC_DCFG_YMBSIZE_SINGLE (0x0 << 4) 248*4882a593Smuzhiyun #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) 249*4882a593Smuzhiyun #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) 250*4882a593Smuzhiyun #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) 251*4882a593Smuzhiyun #define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) 254*4882a593Smuzhiyun #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) 255*4882a593Smuzhiyun #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) 256*4882a593Smuzhiyun #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) 257*4882a593Smuzhiyun #define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* DMA Control Register */ 260*4882a593Smuzhiyun #define ISC_DCTRL 0x000003e4 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #define ISC_DCTRL_DVIEW_PACKED (0x0 << 1) 263*4882a593Smuzhiyun #define ISC_DCTRL_DVIEW_SEMIPLANAR (0x1 << 1) 264*4882a593Smuzhiyun #define ISC_DCTRL_DVIEW_PLANAR (0x2 << 1) 265*4882a593Smuzhiyun #define ISC_DCTRL_DVIEW_MASK GENMASK(2, 1) 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun #define ISC_DCTRL_IE_IS (0x0 << 4) 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* DMA Descriptor Address Register */ 270*4882a593Smuzhiyun #define ISC_DNDA 0x000003e8 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun /* DMA Address 0 Register */ 273*4882a593Smuzhiyun #define ISC_DAD0 0x000003ec 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* DMA Address 1 Register */ 276*4882a593Smuzhiyun #define ISC_DAD1 0x000003f4 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* DMA Address 2 Register */ 279*4882a593Smuzhiyun #define ISC_DAD2 0x000003fc 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* Histogram Entry */ 282*4882a593Smuzhiyun #define ISC_HIS_ENTRY 0x00000410 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #endif 285