include/asm/immap_5445x.h

76 	u16 sbfsr;		/* Serial Boot Facility Status Register */
78 	u16 sbfcr;		/* Serial Boot Facility Control Register */
90 	u16 ccr;		/* Chip Configuration Register (256 TEPBGA, Read-only) */
93 	u16 cir;		/* Chip Identification Register (Read-only) */
95 	u16 misccr;		/* Miscellaneous Control Register */
96 	u16 cdr;		/* Clock Divider Register */
97 	u16 uocsr;		/* USB On-the-Go Controller Status Register */
102 	u8 podr_fec0h;		/* FEC0 High Port Output Data Register */
103 	u8 podr_fec0l;		/* FEC0 Low Port Output Data Register */
104 	u8 podr_ssi;		/* SSI Port Output Data Register */
105 	u8 podr_fbctl;		/* Flexbus Control Port Output Data Register */
106 	u8 podr_be;		/* Flexbus Byte Enable Port Output Data Register */
107 	u8 podr_cs;		/* Flexbus Chip-Select Port Output Data Register */
108 	u8 podr_dma;		/* DMA Port Output Data Register */
109 	u8 podr_feci2c;		/* FEC1 / I2C Port Output Data Register */
111 	u8 podr_uart;		/* UART Port Output Data Register */
112 	u8 podr_dspi;		/* DSPI Port Output Data Register */
113 	u8 podr_timer;		/* Timer Port Output Data Register */
114 	u8 podr_pci;		/* PCI Port Output Data Register */
115 	u8 podr_usb;		/* USB Port Output Data Register */
116 	u8 podr_atah;		/* ATA High Port Output Data Register */
117 	u8 podr_atal;		/* ATA Low Port Output Data Register */
118 	u8 podr_fec1h;		/* FEC1 High Port Output Data Register */
119 	u8 podr_fec1l;		/* FEC1 Low Port Output Data Register */
121 	u8 podr_fbadh;		/* Flexbus AD High Port Output Data Register */
122 	u8 podr_fbadmh;		/* Flexbus AD Med-High Port Output Data Register */
123 	u8 podr_fbadml;		/* Flexbus AD Med-Low Port Output Data Register */
124 	u8 podr_fbadl;		/* Flexbus AD Low Port Output Data Register */
125 	u8 pddr_fec0h;		/* FEC0 High Port Data Direction Register */
126 	u8 pddr_fec0l;		/* FEC0 Low Port Data Direction Register */
127 	u8 pddr_ssi;		/* SSI Port Data Direction Register */
128 	u8 pddr_fbctl;		/* Flexbus Control Port Data Direction Register */
129 	u8 pddr_be;		/* Flexbus Byte Enable Port Data Direction Register */
130 	u8 pddr_cs;		/* Flexbus Chip-Select Port Data Direction Register */
131 	u8 pddr_dma;		/* DMA Port Data Direction Register */
132 	u8 pddr_feci2c;		/* FEC1 / I2C Port Data Direction Register */
134 	u8 pddr_uart;		/* UART Port Data Direction Register */
135 	u8 pddr_dspi;		/* DSPI Port Data Direction Register */
136 	u8 pddr_timer;		/* Timer Port Data Direction Register */
137 	u8 pddr_pci;		/* PCI Port Data Direction Register */
138 	u8 pddr_usb;		/* USB Port Data Direction Register */
139 	u8 pddr_atah;		/* ATA High Port Data Direction Register */
140 	u8 pddr_atal;		/* ATA Low Port Data Direction Register */
141 	u8 pddr_fec1h;		/* FEC1 High Port Data Direction Register */
142 	u8 pddr_fec1l;		/* FEC1 Low Port Data Direction Register */
144 	u8 pddr_fbadh;		/* Flexbus AD High Port Data Direction Register */
145 	u8 pddr_fbadmh;		/* Flexbus AD Med-High Port Data Direction Register */
146 	u8 pddr_fbadml;		/* Flexbus AD Med-Low Port Data Direction Register */
147 	u8 pddr_fbadl;		/* Flexbus AD Low Port Data Direction Register */
148 	u8 ppdsdr_fec0h;	/* FEC0 High Port Pin Data/Set Data Register */
149 	u8 ppdsdr_fec0l;	/* FEC0 Low Port Clear Output Data Register */
150 	u8 ppdsdr_ssi;		/* SSI Port Pin Data/Set Data Register */
151 	u8 ppdsdr_fbctl;	/* Flexbus Control Port Pin Data/Set Data Register */
152 	u8 ppdsdr_be;		/* Flexbus Byte Enable Port Pin Data/Set Data Register */
153 	u8 ppdsdr_cs;		/* Flexbus Chip-Select Port Pin Data/Set Data Register */
154 	u8 ppdsdr_dma;		/* DMA Port Pin Data/Set Data Register */
155 	u8 ppdsdr_feci2c;	/* FEC1 / I2C Port Pin Data/Set Data Register */
157 	u8 ppdsdr_uart;		/* UART Port Pin Data/Set Data Register */
158 	u8 ppdsdr_dspi;		/* DSPI Port Pin Data/Set Data Register */
159 	u8 ppdsdr_timer;	/* FTimer Port Pin Data/Set Data Register */
160 	u8 ppdsdr_pci;		/* PCI Port Pin Data/Set Data Register */
161 	u8 ppdsdr_usb;		/* USB Port Pin Data/Set Data Register */
162 	u8 ppdsdr_atah;		/* ATA High Port Pin Data/Set Data Register */
163 	u8 ppdsdr_atal;		/* ATA Low Port Pin Data/Set Data Register */
164 	u8 ppdsdr_fec1h;	/* FEC1 High Port Pin Data/Set Data Register */
165 	u8 ppdsdr_fec1l;	/* FEC1 Low Port Pin Data/Set Data Register */
167 	u8 ppdsdr_fbadh;	/* Flexbus AD High Port Pin Data/Set Data Register */
168 	u8 ppdsdr_fbadmh;	/* Flexbus AD Med-High Port Pin Data/Set Data Register */
169 	u8 ppdsdr_fbadml;	/* Flexbus AD Med-Low Port Pin Data/Set Data Register */
170 	u8 ppdsdr_fbadl;	/* Flexbus AD Low Port Pin Data/Set Data Register */
171 	u8 pclrr_fec0h;		/* FEC0 High Port Clear Output Data Register */
172 	u8 pclrr_fec0l;		/* FEC0 Low Port Pin Data/Set Data Register */
173 	u8 pclrr_ssi;		/* SSI Port Clear Output Data Register */
174 	u8 pclrr_fbctl;		/* Flexbus Control Port Clear Output Data Register */
175 	u8 pclrr_be;		/* Flexbus Byte Enable Port Clear Output Data Register */
176 	u8 pclrr_cs;		/* Flexbus Chip-Select Port Clear Output Data Register */
177 	u8 pclrr_dma;		/* DMA Port Clear Output Data Register */
178 	u8 pclrr_feci2c;	/* FEC1 / I2C Port Clear Output Data Register */
180 	u8 pclrr_uart;		/* UART Port Clear Output Data Register */
181 	u8 pclrr_dspi;		/* DSPI Port Clear Output Data Register */
182 	u8 pclrr_timer;		/* Timer Port Clear Output Data Register */
183 	u8 pclrr_pci;		/* PCI Port Clear Output Data Register */
184 	u8 pclrr_usb;		/* USB Port Clear Output Data Register */
185 	u8 pclrr_atah;		/* ATA High Port Clear Output Data Register */
186 	u8 pclrr_atal;		/* ATA Low Port Clear Output Data Register */
187 	u8 pclrr_fec1h;		/* FEC1 High Port Clear Output Data Register */
188 	u8 pclrr_fec1l;		/* FEC1 Low Port Clear Output Data Register */
190 	u8 pclrr_fbadh;		/* Flexbus AD High Port Clear Output Data Register */
191 	u8 pclrr_fbadmh;	/* Flexbus AD Med-High Port Clear Output Data Register */
192 	u8 pclrr_fbadml;	/* Flexbus AD Med-Low Port Clear Output Data Register */
193 	u8 pclrr_fbadl;		/* Flexbus AD Low Port Clear Output Data Register */
194 	u8 par_fec;		/* FEC Pin Assignment Register */
195 	u8 par_dma;		/* DMA Pin Assignment Register */
196 	u8 par_fbctl;		/* Flexbus Control Pin Assignment Register */
197 	u8 par_dspi;		/* DSPI Pin Assignment Register */
198 	u8 par_be;		/* Flexbus Byte-Enable Pin Assignment Register */
199 	u8 par_cs;		/* Flexbus Chip-Select Pin Assignment Register */
200 	u8 par_timer;		/* Time Pin Assignment Register */
201 	u8 par_usb;		/* USB Pin Assignment Register */
203 	u8 par_uart;		/* UART Pin Assignment Register */
204 	u16 par_feci2c;		/* FEC / I2C Pin Assignment Register */
205 	u16 par_ssi;		/* SSI Pin Assignment Register */
206 	u16 par_ata;		/* ATA Pin Assignment Register */
207 	u8 par_irq;		/* IRQ Pin Assignment Register */
209 	u16 par_pci;		/* PCI Pin Assignment Register */
210 	u8 mscr_sdram;		/* SDRAM Mode Select Control Register */
211 	u8 mscr_pci;		/* PCI Mode Select Control Register */
213 	u8 dscr_i2c;		/* I2C Drive Strength Control Register */
214 	u8 dscr_flexbus;	/* FLEXBUS Drive Strength Control Register */
215 	u8 dscr_fec;		/* FEC Drive Strength Control Register */
216 	u8 dscr_uart;		/* UART Drive Strength Control Register */
217 	u8 dscr_dspi;		/* DSPI Drive Strength Control Register */
218 	u8 dscr_timer;		/* TIMER Drive Strength Control Register */
219 	u8 dscr_ssi;		/* SSI Drive Strength Control Register */
220 	u8 dscr_dma;		/* DMA Drive Strength Control Register */
221 	u8 dscr_debug;		/* DEBUG Drive Strength Control Register */
222 	u8 dscr_reset;		/* RESET Drive Strength Control Register */
223 	u8 dscr_irq;		/* IRQ Drive Strength Control Register */
224 	u8 dscr_usb;		/* USB Drive Strength Control Register */
225 	u8 dscr_ata;		/* ATA Drive Strength Control Register */
230 	u32 sdmr;		/* SDRAM Mode/Extended Mode Register */
231 	u32 sdcr;		/* SDRAM Control Register */
232 	u32 sdcfg1;		/* SDRAM Configuration Register 1 */
233 	u32 sdcfg2;		/* SDRAM Chip Select Register */
235 	u32 sdcs0;		/* SDRAM Mode/Extended Mode Register */
236 	u32 sdcs1;		/* SDRAM Mode/Extended Mode Register */
241 	u32 pcr;		/* PLL Control Register */
242 	u32 psr;		/* PLL Status Register */
246 	u32 idr;		/* 0x00 Device Id / Vendor Id Register */
247 	u32 scr;		/* 0x04 Status / command Register */
248 	u32 ccrir;		/* 0x08 Class Code / Revision Id Register */
249 	u32 cr1;		/* 0x0c Configuration 1 Register */
250 	u32 bar0;		/* 0x10 Base address register 0 Register */
251 	u32 bar1;		/* 0x14 Base address register 1 Register */
252 	u32 bar2;		/* 0x18 Base address register 2 Register */
253 	u32 bar3;		/* 0x1c Base address register 3 Register */
254 	u32 bar4;		/* 0x20 Base address register 4 Register */
255 	u32 bar5;		/* 0x24 Base address register 5 Register */
256 	u32 ccpr;		/* 0x28 Cardbus CIS Pointer Register */
257 	u32 sid;		/* 0x2c Subsystem ID / Subsystem Vendor ID Register */
258 	u32 erbar;		/* 0x30 Expansion ROM Base Address Register */
259 	u32 cpr;		/* 0x34 Capabilities Pointer Register */
261 	u32 cr2;		/* 0x3c Configuration Register 2 */
265 	u32 gscr;		/* 0x60 Global Status / Control Register */
266 	u32 tbatr0a;		/* 0x64 Target Base Address Translation Register  0 */
267 	u32 tbatr1a;		/* 0x68 Target Base Address Translation Register  1 */
268 	u32 tcr1;		/* 0x6c Target Control 1 Register */
273 	u32 iwcr;		/* 0x80 Initiator Window Configuration Register */
274 	u32 icr;		/* 0x84 Initiator Control Register */
275 	u32 isr;		/* 0x88 Initiator Status Register */
276 	u32 tcr2;		/* 0x8c Target Control 2 Register */
277 	u32 tbatr0;		/* 0x90 Target Base Address Translation Register  0 */
278 	u32 tbatr1;		/* 0x94 Target Base Address Translation Register  1 */
279 	u32 tbatr2;		/* 0x98 Target Base Address Translation Register  2 */
280 	u32 tbatr3;		/* 0x9c Target Base Address Translation Register  3 */
281 	u32 tbatr4;		/* 0xa0 Target Base Address Translation Register  4 */
282 	u32 tbatr5;		/* 0xa4 Target Base Address Translation Register  5 */
283 	u32 intr;		/* 0xa8 Interrupt Register */
285 	u32 car;		/* 0xf8 Configuration Address Register */
291 		u32 acr;	/* Arbiter Control Register */
292 		u32 asr;	/* Arbiter Status Register */
296 /* Register read/write struct */
298 	u32 mpr;		/* 0x00 Master Privilege Register */
300 	u32 pacra;		/* 0x20 Peripheral Access Control Register A */
301 	u32 pacrb;		/* 0x24 Peripheral Access Control Register B */
302 	u32 pacrc;		/* 0x28 Peripheral Access Control Register C */
303 	u32 pacrd;		/* 0x2C Peripheral Access Control Register D */
305 	u32 pacre;		/* 0x40 Peripheral Access Control Register E */
306 	u32 pacrf;		/* 0x44 Peripheral Access Control Register F */
307 	u32 pacrg;		/* 0x48 Peripheral Access Control Register G */