include/linux/immap_qe.h

41 	u32 iadd;		/* I-RAM Address Register */
42 	u32 idata;		/* I-RAM Data Register    */
73 	u32 cecr;		/* QE command register */
74 	u32 ceccr;		/* QE controller configuration register */
75 	u32 cecdr;		/* QE command data register */
77 	u16 ceter;		/* QE timer event register */
79 	u16 cetmr;		/* QE timers mask register */
80 	u32 cetscr;		/* QE time-stamp timer control register */
81 	u32 cetsr1;		/* QE time-stamp register 1 */
82 	u32 cetsr2;		/* QE time-stamp register 2 */
84 	u32 cevter;		/* QE virtual tasks event register */
85 	u32 cevtmr;		/* QE virtual tasks mask register */
86 	u16 cercr;		/* QE RAM control register */
89 	u16 ceexe1;		/* QE external request 1 event register */
91 	u16 ceexm1;		/* QE external request 1 mask register */
93 	u16 ceexe2;		/* QE external request 2 event register */
95 	u16 ceexm2;		/* QE external request 2 mask register */
97 	u16 ceexe3;		/* QE external request 3 event register */
99 	u16 ceexm3;		/* QE external request 3 mask register */
101 	u16 ceexe4;		/* QE external request 4 event register */
103 	u16 ceexm4;		/* QE external request 4 mask register */
110 	u32 cmxgcr;		/* CMX general clock route register    */
111 	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
112 	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
113 	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
114 	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
115 	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
116 	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
117 	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
118 	u32 cmxupcr;		/* CMX UPC clock route register        */
124 	u8 gtcfr1;		/* Timer 1 2 global configuration register */
126 	u8 gtcfr2;		/* Timer 3 4 global configuration register */
128 	u16 gtmdr1;		/* Timer 1 mode register */
129 	u16 gtmdr2;		/* Timer 2 mode register */
130 	u16 gtrfr1;		/* Timer 1 reference register */
131 	u16 gtrfr2;		/* Timer 2 reference register */
132 	u16 gtcpr1;		/* Timer 1 capture register */
133 	u16 gtcpr2;		/* Timer 2 capture register */
136 	u16 gtmdr3;		/* Timer 3 mode register */
137 	u16 gtmdr4;		/* Timer 4 mode register */
138 	u16 gtrfr3;		/* Timer 3 reference register */
139 	u16 gtrfr4;		/* Timer 4 reference register */
140 	u16 gtcpr3;		/* Timer 3 capture register */
141 	u16 gtcpr4;		/* Timer 4 capture register */
144 	u16 gtevr1;		/* Timer 1 event register */
145 	u16 gtevr2;		/* Timer 2 event register */
146 	u16 gtevr3;		/* Timer 3 event register */
147 	u16 gtevr4;		/* Timer 4 event register */
148 	u16 gtps;		/* Timer 1 prescale register */
154 	u32 brgc1;		/* BRG1 configuration register  */
155 	u32 brgc2;		/* BRG2 configuration register  */
156 	u32 brgc3;		/* BRG3 configuration register  */
157 	u32 brgc4;		/* BRG4 configuration register  */
158 	u32 brgc5;		/* BRG5 configuration register  */
159 	u32 brgc6;		/* BRG6 configuration register  */
160 	u32 brgc7;		/* BRG7 configuration register  */
161 	u32 brgc8;		/* BRG8 configuration register  */
162 	u32 brgc9;		/* BRG9 configuration register  */
163 	u32 brgc10;		/* BRG10 configuration register */
164 	u32 brgc11;		/* BRG11 configuration register */
165 	u32 brgc12;		/* BRG12 configuration register */
166 	u32 brgc13;		/* BRG13 configuration register */
167 	u32 brgc14;		/* BRG14 configuration register */
168 	u32 brgc15;		/* BRG15 configuration register */
169 	u32 brgc16;		/* BRG16 configuration register */
176 	u32 spmode;		/* SPI mode register */
178 	u8 spie;		/* SPI event register */
181 	u8 spim;		/* SPI mask register */
184 	u8 spcom;		/* SPI command register  */
186 	u32 spitd;		/* SPI transmit data register (cpu mode) */
187 	u32 spird;		/* SPI receive data register (cpu mode) */
193 	u16 siamr1;		/* SI1 TDMA mode register */
194 	u16 sibmr1;		/* SI1 TDMB mode register */
195 	u16 sicmr1;		/* SI1 TDMC mode register */
196 	u16 sidmr1;		/* SI1 TDMD mode register */
197 	u8 siglmr1_h;		/* SI1 global mode register high */
199 	u8 sicmdr1_h;		/* SI1 command register high */
201 	u8 sistr1_h;		/* SI1 status register high */
203 	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
213 	u16 siemr1;		/* SI1 TDME mode register 16 bits */
214 	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
215 	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
216 	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
217 	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
219 	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
221 	u8 sistr1_l;		/* SI1 status register low 8 bits */
223 	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
233 	u32 siml1;		/* SI1 multiframe limit register */
234 	u8 siedm1;		/* SI1 extended diagnostic mode register */
269 	u32 mcce;		/* MCC event register */
270 	u32 mccm;		/* MCC mask register */
271 	u32 mccf;		/* MCC configuration register */
272 	u32 merl;		/* MCC emergency request level register */
278 	u32 gumr_l;		/* UCCx general mode register (low) */
279 	u32 gumr_h;		/* UCCx general mode register (high) */
280 	u16 upsmr;		/* UCCx protocol-specific mode register */
282 	u16 utodr;		/* UCCx transmit on demand register */
283 	u16 udsr;		/* UCCx data synchronization register */
284 	u16 ucce;		/* UCCx event register */
286 	u16 uccm;		/* UCCx mask register */
288 	u8 uccs;		/* UCCx status register */
291 	u8 guemr;		/* UCC general extended mode register */
375 	u32 scar;		/* Statistics carry register */
376 	u32 scam;		/* Statistics caryy mask register */
382 	u32 gumr;		/* UCCx general mode register */
383 	u32 upsmr;		/* UCCx protocol-specific mode register  */
384 	u16 utodr;		/* UCCx transmit on demand register  */
386 	u16 udsr;		/* UCCx data synchronization register  */
388 	u32 ucce;		/* UCCx event register */
389 	u32 uccm;		/* UCCx mask register.  */
390 	u8 uccs;		/* UCCx status register */
407 	u32 urtry;		/* UCC retry counter register */
409 	u8 guemr;		/* UCC general extended mode register */
431 	u32 upgcr;		/* UTOPIA/POS general configuration register */
433 	u32 uphec;		/* ATM HEC register */
478 	u32 uper1;		/* Device 1 port enable register */
479 	u32 uper2;		/* Device 2 port enable register */
480 	u32 uper3;		/* Device 3 port enable register */
481 	u32 uper4;		/* Device 4 port enable register */
487 	u32 sdsr;		/* Serial DMA status register */
488 	u32 sdmr;		/* Serial DMA mode register */
489 	u32 sdtr1;		/* SDMA system bus threshold register */
490 	u32 sdtr2;		/* SDMA secondary bus threshold register */
491 	u32 sdhy1;		/* SDMA system bus hysteresis register */
492 	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
493 	u32 sdta1;		/* SDMA system bus address register */
494 	u32 sdta2;		/* SDMA secondary bus address register */
495 	u32 sdtm1;		/* SDMA system bus MSNUM register */
496 	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
498 	u32 sdaqr;		/* SDMA address bus qualify register */
499 	u32 sdaqmr;		/* SDMA address bus qualify mask register */
501 	u32 sdwbcr;		/* SDMA CAM entries base register */
507 	u32 bpdcr;		/* Breakpoint debug command register */
508 	u32 bpdsr;		/* Breakpoint debug status register */
509 	u32 bpdmr;		/* Breakpoint debug mask register */
510 	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
511 	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
513 	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
514 	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
516 	u32 bprmir;		/* Breakpoint request mode immediate register */
517 	u32 bprmsr;		/* Breakpoint request mode serial register */
518 	u32 bpemr;		/* Breakpoint exit mode register */
552 	u32 eccr;		/* Exception control configuration register */