1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * MCF5445x Internal Memory Map 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5*4882a593Smuzhiyun * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __IMMAP_5445X__ 11*4882a593Smuzhiyun #define __IMMAP_5445X__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Module Base Addresses */ 14*4882a593Smuzhiyun #define MMAP_SCM1 0xFC000000 15*4882a593Smuzhiyun #define MMAP_XBS 0xFC004000 16*4882a593Smuzhiyun #define MMAP_FBCS 0xFC008000 17*4882a593Smuzhiyun #define MMAP_FEC0 0xFC030000 18*4882a593Smuzhiyun #define MMAP_FEC1 0xFC034000 19*4882a593Smuzhiyun #define MMAP_RTC 0xFC03C000 20*4882a593Smuzhiyun #define MMAP_SCM2 0xFC040000 21*4882a593Smuzhiyun #define MMAP_EDMA 0xFC044000 22*4882a593Smuzhiyun #define MMAP_INTC0 0xFC048000 23*4882a593Smuzhiyun #define MMAP_INTC1 0xFC04C000 24*4882a593Smuzhiyun #define MMAP_IACK 0xFC054000 25*4882a593Smuzhiyun #define MMAP_I2C 0xFC058000 26*4882a593Smuzhiyun #define MMAP_DSPI 0xFC05C000 27*4882a593Smuzhiyun #define MMAP_UART0 0xFC060000 28*4882a593Smuzhiyun #define MMAP_UART1 0xFC064000 29*4882a593Smuzhiyun #define MMAP_UART2 0xFC068000 30*4882a593Smuzhiyun #define MMAP_DTMR0 0xFC070000 31*4882a593Smuzhiyun #define MMAP_DTMR1 0xFC074000 32*4882a593Smuzhiyun #define MMAP_DTMR2 0xFC078000 33*4882a593Smuzhiyun #define MMAP_DTMR3 0xFC07C000 34*4882a593Smuzhiyun #define MMAP_PIT0 0xFC080000 35*4882a593Smuzhiyun #define MMAP_PIT1 0xFC084000 36*4882a593Smuzhiyun #define MMAP_PIT2 0xFC088000 37*4882a593Smuzhiyun #define MMAP_PIT3 0xFC08C000 38*4882a593Smuzhiyun #define MMAP_EPORT 0xFC094000 39*4882a593Smuzhiyun #define MMAP_WTM 0xFC098000 40*4882a593Smuzhiyun #define MMAP_SBF 0xFC0A0000 41*4882a593Smuzhiyun #define MMAP_RCM 0xFC0A0000 42*4882a593Smuzhiyun #define MMAP_CCM 0xFC0A0000 43*4882a593Smuzhiyun #define MMAP_GPIO 0xFC0A4000 44*4882a593Smuzhiyun #define MMAP_PCI 0xFC0A8000 45*4882a593Smuzhiyun #define MMAP_PCIARB 0xFC0AC000 46*4882a593Smuzhiyun #define MMAP_RNG 0xFC0B4000 47*4882a593Smuzhiyun #define MMAP_SDRAM 0xFC0B8000 48*4882a593Smuzhiyun #define MMAP_SSI 0xFC0BC000 49*4882a593Smuzhiyun #define MMAP_PLL 0xFC0C4000 50*4882a593Smuzhiyun #define MMAP_ATA 0x90000000 51*4882a593Smuzhiyun #define MMAP_USBHW 0xFC0B0000 52*4882a593Smuzhiyun #define MMAP_USBCAPS 0xFC0B0100 53*4882a593Smuzhiyun #define MMAP_USBEHCI 0xFC0B0140 54*4882a593Smuzhiyun #define MMAP_USBOTG 0xFC0B01A0 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #include <asm/coldfire/ata.h> 57*4882a593Smuzhiyun #include <asm/coldfire/crossbar.h> 58*4882a593Smuzhiyun #include <asm/coldfire/dspi.h> 59*4882a593Smuzhiyun #include <asm/coldfire/edma.h> 60*4882a593Smuzhiyun #include <asm/coldfire/eport.h> 61*4882a593Smuzhiyun #include <asm/coldfire/flexbus.h> 62*4882a593Smuzhiyun #include <asm/coldfire/intctrl.h> 63*4882a593Smuzhiyun #include <asm/coldfire/ssi.h> 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Watchdog Timer Modules (WTM) */ 66*4882a593Smuzhiyun typedef struct wtm { 67*4882a593Smuzhiyun u16 wcr; 68*4882a593Smuzhiyun u16 wmr; 69*4882a593Smuzhiyun u16 wcntr; 70*4882a593Smuzhiyun u16 wsr; 71*4882a593Smuzhiyun } wtm_t; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Serial Boot Facility (SBF) */ 74*4882a593Smuzhiyun typedef struct sbf { 75*4882a593Smuzhiyun u8 resv0[0x18]; 76*4882a593Smuzhiyun u16 sbfsr; /* Serial Boot Facility Status Register */ 77*4882a593Smuzhiyun u8 resv1[0x6]; 78*4882a593Smuzhiyun u16 sbfcr; /* Serial Boot Facility Control Register */ 79*4882a593Smuzhiyun } sbf_t; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Reset Controller Module (RCM) */ 82*4882a593Smuzhiyun typedef struct rcm { 83*4882a593Smuzhiyun u8 rcr; 84*4882a593Smuzhiyun u8 rsr; 85*4882a593Smuzhiyun } rcm_t; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Chip Configuration Module (CCM) */ 88*4882a593Smuzhiyun typedef struct ccm { 89*4882a593Smuzhiyun u8 ccm_resv0[0x4]; 90*4882a593Smuzhiyun u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ 91*4882a593Smuzhiyun u8 resv1[0x2]; 92*4882a593Smuzhiyun u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ 93*4882a593Smuzhiyun u16 cir; /* Chip Identification Register (Read-only) */ 94*4882a593Smuzhiyun u8 resv2[0x4]; 95*4882a593Smuzhiyun u16 misccr; /* Miscellaneous Control Register */ 96*4882a593Smuzhiyun u16 cdr; /* Clock Divider Register */ 97*4882a593Smuzhiyun u16 uocsr; /* USB On-the-Go Controller Status Register */ 98*4882a593Smuzhiyun } ccm_t; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* General Purpose I/O Module (GPIO) */ 101*4882a593Smuzhiyun typedef struct gpio { 102*4882a593Smuzhiyun u8 podr_fec0h; /* FEC0 High Port Output Data Register */ 103*4882a593Smuzhiyun u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ 104*4882a593Smuzhiyun u8 podr_ssi; /* SSI Port Output Data Register */ 105*4882a593Smuzhiyun u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ 106*4882a593Smuzhiyun u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ 107*4882a593Smuzhiyun u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ 108*4882a593Smuzhiyun u8 podr_dma; /* DMA Port Output Data Register */ 109*4882a593Smuzhiyun u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ 110*4882a593Smuzhiyun u8 resv0[0x1]; 111*4882a593Smuzhiyun u8 podr_uart; /* UART Port Output Data Register */ 112*4882a593Smuzhiyun u8 podr_dspi; /* DSPI Port Output Data Register */ 113*4882a593Smuzhiyun u8 podr_timer; /* Timer Port Output Data Register */ 114*4882a593Smuzhiyun u8 podr_pci; /* PCI Port Output Data Register */ 115*4882a593Smuzhiyun u8 podr_usb; /* USB Port Output Data Register */ 116*4882a593Smuzhiyun u8 podr_atah; /* ATA High Port Output Data Register */ 117*4882a593Smuzhiyun u8 podr_atal; /* ATA Low Port Output Data Register */ 118*4882a593Smuzhiyun u8 podr_fec1h; /* FEC1 High Port Output Data Register */ 119*4882a593Smuzhiyun u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ 120*4882a593Smuzhiyun u8 resv1[0x2]; 121*4882a593Smuzhiyun u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ 122*4882a593Smuzhiyun u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ 123*4882a593Smuzhiyun u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ 124*4882a593Smuzhiyun u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ 125*4882a593Smuzhiyun u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ 126*4882a593Smuzhiyun u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ 127*4882a593Smuzhiyun u8 pddr_ssi; /* SSI Port Data Direction Register */ 128*4882a593Smuzhiyun u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ 129*4882a593Smuzhiyun u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ 130*4882a593Smuzhiyun u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ 131*4882a593Smuzhiyun u8 pddr_dma; /* DMA Port Data Direction Register */ 132*4882a593Smuzhiyun u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ 133*4882a593Smuzhiyun u8 resv2[0x1]; 134*4882a593Smuzhiyun u8 pddr_uart; /* UART Port Data Direction Register */ 135*4882a593Smuzhiyun u8 pddr_dspi; /* DSPI Port Data Direction Register */ 136*4882a593Smuzhiyun u8 pddr_timer; /* Timer Port Data Direction Register */ 137*4882a593Smuzhiyun u8 pddr_pci; /* PCI Port Data Direction Register */ 138*4882a593Smuzhiyun u8 pddr_usb; /* USB Port Data Direction Register */ 139*4882a593Smuzhiyun u8 pddr_atah; /* ATA High Port Data Direction Register */ 140*4882a593Smuzhiyun u8 pddr_atal; /* ATA Low Port Data Direction Register */ 141*4882a593Smuzhiyun u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ 142*4882a593Smuzhiyun u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ 143*4882a593Smuzhiyun u8 resv3[0x2]; 144*4882a593Smuzhiyun u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ 145*4882a593Smuzhiyun u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ 146*4882a593Smuzhiyun u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ 147*4882a593Smuzhiyun u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ 148*4882a593Smuzhiyun u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ 149*4882a593Smuzhiyun u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ 150*4882a593Smuzhiyun u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ 151*4882a593Smuzhiyun u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ 152*4882a593Smuzhiyun u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ 153*4882a593Smuzhiyun u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ 154*4882a593Smuzhiyun u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ 155*4882a593Smuzhiyun u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ 156*4882a593Smuzhiyun u8 resv4[0x1]; 157*4882a593Smuzhiyun u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ 158*4882a593Smuzhiyun u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ 159*4882a593Smuzhiyun u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ 160*4882a593Smuzhiyun u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ 161*4882a593Smuzhiyun u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ 162*4882a593Smuzhiyun u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ 163*4882a593Smuzhiyun u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ 164*4882a593Smuzhiyun u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ 165*4882a593Smuzhiyun u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ 166*4882a593Smuzhiyun u8 resv5[0x2]; 167*4882a593Smuzhiyun u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ 168*4882a593Smuzhiyun u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ 169*4882a593Smuzhiyun u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ 170*4882a593Smuzhiyun u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ 171*4882a593Smuzhiyun u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ 172*4882a593Smuzhiyun u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ 173*4882a593Smuzhiyun u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ 174*4882a593Smuzhiyun u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ 175*4882a593Smuzhiyun u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ 176*4882a593Smuzhiyun u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ 177*4882a593Smuzhiyun u8 pclrr_dma; /* DMA Port Clear Output Data Register */ 178*4882a593Smuzhiyun u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ 179*4882a593Smuzhiyun u8 resv6[0x1]; 180*4882a593Smuzhiyun u8 pclrr_uart; /* UART Port Clear Output Data Register */ 181*4882a593Smuzhiyun u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ 182*4882a593Smuzhiyun u8 pclrr_timer; /* Timer Port Clear Output Data Register */ 183*4882a593Smuzhiyun u8 pclrr_pci; /* PCI Port Clear Output Data Register */ 184*4882a593Smuzhiyun u8 pclrr_usb; /* USB Port Clear Output Data Register */ 185*4882a593Smuzhiyun u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ 186*4882a593Smuzhiyun u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ 187*4882a593Smuzhiyun u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ 188*4882a593Smuzhiyun u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ 189*4882a593Smuzhiyun u8 resv7[0x2]; 190*4882a593Smuzhiyun u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ 191*4882a593Smuzhiyun u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ 192*4882a593Smuzhiyun u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ 193*4882a593Smuzhiyun u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ 194*4882a593Smuzhiyun u8 par_fec; /* FEC Pin Assignment Register */ 195*4882a593Smuzhiyun u8 par_dma; /* DMA Pin Assignment Register */ 196*4882a593Smuzhiyun u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ 197*4882a593Smuzhiyun u8 par_dspi; /* DSPI Pin Assignment Register */ 198*4882a593Smuzhiyun u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ 199*4882a593Smuzhiyun u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ 200*4882a593Smuzhiyun u8 par_timer; /* Time Pin Assignment Register */ 201*4882a593Smuzhiyun u8 par_usb; /* USB Pin Assignment Register */ 202*4882a593Smuzhiyun u8 resv8[0x1]; 203*4882a593Smuzhiyun u8 par_uart; /* UART Pin Assignment Register */ 204*4882a593Smuzhiyun u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ 205*4882a593Smuzhiyun u16 par_ssi; /* SSI Pin Assignment Register */ 206*4882a593Smuzhiyun u16 par_ata; /* ATA Pin Assignment Register */ 207*4882a593Smuzhiyun u8 par_irq; /* IRQ Pin Assignment Register */ 208*4882a593Smuzhiyun u8 resv9[0x1]; 209*4882a593Smuzhiyun u16 par_pci; /* PCI Pin Assignment Register */ 210*4882a593Smuzhiyun u8 mscr_sdram; /* SDRAM Mode Select Control Register */ 211*4882a593Smuzhiyun u8 mscr_pci; /* PCI Mode Select Control Register */ 212*4882a593Smuzhiyun u8 resv10[0x2]; 213*4882a593Smuzhiyun u8 dscr_i2c; /* I2C Drive Strength Control Register */ 214*4882a593Smuzhiyun u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ 215*4882a593Smuzhiyun u8 dscr_fec; /* FEC Drive Strength Control Register */ 216*4882a593Smuzhiyun u8 dscr_uart; /* UART Drive Strength Control Register */ 217*4882a593Smuzhiyun u8 dscr_dspi; /* DSPI Drive Strength Control Register */ 218*4882a593Smuzhiyun u8 dscr_timer; /* TIMER Drive Strength Control Register */ 219*4882a593Smuzhiyun u8 dscr_ssi; /* SSI Drive Strength Control Register */ 220*4882a593Smuzhiyun u8 dscr_dma; /* DMA Drive Strength Control Register */ 221*4882a593Smuzhiyun u8 dscr_debug; /* DEBUG Drive Strength Control Register */ 222*4882a593Smuzhiyun u8 dscr_reset; /* RESET Drive Strength Control Register */ 223*4882a593Smuzhiyun u8 dscr_irq; /* IRQ Drive Strength Control Register */ 224*4882a593Smuzhiyun u8 dscr_usb; /* USB Drive Strength Control Register */ 225*4882a593Smuzhiyun u8 dscr_ata; /* ATA Drive Strength Control Register */ 226*4882a593Smuzhiyun } gpio_t; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* SDRAM Controller (SDRAMC) */ 229*4882a593Smuzhiyun typedef struct sdramc { 230*4882a593Smuzhiyun u32 sdmr; /* SDRAM Mode/Extended Mode Register */ 231*4882a593Smuzhiyun u32 sdcr; /* SDRAM Control Register */ 232*4882a593Smuzhiyun u32 sdcfg1; /* SDRAM Configuration Register 1 */ 233*4882a593Smuzhiyun u32 sdcfg2; /* SDRAM Chip Select Register */ 234*4882a593Smuzhiyun u8 resv0[0x100]; 235*4882a593Smuzhiyun u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ 236*4882a593Smuzhiyun u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ 237*4882a593Smuzhiyun } sdramc_t; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun /* Phase Locked Loop (PLL) */ 240*4882a593Smuzhiyun typedef struct pll { 241*4882a593Smuzhiyun u32 pcr; /* PLL Control Register */ 242*4882a593Smuzhiyun u32 psr; /* PLL Status Register */ 243*4882a593Smuzhiyun } pll_t; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun typedef struct pci { 246*4882a593Smuzhiyun u32 idr; /* 0x00 Device Id / Vendor Id Register */ 247*4882a593Smuzhiyun u32 scr; /* 0x04 Status / command Register */ 248*4882a593Smuzhiyun u32 ccrir; /* 0x08 Class Code / Revision Id Register */ 249*4882a593Smuzhiyun u32 cr1; /* 0x0c Configuration 1 Register */ 250*4882a593Smuzhiyun u32 bar0; /* 0x10 Base address register 0 Register */ 251*4882a593Smuzhiyun u32 bar1; /* 0x14 Base address register 1 Register */ 252*4882a593Smuzhiyun u32 bar2; /* 0x18 Base address register 2 Register */ 253*4882a593Smuzhiyun u32 bar3; /* 0x1c Base address register 3 Register */ 254*4882a593Smuzhiyun u32 bar4; /* 0x20 Base address register 4 Register */ 255*4882a593Smuzhiyun u32 bar5; /* 0x24 Base address register 5 Register */ 256*4882a593Smuzhiyun u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ 257*4882a593Smuzhiyun u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ 258*4882a593Smuzhiyun u32 erbar; /* 0x30 Expansion ROM Base Address Register */ 259*4882a593Smuzhiyun u32 cpr; /* 0x34 Capabilities Pointer Register */ 260*4882a593Smuzhiyun u32 rsvd1; /* 0x38 */ 261*4882a593Smuzhiyun u32 cr2; /* 0x3c Configuration Register 2 */ 262*4882a593Smuzhiyun u32 rsvd2[8]; /* 0x40 - 0x5f */ 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* General control / status registers */ 265*4882a593Smuzhiyun u32 gscr; /* 0x60 Global Status / Control Register */ 266*4882a593Smuzhiyun u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ 267*4882a593Smuzhiyun u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ 268*4882a593Smuzhiyun u32 tcr1; /* 0x6c Target Control 1 Register */ 269*4882a593Smuzhiyun u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ 270*4882a593Smuzhiyun u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ 271*4882a593Smuzhiyun u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ 272*4882a593Smuzhiyun u32 rsvd3; /* 0x7c */ 273*4882a593Smuzhiyun u32 iwcr; /* 0x80 Initiator Window Configuration Register */ 274*4882a593Smuzhiyun u32 icr; /* 0x84 Initiator Control Register */ 275*4882a593Smuzhiyun u32 isr; /* 0x88 Initiator Status Register */ 276*4882a593Smuzhiyun u32 tcr2; /* 0x8c Target Control 2 Register */ 277*4882a593Smuzhiyun u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ 278*4882a593Smuzhiyun u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ 279*4882a593Smuzhiyun u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ 280*4882a593Smuzhiyun u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ 281*4882a593Smuzhiyun u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ 282*4882a593Smuzhiyun u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ 283*4882a593Smuzhiyun u32 intr; /* 0xa8 Interrupt Register */ 284*4882a593Smuzhiyun u32 rsvd4[19]; /* 0xac - 0xf7 */ 285*4882a593Smuzhiyun u32 car; /* 0xf8 Configuration Address Register */ 286*4882a593Smuzhiyun } pci_t; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun typedef struct pci_arbiter { 289*4882a593Smuzhiyun /* Pci Arbiter Registers */ 290*4882a593Smuzhiyun union { 291*4882a593Smuzhiyun u32 acr; /* Arbiter Control Register */ 292*4882a593Smuzhiyun u32 asr; /* Arbiter Status Register */ 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun } pciarb_t; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* Register read/write struct */ 297*4882a593Smuzhiyun typedef struct scm1 { 298*4882a593Smuzhiyun u32 mpr; /* 0x00 Master Privilege Register */ 299*4882a593Smuzhiyun u32 rsvd1[7]; 300*4882a593Smuzhiyun u32 pacra; /* 0x20 Peripheral Access Control Register A */ 301*4882a593Smuzhiyun u32 pacrb; /* 0x24 Peripheral Access Control Register B */ 302*4882a593Smuzhiyun u32 pacrc; /* 0x28 Peripheral Access Control Register C */ 303*4882a593Smuzhiyun u32 pacrd; /* 0x2C Peripheral Access Control Register D */ 304*4882a593Smuzhiyun u32 rsvd2[4]; 305*4882a593Smuzhiyun u32 pacre; /* 0x40 Peripheral Access Control Register E */ 306*4882a593Smuzhiyun u32 pacrf; /* 0x44 Peripheral Access Control Register F */ 307*4882a593Smuzhiyun u32 pacrg; /* 0x48 Peripheral Access Control Register G */ 308*4882a593Smuzhiyun } scm1_t; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun typedef struct scm2 { 311*4882a593Smuzhiyun u8 rsvd1[19]; /* 0x00 - 0x12 */ 312*4882a593Smuzhiyun u8 wcr; /* 0x13 */ 313*4882a593Smuzhiyun u16 rsvd2; /* 0x14 - 0x15 */ 314*4882a593Smuzhiyun u16 cwcr; /* 0x16 */ 315*4882a593Smuzhiyun u8 rsvd3[3]; /* 0x18 - 0x1A */ 316*4882a593Smuzhiyun u8 cwsr; /* 0x1B */ 317*4882a593Smuzhiyun u8 rsvd4[3]; /* 0x1C - 0x1E */ 318*4882a593Smuzhiyun u8 scmisr; /* 0x1F */ 319*4882a593Smuzhiyun u32 rsvd5; /* 0x20 - 0x23 */ 320*4882a593Smuzhiyun u8 bcr; /* 0x24 */ 321*4882a593Smuzhiyun u8 rsvd6[74]; /* 0x25 - 0x6F */ 322*4882a593Smuzhiyun u32 cfadr; /* 0x70 */ 323*4882a593Smuzhiyun u8 rsvd7; /* 0x74 */ 324*4882a593Smuzhiyun u8 cfier; /* 0x75 */ 325*4882a593Smuzhiyun u8 cfloc; /* 0x76 */ 326*4882a593Smuzhiyun u8 cfatr; /* 0x77 */ 327*4882a593Smuzhiyun u32 rsvd8; /* 0x78 - 0x7B */ 328*4882a593Smuzhiyun u32 cfdtr; /* 0x7C */ 329*4882a593Smuzhiyun } scm2_t; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun typedef struct rtcex { 332*4882a593Smuzhiyun u32 rsvd1[3]; 333*4882a593Smuzhiyun u32 gocu; 334*4882a593Smuzhiyun u32 gocl; 335*4882a593Smuzhiyun } rtcex_t; 336*4882a593Smuzhiyun #endif /* __IMMAP_5445X__ */ 337