include/asm/processor.h

13 /* Machine State Register (MSR) Fields */
60 /* Floating Point Status and Control Register (FPSCR) Fields */
92 #define SPRN_CCR0	0x3B3	/* Core Configuration Register 0 */
94 #define SPRN_CCR1	0x378	/* Core Configuration Register for 440 only */
96 #define SPRN_CDBCR	0x3D7	/* Cache Debug Control Register */
97 #define SPRN_CTR	0x009	/* Count Register */
98 #define SPRN_DABR	0x3F5	/* Data Address Breakpoint Register */
106 #define SPRN_DAR	0x013	/* Data Address Register */
107 #define SPRN_DBAT0L	0x219	/* Data BAT 0 Lower Register */
108 #define SPRN_DBAT0U	0x218	/* Data BAT 0 Upper Register */
109 #define SPRN_DBAT1L	0x21B	/* Data BAT 1 Lower Register */
110 #define SPRN_DBAT1U	0x21A	/* Data BAT 1 Upper Register */
111 #define SPRN_DBAT2L	0x21D	/* Data BAT 2 Lower Register */
112 #define SPRN_DBAT2U	0x21C	/* Data BAT 2 Upper Register */
113 #define SPRN_DBAT3L	0x21F	/* Data BAT 3 Lower Register */
114 #define SPRN_DBAT3U	0x21E	/* Data BAT 3 Upper Register */
115 #define SPRN_DBAT4L	0x239	/* Data BAT 4 Lower Register */
116 #define SPRN_DBAT4U	0x238	/* Data BAT 4 Upper Register */
117 #define SPRN_DBAT5L	0x23B	/* Data BAT 5 Lower Register */
118 #define SPRN_DBAT5U	0x23A	/* Data BAT 5 Upper Register */
119 #define SPRN_DBAT6L	0x23D	/* Data BAT 6 Lower Register */
120 #define SPRN_DBAT6U	0x23C	/* Data BAT 6 Upper Register */
121 #define SPRN_DBAT7L	0x23F	/* Data BAT 7 Lower Register */
122 #define SPRN_DBAT7U	0x23E	/* Data BAT 7 Lower Register */
157 #define SPRN_DBCR0	0x3F2		/* Debug Control Register 0 */
159 #define SPRN_DBCR0	0x134		/* Book E Debug Control Register 0 */
162 #define SPRN_DBCR1	0x3BD	/* Debug Control Register 1 */
163 #define SPRN_DBSR	0x3F0	/* Debug Status Register */
165 #define SPRN_DBCR1	0x135		/* Book E Debug Control Register 1 */
167 #define	SPRN_DBDR	0x3f3		/* Debug Data Register */
169 #define SPRN_DBSR	0x130		/* Book E Debug Status Register */
173 #define SPRN_DCCR	0x3FA	/* Data Cache Cacheability Register */
177 #define	SPRN_DCDBTRL	0x39c	/* Data Cache Debug Tag Register Low */
178 #define	SPRN_DCDBTRH	0x39d	/* Data Cache Debug Tag Register High */
180 #define SPRN_DCMP	0x3D1	/* Data TLB Compare Register */
181 #define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
185 #define SPRN_DEAR	0x3D5	/* Data Error Address Register */
187 #define SPRN_DEAR	0x03D	/* Book E Data Error Address Register */
189 #define SPRN_DEC	0x016	/* Decrement Register */
190 #define SPRN_DMISS	0x3D0	/* Data TLB Miss Register */
197 #define SPRN_DSISR	0x012	/* Data Storage Interrupt Status Register */
205 #define SPRN_EAR	0x11A	/* External Address Register */
207 #define SPRN_ESR	0x3D4	/* Exception Syndrome Register */
209 #define SPRN_ESR	0x03E		/* Book E Exception Syndrome Register */
220 #define SPRN_EVPR	0x3D6	/* Exception Vector Prefix Register */
221 #define SPRN_HASH1	0x3D2	/* Primary Hash Address Register */
223 #define SPRN_HID0	0x3F0	/* Hardware Implementation Register 0 */
257 #define SPRN_HID1	0x3F1	/* Hardware Implementation Register 1 */
262 #define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
270 #define SPRN_IBAT0L	0x211	/* Instruction BAT 0 Lower Register */
271 #define SPRN_IBAT0U	0x210	/* Instruction BAT 0 Upper Register */
272 #define SPRN_IBAT1L	0x213	/* Instruction BAT 1 Lower Register */
273 #define SPRN_IBAT1U	0x212	/* Instruction BAT 1 Upper Register */
274 #define SPRN_IBAT2L	0x215	/* Instruction BAT 2 Lower Register */
275 #define SPRN_IBAT2U	0x214	/* Instruction BAT 2 Upper Register */
276 #define SPRN_IBAT3L	0x217	/* Instruction BAT 3 Lower Register */
277 #define SPRN_IBAT3U	0x216	/* Instruction BAT 3 Upper Register */
278 #define SPRN_IBAT4L	0x231	/* Instruction BAT 4 Lower Register */
279 #define SPRN_IBAT4U	0x230	/* Instruction BAT 4 Upper Register */
280 #define SPRN_IBAT5L	0x233	/* Instruction BAT 5 Lower Register */
281 #define SPRN_IBAT5U	0x232	/* Instruction BAT 5 Upper Register */
282 #define SPRN_IBAT6L	0x235	/* Instruction BAT 6 Lower Register */
283 #define SPRN_IBAT6U	0x234	/* Instruction BAT 6 Upper Register */
284 #define SPRN_IBAT7L	0x237	/* Instruction BAT 7 Lower Register */
285 #define SPRN_IBAT7U	0x236	/* Instruction BAT 7 Upper Register */
286 #define SPRN_ICCR	0x3FB	/* Instruction Cache Cacheability Register */
289 #define SPRN_ICDBDR	0x3D3	/* Instruction Cache Debug Data Register */
291 #define SPRN_ICDBTRL	0x39e	/* instruction cache debug tag register low */
292 #define	SPRN_ICDBTRH	0x39f	/* instruction cache debug tag register high */
294 #define SPRN_ICMP	0x3D5	/* Instruction TLB Compare Register */
296 #define SPRN_IMISS	0x3D4	/* Instruction TLB Miss Register */
297 #define SPRN_IMMR	0x27E	/* Internal Memory Map Register */
309 #define SPRN_LDSTCR	0x3F8	/* Load/Store Control Register */
311 #define SPRN_LR		0x008	/* Link Register */
313 #define SPRN_MMCR0	0x3B8	/* Monitor Mode Control Register 0 */
314 #define SPRN_MMCR1	0x3BC	/* Monitor Mode Control Register 1 */
316 #define	SPRN_MMUCR	0x3b2	/* MMU Control Register */
324 #define SPRN_PIR	0x3FF	/* Processor Identification Register */
327 #define SPRN_PIR	0x11E	/* Book E Processor Identification Register */
330 #define SPRN_PMC1	0x3B9	/* Performance Counter Register 1 */
331 #define SPRN_PMC2	0x3BA	/* Performance Counter Register 2 */
332 #define SPRN_PMC3	0x3BD	/* Performance Counter Register 3 */
333 #define SPRN_PMC4	0x3BE	/* Performance Counter Register 4 */
334 #define SPRN_PVR	0x11F	/* Processor Version Register */
335 #define SPRN_RPA	0x3D6	/* Required Physical Address Register */
339 #define SPRN_SDA	0x3BF	/* Sampled Data Address Register */
340 #define SPRN_SDR1	0x019	/* MMU Hash Base Register */
341 #define SPRN_SGR	0x3B9	/* Storage Guarded Register */
344 #define SPRN_SIA	0x3BB	/* Sampled Instruction Address Register */
345 #define SPRN_SPRG0	0x110	/* Special Purpose Register General 0 */
346 #define SPRN_SPRG1	0x111	/* Special Purpose Register General 1 */
347 #define SPRN_SPRG2	0x112	/* Special Purpose Register General 2 */
348 #define SPRN_SPRG3	0x113	/* Special Purpose Register General 3 */
349 #define SPRN_SPRG4	0x114	/* Special Purpose Register General 4 */
350 #define SPRN_SPRG5	0x115	/* Special Purpose Register General 5 */
351 #define SPRN_SPRG6	0x116	/* Special Purpose Register General 6 */
352 #define SPRN_SPRG7	0x117	/* Special Purpose Register General 7 */
353 #define SPRN_SRR0	0x01A	/* Save/Restore Register 0 */
354 #define SPRN_SRR1	0x01B	/* Save/Restore Register 1 */
355 #define SPRN_SRR2	0x3DE	/* Save/Restore Register 2 */
356 #define SPRN_SRR3	0x3DF	/* Save/Restore Register 3 */
359 #define SPRN_SVR	0x3FF	/* System Version Register */
361 #define SPRN_SVR	0x11E	/* System Version Register */
367 #define SPRN_TBRL	0x10C	/* Time Base Read Lower Register */
368 #define SPRN_TBRU	0x10D	/* Time Base Read Upper Register */
369 #define SPRN_TBWL	0x11C	/* Time Base Write Lower Register */
370 #define SPRN_TBWU	0x11D	/* Time Base Write Upper Register */
372 #define SPRN_TCR	0x3DA	/* Timer Control Register */
374 #define SPRN_TCR	0x154	/* Book E Timer Control Register */
400 #define SPRN_THRM1	0x3FC	/* Thermal Management Register 1 */
407 #define SPRN_THRM2	0x3FD	/* Thermal Management Register 2 */
408 #define SPRN_THRM3	0x3FE	/* Thermal Management Register 3 */
410 #define SPRN_TLBMISS	0x3D4	/* 980 7450 TLB Miss Register */
412 #define SPRN_TSR	0x3D8	/* Timer Status Register */
414 #define SPRN_TSR	0x150	/* Book E Timer Status Register */
425 #define SPRN_UMMCR0	0x3A8	/* User Monitor Mode Control Register 0 */
426 #define SPRN_UMMCR1	0x3AC	/* User Monitor Mode Control Register 0 */
427 #define SPRN_UPMC1	0x3A9	/* User Performance Counter Register 1 */
428 #define SPRN_UPMC2	0x3AA	/* User Performance Counter Register 2 */
429 #define SPRN_UPMC3	0x3AD	/* User Performance Counter Register 3 */
430 #define SPRN_UPMC4	0x3AE	/* User Performance Counter Register 4 */
431 #define SPRN_USIA	0x3AB	/* User Sampled Instruction Address Register */
432 #define SPRN_XER	0x001	/* Fixed Point Exception Register */
433 #define SPRN_ZPR	0x3B0	/* Zone Protection Register */
436 #define SPRN_DECAR	0x036	/* Decrementer Auto Reload Register */
439 #define SPRN_IVPR	0x03F	/* Interrupt Vector Prefix Register */
440 #define SPRN_USPRG0	0x100	/* User Special Purpose Register General 0 */
441 #define SPRN_SPRG4R	0x104	/* Special Purpose Register General 4 Read */
442 #define SPRN_SPRG5R	0x105	/* Special Purpose Register General 5 Read */
443 #define SPRN_SPRG6R	0x106	/* Special Purpose Register General 6 Read */
444 #define SPRN_SPRG7R	0x107	/* Special Purpose Register General 7 Read */
445 #define SPRN_SPRG4W	0x114	/* Special Purpose Register General 4 Write */
446 #define SPRN_SPRG5W	0x115	/* Special Purpose Register General 5 Write */
447 #define SPRN_SPRG6W	0x116	/* Special Purpose Register General 6 Write */
448 #define SPRN_SPRG7W	0x117	/* Special Purpose Register General 7 Write */
449 #define SPRN_DBCR2	0x136	/* Debug Control Register 2 */
452 #define SPRN_DVC1	0x13E	/* Data Value Compare Register 1 */
453 #define SPRN_DVC2	0x13F	/* Data Value Compare Register 2 */
454 #define SPRN_IVOR0	0x190	/* Interrupt Vector Offset Register 0 */
455 #define SPRN_IVOR1	0x191	/* Interrupt Vector Offset Register 1 */
456 #define SPRN_IVOR2	0x192	/* Interrupt Vector Offset Register 2 */
457 #define SPRN_IVOR3	0x193	/* Interrupt Vector Offset Register 3 */
458 #define SPRN_IVOR4	0x194	/* Interrupt Vector Offset Register 4 */
459 #define SPRN_IVOR5	0x195	/* Interrupt Vector Offset Register 5 */
460 #define SPRN_IVOR6	0x196	/* Interrupt Vector Offset Register 6 */
461 #define SPRN_IVOR7	0x197	/* Interrupt Vector Offset Register 7 */
462 #define SPRN_IVOR8	0x198	/* Interrupt Vector Offset Register 8 */
463 #define SPRN_IVOR9	0x199	/* Interrupt Vector Offset Register 9 */
464 #define SPRN_IVOR10	0x19a	/* Interrupt Vector Offset Register 10 */
465 #define SPRN_IVOR11	0x19b	/* Interrupt Vector Offset Register 11 */
466 #define SPRN_IVOR12	0x19c	/* Interrupt Vector Offset Register 12 */
467 #define SPRN_IVOR13	0x19d	/* Interrupt Vector Offset Register 13 */
468 #define SPRN_IVOR14	0x19e	/* Interrupt Vector Offset Register 14 */
469 #define SPRN_IVOR15	0x19f	/* Interrupt Vector Offset Register 15 */
470 #define SPRN_IVOR38	0x1b0	/* Interrupt Vector Offset Register 38 */
471 #define SPRN_IVOR39	0x1b1	/* Interrupt Vector Offset Register 39 */
472 #define SPRN_IVOR40	0x1b2	/* Interrupt Vector Offset Register 40 */
473 #define SPRN_IVOR41	0x1b3	/* Interrupt Vector Offset Register 41 */
474 #define SPRN_GIVOR2	0x1b8	/* Guest Interrupt Vector Offset Register 2 */
475 #define SPRN_GIVOR3	0x1b9	/* Guest Interrupt Vector Offset Register 3 */
476 #define SPRN_GIVOR4	0x1ba	/* Guest Interrupt Vector Offset Register 4 */
477 #define SPRN_GIVOR8	0x1bb	/* Guest Interrupt Vector Offset Register 8 */
478 #define SPRN_GIVOR13	0x1bc	/* Guest Interrupt Vector Offset Register 13 */
479 #define SPRN_GIVOR14	0x1bd	/* Guest Interrupt Vector Offset Register 14 */
482 #define SPRN_L1CFG0	0x203	/* L1 Cache Configuration Register 0 */
483 #define SPRN_L1CFG1	0x204	/* L1 Cache Configuration Register 1 */
484 #define SPRN_L2CFG0	0x207	/* L2 Cache Configuration Register 0 */
485 #define SPRN_L1CSR0	0x3f2	/* L1 Data Cache Control and Status Register 0 */
491 #define SPRN_L1CSR1	0x3f3	/* L1 Instruction Cache Control and Status Register 1 */
497 #define SPRN_L1CSR2	0x25e	/* L1 Data Cache Control and Status Register 2 */
500 #define SPRN_L2CSR0	0x3f9	/* L2 Data Cache Control and Status Register 0 */
522 #define SPRN_L2CSR1	0x3fa	/* L2 Data Cache Control and Status Register 1 */
524 #define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
525 #define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
527 #define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
528 #define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
529 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
530 #define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
534 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
535 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
536 #define SPRN_MAS2	0x272	/* MMU Assist Register 2 */
537 #define SPRN_MAS3	0x273	/* MMU Assist Register 3 */
538 #define SPRN_MAS4	0x274	/* MMU Assist Register 4 */
539 #define SPRN_MAS5	0x275	/* MMU Assist Register 5 */
540 #define SPRN_MAS6	0x276	/* MMU Assist Register 6 */
541 #define SPRN_MAS7	0x3B0	/* MMU Assist Register 7 */
542 #define SPRN_MAS8	0x155	/* MMU Assist Register 8 */
544 #define SPRN_IVOR32	0x210	/* Interrupt Vector Offset Register 32 */
545 #define SPRN_IVOR33	0x211	/* Interrupt Vector Offset Register 33 */
546 #define SPRN_IVOR34	0x212	/* Interrupt Vector Offset Register 34 */
547 #define SPRN_IVOR35	0x213	/* Interrupt Vector Offset Register 35 */
548 #define SPRN_IVOR36	0x214	/* Interrupt Vector Offset Register 36 */
549 #define SPRN_IVOR37	0x215	/* Interrupt Vector Offset Register 37 */
552 #define SPRN_MCSRR0	0x23a	/* Machine Check Save and Restore Register 0 */
553 #define SPRN_MCSRR1	0x23b	/* Machine Check Save and Restore Register 1 */
554 #define SPRN_BUCSR	0x3f5	/* Branch Control and Status Register */
560 #define SPRN_BBEAR	0x201	/* Branch Buffer Entry Address Register */
561 #define SPRN_BBTAR	0x202	/* Branch Buffer Target Address Register */
562 #define SPRN_PID1	0x279	/* Process ID Register 1 */
563 #define SPRN_PID2	0x27a	/* Process ID Register 2 */
564 #define SPRN_MCSR	0x23c	/* Machine Check Syndrome register */
565 #define SPRN_MCAR	0x23d	/* Machine Check Address register */
593 #define CTR	SPRN_CTR	/* Counter Register */
594 #define DAR	SPRN_DAR	/* Data Address Register */
595 #define DABR	SPRN_DABR	/* Data Address Breakpoint Register */
596 #define DAC1	SPRN_DAC1	/* Data Address Register 1 */
597 #define DAC2	SPRN_DAC2	/* Data Address Register 2 */
598 #define DBAT0L	SPRN_DBAT0L	/* Data BAT 0 Lower Register */
599 #define DBAT0U	SPRN_DBAT0U	/* Data BAT 0 Upper Register */
600 #define DBAT1L	SPRN_DBAT1L	/* Data BAT 1 Lower Register */
601 #define DBAT1U	SPRN_DBAT1U	/* Data BAT 1 Upper Register */
602 #define DBAT2L	SPRN_DBAT2L	/* Data BAT 2 Lower Register */
603 #define DBAT2U	SPRN_DBAT2U	/* Data BAT 2 Upper Register */
604 #define DBAT3L	SPRN_DBAT3L	/* Data BAT 3 Lower Register */
605 #define DBAT3U	SPRN_DBAT3U	/* Data BAT 3 Upper Register */
606 #define DBAT4L	SPRN_DBAT4L	/* Data BAT 4 Lower Register */
607 #define DBAT4U	SPRN_DBAT4U	/* Data BAT 4 Upper Register */
608 #define DBAT5L	SPRN_DBAT5L	/* Data BAT 5 Lower Register */
609 #define DBAT5U	SPRN_DBAT5U	/* Data BAT 5 Upper Register */
610 #define DBAT6L	SPRN_DBAT6L	/* Data BAT 6 Lower Register */
611 #define DBAT6U	SPRN_DBAT6U	/* Data BAT 6 Upper Register */
612 #define DBAT7L	SPRN_DBAT7L	/* Data BAT 7 Lower Register */
613 #define DBAT7U	SPRN_DBAT7U	/* Data BAT 7 Upper Register */
614 #define DBCR0	SPRN_DBCR0	/* Debug Control Register 0 */
615 #define DBCR1	SPRN_DBCR1	/* Debug Control Register 1 */
616 #define DBSR	SPRN_DBSR	/* Debug Status Register */
617 #define DCMP	SPRN_DCMP	/* Data TLB Compare Register */
618 #define DEC	SPRN_DEC	/* Decrement Register */
619 #define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
620 #define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
621 #define EAR	SPRN_EAR	/* External Address Register */
622 #define ESR	SPRN_ESR	/* Exception Syndrome Register */
623 #define HASH1	SPRN_HASH1	/* Primary Hash Address Register */
624 #define HASH2	SPRN_HASH2	/* Secondary Hash Address Register */
625 #define HID0	SPRN_HID0	/* Hardware Implementation Register 0 */
626 #define HID1	SPRN_HID1	/* Hardware Implementation Register 1 */
627 #define IABR	SPRN_IABR	/* Instruction Address Breakpoint Register */
628 #define IAC1	SPRN_IAC1	/* Instruction Address Register 1 */
629 #define IAC2	SPRN_IAC2	/* Instruction Address Register 2 */
630 #define IBAT0L	SPRN_IBAT0L	/* Instruction BAT 0 Lower Register */
631 #define IBAT0U	SPRN_IBAT0U	/* Instruction BAT 0 Upper Register */
632 #define IBAT1L	SPRN_IBAT1L	/* Instruction BAT 1 Lower Register */
633 #define IBAT1U	SPRN_IBAT1U	/* Instruction BAT 1 Upper Register */
634 #define IBAT2L	SPRN_IBAT2L	/* Instruction BAT 2 Lower Register */
635 #define IBAT2U	SPRN_IBAT2U	/* Instruction BAT 2 Upper Register */
636 #define IBAT3L	SPRN_IBAT3L	/* Instruction BAT 3 Lower Register */
637 #define IBAT3U	SPRN_IBAT3U	/* Instruction BAT 3 Upper Register */
638 #define IBAT4L	SPRN_IBAT4L	/* Instruction BAT 4 Lower Register */
639 #define IBAT4U	SPRN_IBAT4U	/* Instruction BAT 4 Upper Register */
640 #define IBAT5L	SPRN_IBAT5L	/* Instruction BAT 5 Lower Register */
641 #define IBAT5U	SPRN_IBAT5U	/* Instruction BAT 5 Upper Register */
642 #define IBAT6L	SPRN_IBAT6L	/* Instruction BAT 6 Lower Register */
643 #define IBAT6U	SPRN_IBAT6U	/* Instruction BAT 6 Upper Register */
644 #define IBAT7L	SPRN_IBAT7L	/* Instruction BAT 7 Lower Register */
645 #define IBAT7U	SPRN_IBAT7U	/* Instruction BAT 7 Lower Register */
646 #define ICMP	SPRN_ICMP	/* Instruction TLB Compare Register */
647 #define IMISS	SPRN_IMISS	/* Instruction TLB Miss Register */
648 #define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
649 #define LDSTCR	SPRN_LDSTCR	/* Load/Store Control Register */
650 #define L2CR	SPRN_L2CR	/* PPC 750 L2 control register */
659 #define SVR	SPRN_SVR	/* System-On-Chip Version Register */
661 #define RPA	SPRN_RPA	/* Required Physical Address Register */
662 #define SDR1	SPRN_SDR1	/* MMU hash base register */
675 #define SRR0	SPRN_SRR0	/* Save and Restore Register 0 */
676 #define SRR1	SPRN_SRR1	/* Save and Restore Register 1 */
677 #define SRR2	SPRN_SRR2	/* Save and Restore Register 2 */
678 #define SRR3	SPRN_SRR3	/* Save and Restore Register 3 */
679 #define SVR	SPRN_SVR	/* System Version Register */
680 #define TBRL	SPRN_TBRL	/* Time Base Read Lower Register */
681 #define TBRU	SPRN_TBRU	/* Time Base Read Upper Register */
682 #define TBWL	SPRN_TBWL	/* Time Base Write Lower Register */
683 #define TBWU	SPRN_TBWU	/* Time Base Write Upper Register */
684 #define TCR	SPRN_TCR	/* Timer Control Register */
685 #define TSR	SPRN_TSR	/* Timer Status Register */
687 #define THRM1	SPRN_THRM1	/* Thermal Management Register 1 */
688 #define THRM2	SPRN_THRM2	/* Thermal Management Register 2 */
689 #define THRM3	SPRN_THRM3	/* Thermal Management Register 3 */
765 #define DCRN_BEAR	0x090	/* Bus Error Address Register */
766 #define DCRN_BESR	0x091	/* Bus Error Syndrome Register */
776 #define DCRN_DMACC0	0x0C4	/* DMA Chained Count Register 0 */
777 #define DCRN_DMACC1	0x0CC	/* DMA Chained Count Register 1 */
778 #define DCRN_DMACC2	0x0D4	/* DMA Chained Count Register 2 */
779 #define DCRN_DMACC3	0x0DC	 /* DMA Chained Count Register 3 */
780 #define DCRN_DMACR0	0x0C0	 /* DMA Channel Control Register 0 */
781 #define DCRN_DMACR1	0x0C8	 /* DMA Channel Control Register 1 */
782 #define DCRN_DMACR2	0x0D0	 /* DMA Channel Control Register 2 */
783 #define DCRN_DMACR3	0x0D8	 /* DMA Channel Control Register 3 */
784 #define DCRN_DMACT0	0x0C1	 /* DMA Count Register 0 */
785 #define DCRN_DMACT1	0x0C9	 /* DMA Count Register 1 */
786 #define DCRN_DMACT2	0x0D1	 /* DMA Count Register 2 */
787 #define DCRN_DMACT3	0x0D9	 /* DMA Count Register 3 */
788 #define DCRN_DMADA0	0x0C2	 /* DMA Destination Address Register 0 */
789 #define DCRN_DMADA1	0x0CA	 /* DMA Destination Address Register 1 */
790 #define DCRN_DMADA2	0x0D2	 /* DMA Destination Address Register 2 */
791 #define DCRN_DMADA3	0x0DA	 /* DMA Destination Address Register 3 */
792 #define DCRN_DMASA0	0x0C3	 /* DMA Source Address Register 0 */
793 #define DCRN_DMASA1	0x0CB	 /* DMA Source Address Register 1 */
794 #define DCRN_DMASA2	0x0D3	 /* DMA Source Address Register 2 */
795 #define DCRN_DMASA3	0x0DB	 /* DMA Source Address Register 3 */
796 #define DCRN_DMASR	0x0E0	 /* DMA Status Register */
797 #define DCRN_EXIER	0x042	 /* External Interrupt Enable Register */
812 #define DCRN_EXISR	0x040	 /* External Interrupt Status Register */
813 #define DCRN_IOCR	0x0A0	 /* Input/Output Configuration Register */
839 /* System-On-Chip Version Register */
841 /* System-On-Chip Version Register (SVR) field extraction */
854 /* Processor Version Register */
856 /* Processor Version Register (PVR) field extraction */
1020  * System Version Register
1023 /* System Version Register (SVR) field extraction */
1265 	struct pt_regs	*regs;		/* Pointer to saved register state */