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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/video/
H A Drockchip_rga.txt29 reg = <0xff680000 0x10000>;
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/
H A Drockchip-rga.yaml72 reg = <0xff680000 0x10000>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-linux.dtsi20 …bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 roo…
30 reg = <0x0 0x0 0x0 0x0>;
34 reg = <0x0 0x110000 0x0 0xf0000>;
41 record-size = <0x0 0x40000>;
42 console-size = <0x0 0x80000>;
43 ftrace-size = <0x0 0x00000>;
44 pmsg-size = <0x0 0x00000>;
51 rockchip,wake-irq = <0>;
54 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
56 pinctrl-0 = <&uart2c_xfer>;
[all …]
H A Drk3399-android.dtsi16 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m";
28 rockchip,wake-irq = <0>;
32 pinctrl-0 = <&uart2c_xfer>;
33 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
43 reg = <0x0 0x0 0x0 0x0>;
48 reg = <0x0 0x0 0x0 0x0>;
53 reg = <0x0 0x110000 0x0 0xf0000>;
54 record-size = <0x20000>;
55 console-size = <0x80000>;
56 ftrace-size = <0x00000>;
[all …]
H A Drk3399-firefly-android.dts21 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m";
32 pwms = <&pwm0 0 25000 0>;
34 0 1 2 3 4 5 6 7
73 #clock-cells = <0>;
79 #sound-dai-cells = <0>;
90 pinctrl-0 = <&lcd_panel_reset>;
102 rockchip,wake-irq = <0>;
104 rockchip,irq-mode-enable = <0>;
108 pinctrl-0 = <&uart2c_xfer>;
109 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
[all …]
H A Drk3368.dtsi43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
78 cpu_l0: cpu@0 {
81 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
97 reg = <0x0 0x2>;
105 reg = <0x0 0x3>;
113 reg = <0x0 0x100>;
121 reg = <0x0 0x101>;
129 reg = <0x0 0x102>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3562/
H A Drk3562.c23 #define FIREWALL_DDR_BASE 0xfef00000
24 #define FW_DDR_MST3_REG 0x2c /* usb */
25 #define FW_DDR_MST4_REG 0x30 /* emmc */
26 #define FW_DDR_MST5_REG 0x34 /* fspi */
27 #define FW_DDR_MST6_REG 0x38 /* sdmmc mcu */
28 #define FW_DDR_CON_REG 0x80
30 #define PMU_GRF_BASE 0xff010000
31 #define PMU_GRF_SOC_CON9 0x0124
33 #define SYS_GRF_BASE 0xff030000
34 #define SYS_GRF_SOC_CON5 0x0414
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3368.dtsi76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
114 cpu_sleep: cpu-sleep-0 {
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
123 cpu_l0: cpu@0 {
126 reg = <0x0 0x0>;
136 reg = <0x0 0x1>;
[all …]
H A D.rk3368-sheep.dtb.dts.tmp
H A D.rk3368-geekbox.dtb.dts.tmp
H A D.rk3368-lion.dtb.dts.tmp
H A D.rk3368-px5-evb.dtb.dts.tmp
H A Drk3288.dtsi55 #size-cells = <0>;
62 reg = <0x500>;
87 reg = <0x501>;
93 reg = <0x502>;
99 reg = <0x503>;
113 reg = <0xff250000 0x4000>;
124 reg = <0xff600000 0x4000>;
125 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 reg = <0xffb20000 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A D.rk3288-rock2-square.dtb.dts.tmp
H A D.rk3288-vyasa.dtb.dts.tmp
H A D.rk3288-firefly.dtb.dts.tmp
H A D.rk3288-evb.dtb.dts.tmp
H A D.rk3288-tinker.dtb.dts.tmp
H A D.rk3288-popmetal.dtb.dts.tmp
H A D.rk3288-miqi.dtb.dts.tmp
H A Drv1126.dtsi46 #size-cells = <0>;
51 reg = <0xf00>;
61 reg = <0xf01>;
71 reg = <0xf02>;
81 reg = <0xf03>;
94 arm,psci-suspend-param = <0x0010000>;
164 bus-id = <0>;
165 cfg-val = <0x00300020>;
166 enable-msk = <0x7144>;
171 cfg-val = <0x00300020>;
[all …]
H A D.rk3288-fennec.dtb.dts.tmp
H A D.rk3288-phycore-rdk.dtb.dts.tmp
H A Drk3562.dtsi71 #clock-cells = <0>;
78 #clock-cells = <0>;
85 reg = <0 0xff100324 0 0x10>;
89 #clock-cells = <0>;
94 reg = <0 0xff100328 0 0x10>;
98 #clock-cells = <0>;
103 reg = <0 0xff10032c 0 0x10>;
107 #clock-cells = <0>;
112 reg = <0 0xff100334 0 0x10>;
116 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3288.dtsi70 #size-cells = <0>;
77 reg = <0x500>;
89 reg = <0x501>;
101 reg = <0x502>;
113 reg = <0x503>;
138 0 17
144 0 15300 0
151 rockchip,pvtm-ch = <0 0>;
269 reg = <0x0 0xff250000 0x0 0x4000>;
281 reg = <0x0 0xff600000 0x0 0x4000>;
[all …]

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