dts/rockchip/rk3399-firefly-android.dts

21 		bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m";
32 		pwms = <&pwm0 0 25000 0>;
34 			  0   1   2   3   4   5   6   7
73 		#clock-cells = <0>;
79 		#sound-dai-cells = <0>;
90 		pinctrl-0 = <&lcd_panel_reset>;
102 		rockchip,wake-irq = <0>;
104 		rockchip,irq-mode-enable = <0>;
108 		pinctrl-0 = <&uart2c_xfer>;
109 		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
119 			reg = <0x0 0x0 0x0 0x0>;
124 			reg = <0x0 0x0 0x0 0x0>;
129 			reg = <0x0 0x110000 0x0 0xf0000>;
130 			record-size = <0x20000>;
131 			console-size = <0x80000>;
132 			ftrace-size = <0x00000>;
133 			pmsg-size = <0x50000>;
204 		reg = <0x0 0xff680000 0x0 0x1000>;
205 		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
231 		#sound-dai-cells = <0>;
239 		pinctrl-0 = <&wifi_enable_h>;
257 		pinctrl-0 = <&pcie_drv>;
273 		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
275 		pinctrl-0 = <&host_vbus_drv>;
298 		pwms = <&pwm2 0 25000 1>;
333 		pinctrl-0 = <&lcd_en>;
341 		#clock-cells = <0>;
358 		pinctrl-0 = <&uart0_rts>;
422 	pinctrl-0 = <&edp_hpd>;
428 			#size-cells = <0>;
430 			edp_out_panel: endpoint@0 {
431 				reg = <0>;
448 	snps,reset-delays-us = <0 10000 50000>;
452 	pinctrl-0 = <&rgmii_pins>;
453 	tx_delay = <0x28>;
454 	rx_delay = <0x11>;
465 	#size-cells = <0>;
466 	#sound-dai-cells = <0>;
478 		reg = <0x40>;
497 		reg = <0x41>;
515 		reg = <0x1b>;
519 		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
703 		#sound-dai-cells = <0>;
705 		reg = <0x1c>;
710 		pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>;
732 		reg = <0x22>;
734 		pinctrl-0 = <&fusb0_int>;
736 		vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
742 		reg = <0x41>;
752 		reg = <0x68>;
753 		mpu-int_config = <0x10>;
754 		mpu-level_shifter = <0>;
755 		mpu-orientation = <0 1 0 1 0 0 0 0 1>;
770 	#sound-dai-cells = <0>;
778 	#sound-dai-cells = <0>;
782 	#sound-dai-cells = <0>;
803 	pinctrl-0 = <&pcie_clkreqn_cpm>;
831 				<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
850 				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
900 	pinctrl-0 = <&pwm2_pin_pull_down>;
936 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
952 	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
959 	pinctrl-0 = <&spdif_bus_1>;
962 	#sound-dai-cells = <0>;
975 	/* tshut mode 0:CRU 1:GPIO */
977 	/* tshut polarity 0:LOW 1:HIGH */
1011 	pinctrl-0 = <&uart0_xfer &uart0_cts>;