1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/display/drm_mipi_dsi.h> 8#include <dt-bindings/display/media-bus-format.h> 9#include "rk3399-vop-clk-set.dtsi" 10#include <dt-bindings/input/input.h> 11 12/ { 13 compatible = "rockchip,android", "rockchip,rk3399"; 14 15 chosen: chosen { 16 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m"; 17 }; 18 19 cpuinfo { 20 compatible = "rockchip,cpuinfo"; 21 nvmem-cells = <&cpu_id>; 22 nvmem-cell-names = "id"; 23 }; 24 25 fiq_debugger: fiq-debugger { 26 compatible = "rockchip,fiq-debugger"; 27 rockchip,serial-id = <2>; 28 rockchip,wake-irq = <0>; 29 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ 30 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 31 pinctrl-names = "default"; 32 pinctrl-0 = <&uart2c_xfer>; 33 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 34 }; 35 36 reserved-memory { 37 #address-cells = <2>; 38 #size-cells = <2>; 39 ranges; 40 41 drm_logo: drm-logo@00000000 { 42 compatible = "rockchip,drm-logo"; 43 reg = <0x0 0x0 0x0 0x0>; 44 }; 45 46 vendor_storage_rm: vendor-storage-rm@00000000 { 47 compatible = "rockchip,vendor-storage-rm"; 48 reg = <0x0 0x0 0x0 0x0>; 49 }; 50 51 ramoops: ramoops@110000 { 52 compatible = "ramoops"; 53 reg = <0x0 0x110000 0x0 0xf0000>; 54 record-size = <0x20000>; 55 console-size = <0x80000>; 56 ftrace-size = <0x00000>; 57 pmsg-size = <0x50000>; 58 }; 59 60 secure_memory: secure-memory@20000000 { 61 compatible = "rockchip,secure-memory"; 62 reg = <0x0 0x20000000 0x0 0x10000000>; 63 status = "disabled"; 64 }; 65 66 stb_devinfo: stb-devinfo@00000000 { 67 compatible = "rockchip,stb-devinfo"; 68 reg = <0x0 0x0 0x0 0x0>; 69 }; 70 }; 71 72 gpio_keys: gpio-keys { 73 compatible = "gpio-keys"; 74 autorepeat; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pwrbtn>; 77 78 power { 79 debounce-interval = <100>; 80 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 81 label = "GPIO Key Power"; 82 linux,code = <KEY_POWER>; 83 wakeup-source; 84 }; 85 }; 86 87 vendor_storage: vendor-storage { 88 compatible = "rockchip,ram-vendor-storage"; 89 memory-region = <&vendor_storage_rm>; 90 status = "okay"; 91 }; 92 93 rga: rga@ff680000 { 94 compatible = "rockchip,rga2"; 95 dev_mode = <1>; 96 reg = <0x0 0xff680000 0x0 0x1000>; 97 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 98 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 99 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 100 power-domains = <&power RK3399_PD_RGA>; 101 status = "okay"; 102 }; 103 104 hdmi_dp_sound: hdmi-dp-sound { 105 status = "disabled"; 106 compatible = "rockchip,rk3399-hdmi-dp"; 107 rockchip,cpu = <&i2s2>; 108 rockchip,codec = <&hdmi>, <&cdn_dp>; 109 }; 110 111 firmware { 112 firmware_android: android {}; 113 114 optee: optee { 115 compatible = "linaro,optee-tz"; 116 method = "smc"; 117 }; 118 }; 119}; 120 121&uart2 { 122 status = "disabled"; 123}; 124 125&vopb { 126 support-multi-area; 127 status = "okay"; 128}; 129 130&vopb_mmu { 131 status = "okay"; 132}; 133 134&vopl { 135 support-multi-area; 136 status = "okay"; 137}; 138 139&vopl_mmu { 140 status = "okay"; 141}; 142 143&hdmi { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 #sound-dai-cells = <0>; 147 ddc-i2c-scl-high-time-ns = <9625>; 148 ddc-i2c-scl-low-time-ns = <10000>; 149 status = "okay"; 150}; 151 152&display_subsystem { 153 status = "okay"; 154 155 ports = <&vopb_out>, <&vopl_out>; 156 logo-memory-region = <&drm_logo>; 157 secure-memory-region = <&secure_memory>; 158 route { 159 route_hdmi: route-hdmi { 160 status = "disabled"; 161 logo,uboot = "logo.bmp"; 162 logo,kernel = "logo_kernel.bmp"; 163 logo,mode = "center"; 164 charge_logo,mode = "center"; 165 connect = <&vopb_out_hdmi>; 166 }; 167 168 route_dsi: route-dsi { 169 status = "disabled"; 170 logo,uboot = "logo.bmp"; 171 logo,kernel = "logo_kernel.bmp"; 172 logo,mode = "center"; 173 charge_logo,mode = "center"; 174 connect = <&vopb_out_dsi>; 175 }; 176 177 route_dsi1: route-dsi1 { 178 status = "disabled"; 179 logo,uboot = "logo.bmp"; 180 logo,kernel = "logo_kernel.bmp"; 181 logo,mode = "center"; 182 charge_logo,mode = "center"; 183 connect = <&vopl_out_dsi1>; 184 }; 185 186 route_edp: route-edp { 187 status = "disabled"; 188 logo,uboot = "logo.bmp"; 189 logo,kernel = "logo_kernel.bmp"; 190 logo,mode = "center"; 191 charge_logo,mode = "center"; 192 connect = <&vopb_out_edp>; 193 }; 194 }; 195}; 196 197&dsi { 198 panel@0 { 199 reg = <0>; 200 201 ports { 202 #address-cells = <1>; 203 #size-cells = <0>; 204 205 port@0 { 206 reg = <0>; 207 208 panel_in_dsi: endpoint { 209 remote-endpoint = <&dsi_out_panel>; 210 }; 211 }; 212 }; 213 }; 214 215 ports { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 port@1 { 220 reg = <1>; 221 222 dsi_out_panel: endpoint { 223 remote-endpoint = <&panel_in_dsi>; 224 }; 225 }; 226 }; 227}; 228 229&i2s2 { 230 #sound-dai-cells = <0>; 231 rockchip,bclk-fs = <128>; 232}; 233 234&rkvdec { 235 status = "okay"; 236}; 237 238&vdec_mmu { 239 status = "okay"; 240}; 241 242&usbdrd_dwc3_0 { 243 dr_mode = "otg"; 244}; 245 246&iep { 247 status = "okay"; 248}; 249 250&iep_mmu { 251 status = "okay"; 252}; 253 254&mpp_srv { 255 status = "okay"; 256}; 257 258&vdpu { 259 status = "okay"; 260}; 261 262&vepu { 263 status = "okay"; 264}; 265 266&vpu_mmu { 267 status = "okay"; 268}; 269 270&pvtm { 271 status = "okay"; 272}; 273 274&rng { 275 status = "okay"; 276}; 277 278&pinctrl { 279 isp { 280 cif_clkout: cif-clkout { 281 rockchip,pins = 282 /*cif_clkout*/ 283 <2 RK_PB3 3 &pcfg_pull_none>; 284 }; 285 286 isp_dvp_d0d7: isp-dvp-d0d7 { 287 rockchip,pins = 288 /*cif_data0*/ 289 <2 RK_PA0 3 &pcfg_pull_none>, 290 /*cif_data1*/ 291 <2 RK_PA1 3 &pcfg_pull_none>, 292 /*cif_data2*/ 293 <2 RK_PA2 3 &pcfg_pull_none>, 294 /*cif_data3*/ 295 <2 RK_PA3 3 &pcfg_pull_none>, 296 /*cif_data4*/ 297 <2 RK_PA4 3 &pcfg_pull_none>, 298 /*cif_data5*/ 299 <2 RK_PA5 3 &pcfg_pull_none>, 300 /*cif_data6*/ 301 <2 RK_PA6 3 &pcfg_pull_none>, 302 /*cif_data7*/ 303 <2 RK_PA7 3 &pcfg_pull_none>, 304 /*cif_sync*/ 305 <2 RK_PB0 3 &pcfg_pull_none>, 306 /*cif_href*/ 307 <2 RK_PB1 3 &pcfg_pull_none>, 308 /*cif_clkin*/ 309 <2 RK_PB2 3 &pcfg_pull_none>; 310 }; 311 }; 312 313 buttons { 314 pwrbtn: pwrbtn { 315 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 316 }; 317 }; 318}; 319 320
