1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/rockchip-rga.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Rockchip 2D raster graphic acceleration controller (RGA) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: 10*4882a593Smuzhiyun RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D 11*4882a593Smuzhiyun graphics operations, such as point/line drawing, image scaling, rotation, 12*4882a593Smuzhiyun BitBLT, alpha blending and image blur/sharpness. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunmaintainers: 15*4882a593Smuzhiyun - Jacob Chen <jacob-chen@iotwrt.com> 16*4882a593Smuzhiyun - Ezequiel Garcia <ezequiel@collabora.com> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun oneOf: 21*4882a593Smuzhiyun - const: rockchip,rk3288-rga 22*4882a593Smuzhiyun - const: rockchip,rk3399-rga 23*4882a593Smuzhiyun - items: 24*4882a593Smuzhiyun - const: rockchip,rk3228-rga 25*4882a593Smuzhiyun - const: rockchip,rk3288-rga 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun maxItems: 3 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clock-names: 37*4882a593Smuzhiyun items: 38*4882a593Smuzhiyun - const: aclk 39*4882a593Smuzhiyun - const: hclk 40*4882a593Smuzhiyun - const: sclk 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun power-domains: 43*4882a593Smuzhiyun maxItems: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun resets: 46*4882a593Smuzhiyun maxItems: 3 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun reset-names: 49*4882a593Smuzhiyun items: 50*4882a593Smuzhiyun - const: core 51*4882a593Smuzhiyun - const: axi 52*4882a593Smuzhiyun - const: ahb 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunrequired: 55*4882a593Smuzhiyun - compatible 56*4882a593Smuzhiyun - reg 57*4882a593Smuzhiyun - interrupts 58*4882a593Smuzhiyun - clocks 59*4882a593Smuzhiyun - clock-names 60*4882a593Smuzhiyun - resets 61*4882a593Smuzhiyun - reset-names 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunadditionalProperties: false 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunexamples: 66*4882a593Smuzhiyun - | 67*4882a593Smuzhiyun #include <dt-bindings/clock/rk3399-cru.h> 68*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 69*4882a593Smuzhiyun #include <dt-bindings/power/rk3399-power.h> 70*4882a593Smuzhiyun rga: rga@ff680000 { 71*4882a593Smuzhiyun compatible = "rockchip,rk3399-rga"; 72*4882a593Smuzhiyun reg = <0xff680000 0x10000>; 73*4882a593Smuzhiyun interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 74*4882a593Smuzhiyun clocks = <&cru ACLK_RGA>, 75*4882a593Smuzhiyun <&cru HCLK_RGA>, 76*4882a593Smuzhiyun <&cru SCLK_RGA_CORE>; 77*4882a593Smuzhiyun clock-names = "aclk", "hclk", "sclk"; 78*4882a593Smuzhiyun power-domains = <&power RK3399_PD_RGA>; 79*4882a593Smuzhiyun resets = <&cru SRST_RGA_CORE>, 80*4882a593Smuzhiyun <&cru SRST_A_RGA>, 81*4882a593Smuzhiyun <&cru SRST_H_RGA>; 82*4882a593Smuzhiyun reset-names = "core", "axi", "ahb"; 83*4882a593Smuzhiyun }; 84