1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include "dt-bindings/pwm/pwm.h" 10#include "rk3399.dtsi" 11#include "rk3399-opp.dtsi" 12#include <dt-bindings/display/drm_mipi_dsi.h> 13#include <dt-bindings/input/input.h> 14#include "rk3399-vop-clk-set.dtsi" 15 16/ { 17 model = "Rockchip RK3399 Firefly Board (Android)"; 18 compatible = "rockchip,rk3399-firefly-android", "rockchip,rk3399"; 19 20 chosen: chosen { 21 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m"; 22 }; 23 24 cpuinfo { 25 compatible = "rockchip,cpuinfo"; 26 nvmem-cells = <&cpu_id>; 27 nvmem-cell-names = "id"; 28 }; 29 30 backlight: backlight { 31 compatible = "pwm-backlight"; 32 pwms = <&pwm0 0 25000 0>; 33 brightness-levels = < 34 0 1 2 3 4 5 6 7 35 8 9 10 11 12 13 14 15 36 16 17 18 19 20 21 22 23 37 24 25 26 27 28 29 30 31 38 32 33 34 35 36 37 38 39 39 40 41 42 43 44 45 46 47 40 48 49 50 51 52 53 54 55 41 56 57 58 59 60 61 62 63 42 64 65 66 67 68 69 70 71 43 72 73 74 75 76 77 78 79 44 80 81 82 83 84 85 86 87 45 88 89 90 91 92 93 94 95 46 96 97 98 99 100 101 102 103 47 104 105 106 107 108 109 110 111 48 112 113 114 115 116 117 118 119 49 120 121 122 123 124 125 126 127 50 128 129 130 131 132 133 134 135 51 136 137 138 139 140 141 142 143 52 144 145 146 147 148 149 150 151 53 152 153 154 155 156 157 158 159 54 160 161 162 163 164 165 166 167 55 168 169 170 171 172 173 174 175 56 176 177 178 179 180 181 182 183 57 184 185 186 187 188 189 190 191 58 192 193 194 195 196 197 198 199 59 200 201 202 203 204 205 206 207 60 208 209 210 211 212 213 214 215 61 216 217 218 219 220 221 222 223 62 224 225 226 227 228 229 230 231 63 232 233 234 235 236 237 238 239 64 240 241 242 243 244 245 246 247 65 248 249 250 251 252 253 254 255>; 66 default-brightness-level = <200>; 67 }; 68 69 clkin_gmac: external-gmac-clock { 70 compatible = "fixed-clock"; 71 clock-frequency = <125000000>; 72 clock-output-names = "clkin_gmac"; 73 #clock-cells = <0>; 74 }; 75 76 dw_hdmi_audio: dw-hdmi-audio { 77 status = "okay"; 78 compatible = "rockchip,dw-hdmi-audio"; 79 #sound-dai-cells = <0>; 80 }; 81 82 edp_panel: edp-panel { 83 compatible = "sharp,lcd-f402", "panel-simple"; 84 status = "okay"; 85 86 backlight = <&backlight>; 87 power-supply = <&vcc_lcd>; 88 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&lcd_panel_reset>; 91 92 ports { 93 panel_in_edp: endpoint { 94 remote-endpoint = <&edp_out_panel>; 95 }; 96 }; 97 }; 98 99 fiq_debugger: fiq-debugger { 100 compatible = "rockchip,fiq-debugger"; 101 rockchip,serial-id = <2>; 102 rockchip,wake-irq = <0>; 103 /* If enable uart uses irq instead of fiq */ 104 rockchip,irq-mode-enable = <0>; 105 /* Only 115200 and 1500000 */ 106 rockchip,baudrate = <1500000>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&uart2c_xfer>; 109 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 110 }; 111 112 reserved-memory { 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 drm_logo: drm-logo@00000000 { 118 compatible = "rockchip,drm-logo"; 119 reg = <0x0 0x0 0x0 0x0>; 120 }; 121 122 stb_devinfo: stb-devinfo@00000000 { 123 compatible = "rockchip,stb-devinfo"; 124 reg = <0x0 0x0 0x0 0x0>; 125 }; 126 127 ramoops: ramoops@110000 { 128 compatible = "ramoops"; 129 reg = <0x0 0x110000 0x0 0xf0000>; 130 record-size = <0x20000>; 131 console-size = <0x80000>; 132 ftrace-size = <0x00000>; 133 pmsg-size = <0x50000>; 134 }; 135 }; 136 137 rockchip-key { 138 compatible = "rockchip,key"; 139 status = "okay"; 140 141 io-channels = <&saradc 1>; 142 power-key { 143 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 144 linux,code = <116>; 145 label = "power"; 146 gpio-key,wakeup; 147 }; 148 }; 149 150 rt5640-sound { 151 compatible = "simple-audio-card"; 152 simple-audio-card,format = "i2s"; 153 simple-audio-card,name = "rockchip,rt5640-codec"; 154 simple-audio-card,mclk-fs = <256>; 155 simple-audio-card,widgets = 156 "Microphone", "Mic Jack", 157 "Headphone", "Headphone Jack"; 158 simple-audio-card,routing = 159 "Mic Jack", "MICBIAS1", 160 "IN1P", "Mic Jack", 161 "Headphone Jack", "HPOL", 162 "Headphone Jack", "HPOR"; 163 simple-audio-card,cpu { 164 sound-dai = <&i2s1>; 165 }; 166 simple-audio-card,codec { 167 sound-dai = <&rt5640>; 168 }; 169 }; 170 171 hdmi_sound: hdmi-sound { 172 status = "disabled"; 173 compatible = "simple-audio-card"; 174 simple-audio-card,format = "i2s"; 175 simple-audio-card,mclk-fs = <256>; 176 simple-audio-card,name = "rockchip,hdmi"; 177 178 simple-audio-card,cpu { 179 sound-dai = <&i2s2>; 180 }; 181 simple-audio-card,codec { 182 sound-dai = <&dw_hdmi_audio>; 183 }; 184 }; 185 186 hdmi_codec: hdmi-codec { 187 compatible = "simple-audio-card"; 188 simple-audio-card,format = "i2s"; 189 simple-audio-card,mclk-fs = <256>; 190 simple-audio-card,name = "HDMI-CODEC"; 191 192 simple-audio-card,cpu { 193 sound-dai = <&i2s2>; 194 }; 195 196 simple-audio-card,codec { 197 sound-dai = <&hdmi>; 198 }; 199 }; 200 201 rga: rga@ff680000 { 202 compatible = "rockchip,rga2"; 203 dev_mode = <1>; 204 reg = <0x0 0xff680000 0x0 0x1000>; 205 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 206 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 207 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 208 power-domains = <&power RK3399_PD_RGA>; 209 dma-coherent; 210 status = "okay"; 211 }; 212 213 spdif-sound { 214 compatible = "simple-audio-card"; 215 status = "okay"; 216 217 simple-audio-card,name = "ROCKCHIP,SPDIF"; 218 simple-audio-card,mclk-fs = <128>; 219 simple-audio-card,cpu { 220 sound-dai = <&spdif>; 221 }; 222 simple-audio-card,codec { 223 sound-dai = <&spdif_out>; 224 }; 225 }; 226 227 spdif_out: spdif-out { 228 compatible = "linux,spdif-dit"; 229 status = "okay"; 230 231 #sound-dai-cells = <0>; 232 }; 233 234 sdio_pwrseq: sdio-pwrseq { 235 compatible = "mmc-pwrseq-simple"; 236 clocks = <&rk808 1>; 237 clock-names = "ext_clock"; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&wifi_enable_h>; 240 241 /* 242 * On the module itself this is one of these (depending 243 * on the actual card populated): 244 * - SDIO_RESET_L_WL_REG_ON 245 * - PDN (power down when low) 246 */ 247 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ 248 }; 249 250 vcc3v3_pcie: vcc3v3-pcie-regulator { 251 compatible = "regulator-fixed"; 252 enable-active-high; 253 regulator-always-on; 254 regulator-boot-on; 255 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pcie_drv>; 258 regulator-name = "vcc3v3_pcie"; 259 }; 260 261 vcc3v3_sys: vcc3v3-sys { 262 compatible = "regulator-fixed"; 263 regulator-name = "vcc3v3_sys"; 264 regulator-always-on; 265 regulator-boot-on; 266 regulator-min-microvolt = <3300000>; 267 regulator-max-microvolt = <3300000>; 268 }; 269 270 vcc5v0_host: vcc5v0-host-regulator { 271 compatible = "regulator-fixed"; 272 enable-active-high; 273 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 274 pinctrl-names = "default"; 275 pinctrl-0 = <&host_vbus_drv>; 276 regulator-name = "vcc5v0_host"; 277 regulator-always-on; 278 }; 279 280 vcc5v0_sys: vcc5v0-sys { 281 compatible = "regulator-fixed"; 282 regulator-name = "vcc5v0_sys"; 283 regulator-always-on; 284 regulator-boot-on; 285 regulator-min-microvolt = <5000000>; 286 regulator-max-microvolt = <5000000>; 287 }; 288 289 vcc_phy: vcc-phy-regulator { 290 compatible = "regulator-fixed"; 291 regulator-name = "vcc_phy"; 292 regulator-always-on; 293 regulator-boot-on; 294 }; 295 296 vdd_log: vdd-log { 297 compatible = "pwm-regulator"; 298 pwms = <&pwm2 0 25000 1>; 299 regulator-name = "vdd_log"; 300 regulator-min-microvolt = <800000>; 301 /* 302 * the firefly hardware using 3.0 v as APIO2_VDD 303 * voltage, but the pwm divider resistance is designed 304 * based on hardware which the APIO2_VDD is 1.8v, so we 305 * need to change the regulator-max-microvolt from 1.4v 306 * to 1.0v, so the pwm can output 0.9v voltage. 307 */ 308 regulator-max-microvolt = <1000000>; 309 regulator-always-on; 310 regulator-boot-on; 311 312 /* for rockchip boot on */ 313 rockchip,pwm_id= <2>; 314 rockchip,pwm_voltage = <900000>; 315 }; 316 317 vccadc_ref: vccadc-ref { 318 compatible = "regulator-fixed"; 319 regulator-name = "vcc1v8_sys"; 320 regulator-always-on; 321 regulator-boot-on; 322 regulator-min-microvolt = <1800000>; 323 regulator-max-microvolt = <1800000>; 324 }; 325 326 vcc_lcd: vcc-lcd-regulator { 327 compatible = "regulator-fixed"; 328 regulator-always-on; 329 regulator-boot-on; 330 enable-active-high; 331 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&lcd_en>; 334 regulator-name = "vcc_lcd"; 335 }; 336 337 xin32k: xin32k { 338 compatible = "fixed-clock"; 339 clock-frequency = <32768>; 340 clock-output-names = "xin32k"; 341 #clock-cells = <0>; 342 }; 343 344 wireless-wlan { 345 compatible = "wlan-platdata"; 346 rockchip,grf = <&grf>; 347 wifi_chip_type = "ap6354"; 348 sdio_vref = <1800>; 349 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ 350 status = "okay"; 351 }; 352 353 wireless-bluetooth { 354 compatible = "bluetooth-platdata"; 355 //wifi-bt-power-toggle; 356 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ 357 pinctrl-names = "default", "rts_gpio"; 358 pinctrl-0 = <&uart0_rts>; 359 pinctrl-1 = <&uart0_gpios>; 360 //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ 361 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ 362 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ 363 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ 364 status = "okay"; 365 }; 366}; 367 368&cpu_l0 { 369 cpu-supply = <&vdd_cpu_l>; 370}; 371 372&cpu_l1 { 373 cpu-supply = <&vdd_cpu_l>; 374}; 375 376&cpu_l2 { 377 cpu-supply = <&vdd_cpu_l>; 378}; 379 380&cpu_l3 { 381 cpu-supply = <&vdd_cpu_l>; 382}; 383 384&cpu_b0 { 385 cpu-supply = <&vdd_cpu_b>; 386}; 387 388&cpu_b1 { 389 cpu-supply = <&vdd_cpu_b>; 390}; 391 392&display_subsystem { 393 status = "okay"; 394 395 ports = <&vopb_out>, <&vopl_out>; 396 logo-memory-region = <&drm_logo>; 397 398 route { 399 route_hdmi: route-hdmi { 400 status = "okay"; 401 logo,uboot = "logo.bmp"; 402 logo,kernel = "logo_kernel.bmp"; 403 logo,mode = "fullscreen"; 404 charge_logo,mode = "center"; 405 connect = <&vopl_out_hdmi>; 406 }; 407 408 route_edp: route-edp { 409 status = "okay"; 410 logo,uboot = "logo.bmp"; 411 logo,kernel = "logo_kernel.bmp"; 412 logo,mode = "fullscreen"; 413 charge_logo,mode = "center"; 414 connect = <&vopb_out_edp>; 415 }; 416 }; 417}; 418 419&edp { 420 status = "okay"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&edp_hpd>; 423 424 ports { 425 edp_out: port@1 { 426 reg = <1>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 430 edp_out_panel: endpoint@0 { 431 reg = <0>; 432 remote-endpoint = <&panel_in_edp>; 433 }; 434 }; 435 }; 436}; 437 438&emmc_phy { 439 status = "okay"; 440}; 441 442&gmac { 443 phy-supply = <&vcc_phy>; 444 phy-mode = "rgmii"; 445 clock_in_out = "input"; 446 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; 447 snps,reset-active-low; 448 snps,reset-delays-us = <0 10000 50000>; 449 assigned-clocks = <&cru SCLK_RMII_SRC>; 450 assigned-clock-parents = <&clkin_gmac>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&rgmii_pins>; 453 tx_delay = <0x28>; 454 rx_delay = <0x11>; 455 status = "okay"; 456}; 457 458&gpu { 459 status = "okay"; 460 mali-supply = <&vdd_gpu>; 461}; 462 463&hdmi { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 #sound-dai-cells = <0>; 467 status = "okay"; 468}; 469 470&i2c0 { 471 status = "okay"; 472 i2c-scl-rising-time-ns = <168>; 473 i2c-scl-falling-time-ns = <4>; 474 clock-frequency = <400000>; 475 476 vdd_cpu_b: syr827@40 { 477 compatible = "silergy,syr827"; 478 reg = <0x40>; 479 vin-supply = <&vcc5v0_sys>; 480 regulator-compatible = "fan53555-reg"; 481 regulator-name = "vdd_cpu_b"; 482 regulator-min-microvolt = <712500>; 483 regulator-max-microvolt = <1500000>; 484 regulator-ramp-delay = <1000>; 485 vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 486 fcs,suspend-voltage-selector = <1>; 487 regulator-always-on; 488 regulator-boot-on; 489 regulator-initial-state = <3>; 490 regulator-state-mem { 491 regulator-off-in-suspend; 492 }; 493 }; 494 495 vdd_gpu: syr828@41 { 496 compatible = "silergy,syr828"; 497 reg = <0x41>; 498 vin-supply = <&vcc5v0_sys>; 499 regulator-compatible = "fan53555-reg"; 500 regulator-name = "vdd_gpu"; 501 regulator-min-microvolt = <712500>; 502 regulator-max-microvolt = <1500000>; 503 regulator-ramp-delay = <1000>; 504 fcs,suspend-voltage-selector = <1>; 505 regulator-always-on; 506 regulator-boot-on; 507 regulator-initial-state = <3>; 508 regulator-state-mem { 509 regulator-off-in-suspend; 510 }; 511 }; 512 513 rk808: pmic@1b { 514 compatible = "rockchip,rk808"; 515 reg = <0x1b>; 516 interrupt-parent = <&gpio1>; 517 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 518 pinctrl-names = "default"; 519 pinctrl-0 = <&pmic_int_l &pmic_dvs2>; 520 rockchip,system-power-controller; 521 wakeup-source; 522 #clock-cells = <1>; 523 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 524 525 vcc1-supply = <&vcc3v3_sys>; 526 vcc2-supply = <&vcc3v3_sys>; 527 vcc3-supply = <&vcc3v3_sys>; 528 vcc4-supply = <&vcc3v3_sys>; 529 vcc6-supply = <&vcc3v3_sys>; 530 vcc7-supply = <&vcc3v3_sys>; 531 vcc8-supply = <&vcc3v3_sys>; 532 vcc9-supply = <&vcc3v3_sys>; 533 vcc10-supply = <&vcc3v3_sys>; 534 vcc11-supply = <&vcc3v3_sys>; 535 vcc12-supply = <&vcc3v3_sys>; 536 vddio-supply = <&vcc1v8_pmu>; 537 538 regulators { 539 vdd_center: DCDC_REG1 { 540 regulator-always-on; 541 regulator-boot-on; 542 regulator-min-microvolt = <750000>; 543 regulator-max-microvolt = <1350000>; 544 regulator-ramp-delay = <6001>; 545 regulator-name = "vdd_center"; 546 regulator-state-mem { 547 regulator-off-in-suspend; 548 }; 549 }; 550 551 vdd_cpu_l: DCDC_REG2 { 552 regulator-always-on; 553 regulator-boot-on; 554 regulator-min-microvolt = <750000>; 555 regulator-max-microvolt = <1350000>; 556 regulator-ramp-delay = <6001>; 557 regulator-name = "vdd_cpu_l"; 558 regulator-state-mem { 559 regulator-off-in-suspend; 560 }; 561 }; 562 563 vcc_ddr: DCDC_REG3 { 564 regulator-always-on; 565 regulator-boot-on; 566 regulator-name = "vcc_ddr"; 567 regulator-state-mem { 568 regulator-on-in-suspend; 569 }; 570 }; 571 572 vcc_1v8: DCDC_REG4 { 573 regulator-always-on; 574 regulator-boot-on; 575 regulator-min-microvolt = <1800000>; 576 regulator-max-microvolt = <1800000>; 577 regulator-name = "vcc_1v8"; 578 regulator-state-mem { 579 regulator-on-in-suspend; 580 regulator-suspend-microvolt = <1800000>; 581 }; 582 }; 583 584 vcc1v8_dvp: LDO_REG1 { 585 regulator-always-on; 586 regulator-boot-on; 587 regulator-min-microvolt = <1800000>; 588 regulator-max-microvolt = <1800000>; 589 regulator-name = "vcc1v8_dvp"; 590 regulator-state-mem { 591 regulator-off-in-suspend; 592 }; 593 }; 594 595 vcc3v0_tp: LDO_REG2 { 596 regulator-always-on; 597 regulator-boot-on; 598 regulator-min-microvolt = <3000000>; 599 regulator-max-microvolt = <3000000>; 600 regulator-name = "vcc3v0_tp"; 601 regulator-state-mem { 602 regulator-off-in-suspend; 603 }; 604 }; 605 606 vcc1v8_pmu: LDO_REG3 { 607 regulator-always-on; 608 regulator-boot-on; 609 regulator-min-microvolt = <1800000>; 610 regulator-max-microvolt = <1800000>; 611 regulator-name = "vcc1v8_pmu"; 612 regulator-state-mem { 613 regulator-on-in-suspend; 614 regulator-suspend-microvolt = <1800000>; 615 }; 616 }; 617 618 vcc_sd: LDO_REG4 { 619 regulator-always-on; 620 regulator-boot-on; 621 regulator-min-microvolt = <1800000>; 622 regulator-max-microvolt = <3000000>; 623 regulator-name = "vcc_sd"; 624 regulator-state-mem { 625 regulator-on-in-suspend; 626 regulator-suspend-microvolt = <3000000>; 627 }; 628 }; 629 630 vcca3v0_codec: LDO_REG5 { 631 regulator-always-on; 632 regulator-boot-on; 633 regulator-min-microvolt = <3000000>; 634 regulator-max-microvolt = <3000000>; 635 regulator-name = "vcca3v0_codec"; 636 regulator-state-mem { 637 regulator-off-in-suspend; 638 }; 639 }; 640 641 vcc_1v5: LDO_REG6 { 642 regulator-always-on; 643 regulator-boot-on; 644 regulator-min-microvolt = <1500000>; 645 regulator-max-microvolt = <1500000>; 646 regulator-name = "vcc_1v5"; 647 regulator-state-mem { 648 regulator-on-in-suspend; 649 regulator-suspend-microvolt = <1500000>; 650 }; 651 }; 652 653 vcca1v8_codec: LDO_REG7 { 654 regulator-always-on; 655 regulator-boot-on; 656 regulator-min-microvolt = <1800000>; 657 regulator-max-microvolt = <1800000>; 658 regulator-name = "vcca1v8_codec"; 659 regulator-state-mem { 660 regulator-off-in-suspend; 661 }; 662 }; 663 664 vcc_3v0: LDO_REG8 { 665 regulator-always-on; 666 regulator-boot-on; 667 regulator-min-microvolt = <3000000>; 668 regulator-max-microvolt = <3000000>; 669 regulator-name = "vcc_3v0"; 670 regulator-state-mem { 671 regulator-on-in-suspend; 672 regulator-suspend-microvolt = <3000000>; 673 }; 674 }; 675 676 vcc3v3_s3: SWITCH_REG1 { 677 regulator-always-on; 678 regulator-boot-on; 679 regulator-name = "vcc3v3_s3"; 680 regulator-state-mem { 681 regulator-off-in-suspend; 682 }; 683 }; 684 685 vcc3v3_s0: SWITCH_REG2 { 686 regulator-always-on; 687 regulator-boot-on; 688 regulator-name = "vcc3v3_s0"; 689 regulator-state-mem { 690 regulator-off-in-suspend; 691 }; 692 }; 693 }; 694 }; 695}; 696 697&i2c1 { 698 status = "okay"; 699 i2c-scl-rising-time-ns = <300>; 700 i2c-scl-falling-time-ns = <15>; 701 702 rt5640: rt5640@1c { 703 #sound-dai-cells = <0>; 704 compatible = "realtek,rt5640"; 705 reg = <0x1c>; 706 clocks = <&cru SCLK_I2S_8CH_OUT>; 707 clock-names = "mclk"; 708 realtek,in1-differential; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>; 711 hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 712 //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; 713 io-channels = <&saradc 4>; 714 hp-det-adc-value = <500>; 715 status = "okay"; 716 }; 717}; 718 719&i2c3 { 720 status = "okay"; 721 i2c-scl-rising-time-ns = <450>; 722 i2c-scl-falling-time-ns = <15>; 723}; 724 725&i2c4 { 726 status = "okay"; 727 i2c-scl-rising-time-ns = <600>; 728 i2c-scl-falling-time-ns = <20>; 729 730 fusb0: fusb30x@22 { 731 compatible = "fairchild,fusb302"; 732 reg = <0x22>; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&fusb0_int>; 735 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 736 vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; 737 status = "okay"; 738 }; 739 740 gsl3680: gsl3680@41 { 741 compatible = "gslX680-pad"; 742 reg = <0x41>; 743 screen_max_x = <1536>; 744 screen_max_y = <2048>; 745 touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; 746 reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; 747 status = "okay"; 748 }; 749 750 mpu6050: mpu@68 { 751 compatible = "invensense,mpu6050"; 752 reg = <0x68>; 753 mpu-int_config = <0x10>; 754 mpu-level_shifter = <0>; 755 mpu-orientation = <0 1 0 1 0 0 0 0 1>; 756 orientation-x= <1>; 757 orientation-y= <1>; 758 orientation-z= <1>; 759 irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>; 760 mpu-debug = <1>; 761 status = "okay"; 762 }; 763}; 764 765&i2s0 { 766 status = "okay"; 767 rockchip,i2s-broken-burst-len; 768 rockchip,playback-channels = <8>; 769 rockchip,capture-channels = <8>; 770 #sound-dai-cells = <0>; 771}; 772 773&i2s1 { 774 status = "okay"; 775 rockchip,i2s-broken-burst-len; 776 rockchip,playback-channels = <2>; 777 rockchip,capture-channels = <2>; 778 #sound-dai-cells = <0>; 779}; 780 781&i2s2 { 782 #sound-dai-cells = <0>; 783 status = "okay"; 784}; 785 786&io_domains { 787 status = "okay"; 788 789 bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ 790 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ 791 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ 792 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ 793}; 794 795&pcie_phy { 796 status = "okay"; 797}; 798 799&pcie0 { 800 ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 801 num-lanes = <4>; 802 pinctrl-names = "default"; 803 pinctrl-0 = <&pcie_clkreqn_cpm>; 804 status = "okay"; 805}; 806 807&pmu_io_domains { 808 status = "okay"; 809 pmu1830-supply = <&vcc_3v0>; 810}; 811 812&pinctrl { 813 814 lcd-panel { 815 lcd_panel_reset: lcd-panel-reset { 816 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 817 }; 818 819 lcd_en: lcd-en { 820 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 821 }; 822 }; 823 824 pcie { 825 pcie_drv: pcie-drv { 826 rockchip,pins = 827 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 828 }; 829 pcie_3g_drv: pcie-3g-drv { 830 rockchip,pins = 831 <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 832 }; 833 }; 834 835 pmic { 836 vsel1_gpio: vsel1-gpio { 837 rockchip,pins = 838 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 839 }; 840 841 vsel2_gpio: vsel2-gpio { 842 rockchip,pins = 843 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 844 }; 845 }; 846 847 sdio-pwrseq { 848 wifi_enable_h: wifi-enable-h { 849 rockchip,pins = 850 <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 851 }; 852 }; 853 854 wireless-bluetooth { 855 uart0_gpios: uart0-gpios { 856 rockchip,pins = 857 <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 858 }; 859 }; 860 861 rt5640 { 862 rt5640_hpcon: rt5640-hpcon { 863 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 864 }; 865 }; 866 867 pmic { 868 pmic_int_l: pmic-int-l { 869 rockchip,pins = 870 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 871 }; 872 873 pmic_dvs2: pmic-dvs2 { 874 rockchip,pins = 875 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 876 }; 877 }; 878 879 usb2 { 880 host_vbus_drv: host-vbus-drv { 881 rockchip,pins = 882 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 883 }; 884 }; 885 886 fusb30x { 887 fusb0_int: fusb0-int { 888 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 889 }; 890 }; 891}; 892 893&pwm0 { 894 status = "okay"; 895}; 896 897&pwm2 { 898 status = "okay"; 899 pinctrl-names = "active"; 900 pinctrl-0 = <&pwm2_pin_pull_down>; 901}; 902 903&rockchip_suspend { 904 rockchip,power-ctrl = 905 <&gpio1 18 GPIO_ACTIVE_LOW>, 906 <&gpio1 14 GPIO_ACTIVE_HIGH>; 907}; 908 909&saradc { 910 status = "okay"; 911 vref-supply = <&vccadc_ref>; 912}; 913 914&sdhci { 915 bus-width = <8>; 916 keep-power-in-suspend; 917 mmc-hs400-1_8v; 918 mmc-hs400-enhanced-strobe; 919 non-removable; 920 status = "okay"; 921 no-sdio; 922 no-sd; 923}; 924 925&sdmmc { 926 max-frequency = <150000000>; 927 no-sdio; 928 no-mmc; 929 bus-width = <4>; 930 cap-mmc-highspeed; 931 cap-sd-highspeed; 932 disable-wp; 933 num-slots = <1>; 934 vqmmc-supply = <&vcc_sd>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 937 status = "okay"; 938}; 939 940&sdio0 { 941 max-frequency = <50000000>; 942 no-sd; 943 no-mmc; 944 bus-width = <4>; 945 disable-wp; 946 cap-sd-highspeed; 947 keep-power-in-suspend; 948 mmc-pwrseq = <&sdio_pwrseq>; 949 non-removable; 950 num-slots = <1>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 953 sd-uhs-sdr104; 954 status = "okay"; 955}; 956 957&spdif { 958 status = "okay"; 959 pinctrl-0 = <&spdif_bus_1>; 960 i2c-scl-rising-time-ns = <450>; 961 i2c-scl-falling-time-ns = <15>; 962 #sound-dai-cells = <0>; 963}; 964 965&tcphy0 { 966 extcon = <&fusb0>; 967 status = "okay"; 968}; 969 970&tcphy1 { 971 status = "okay"; 972}; 973 974&tsadc { 975 /* tshut mode 0:CRU 1:GPIO */ 976 rockchip,hw-tshut-mode = <1>; 977 /* tshut polarity 0:LOW 1:HIGH */ 978 rockchip,hw-tshut-polarity = <1>; 979 status = "okay"; 980}; 981 982&u2phy0 { 983 status = "okay"; 984 extcon = <&fusb0>; 985 986 u2phy0_otg: otg-port { 987 status = "okay"; 988 }; 989 990 u2phy0_host: host-port { 991 phy-supply = <&vcc5v0_host>; 992 status = "okay"; 993 }; 994}; 995 996&u2phy1 { 997 status = "okay"; 998 999 u2phy1_otg: otg-port { 1000 status = "okay"; 1001 }; 1002 1003 u2phy1_host: host-port { 1004 phy-supply = <&vcc5v0_host>; 1005 status = "okay"; 1006 }; 1007}; 1008 1009&uart0 { 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&uart0_xfer &uart0_cts>; 1012 status = "okay"; 1013}; 1014 1015&uart2 { 1016 status = "okay"; 1017}; 1018 1019&usbdrd3_0 { 1020 status = "okay"; 1021}; 1022 1023&usbdrd3_1 { 1024 status = "okay"; 1025}; 1026 1027&usbdrd_dwc3_0 { 1028 status = "okay"; 1029 extcon = <&fusb0>; 1030}; 1031 1032&usbdrd_dwc3_1 { 1033 status = "okay"; 1034 dr_mode = "host"; 1035}; 1036 1037&usb_host0_ehci { 1038 status = "okay"; 1039}; 1040 1041&usb_host0_ohci { 1042 status = "okay"; 1043}; 1044 1045&usb_host1_ehci { 1046 status = "okay"; 1047}; 1048 1049&usb_host1_ohci { 1050 status = "okay"; 1051}; 1052 1053&vopb { 1054 status = "okay"; 1055}; 1056 1057&vopb_mmu { 1058 status = "okay"; 1059}; 1060 1061&vopl { 1062 status = "okay"; 1063}; 1064 1065&vopl_mmu { 1066 status = "okay"; 1067}; 1068
