1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 8*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 9*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi" 10*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "rockchip,android", "rockchip,rk3399"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen: chosen { 16*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m"; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpuinfo { 20*4882a593Smuzhiyun compatible = "rockchip,cpuinfo"; 21*4882a593Smuzhiyun nvmem-cells = <&cpu_id>; 22*4882a593Smuzhiyun nvmem-cell-names = "id"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun fiq_debugger: fiq-debugger { 26*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 27*4882a593Smuzhiyun rockchip,serial-id = <2>; 28*4882a593Smuzhiyun rockchip,wake-irq = <0>; 29*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ 30*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&uart2c_xfer>; 33*4882a593Smuzhiyun interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun reserved-memory { 37*4882a593Smuzhiyun #address-cells = <2>; 38*4882a593Smuzhiyun #size-cells = <2>; 39*4882a593Smuzhiyun ranges; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun drm_logo: drm-logo@00000000 { 42*4882a593Smuzhiyun compatible = "rockchip,drm-logo"; 43*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun vendor_storage_rm: vendor-storage-rm@00000000 { 47*4882a593Smuzhiyun compatible = "rockchip,vendor-storage-rm"; 48*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ramoops: ramoops@110000 { 52*4882a593Smuzhiyun compatible = "ramoops"; 53*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 54*4882a593Smuzhiyun record-size = <0x20000>; 55*4882a593Smuzhiyun console-size = <0x80000>; 56*4882a593Smuzhiyun ftrace-size = <0x00000>; 57*4882a593Smuzhiyun pmsg-size = <0x50000>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun secure_memory: secure-memory@20000000 { 61*4882a593Smuzhiyun compatible = "rockchip,secure-memory"; 62*4882a593Smuzhiyun reg = <0x0 0x20000000 0x0 0x10000000>; 63*4882a593Smuzhiyun status = "disabled"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun stb_devinfo: stb-devinfo@00000000 { 67*4882a593Smuzhiyun compatible = "rockchip,stb-devinfo"; 68*4882a593Smuzhiyun reg = <0x0 0x0 0x0 0x0>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun gpio_keys: gpio-keys { 73*4882a593Smuzhiyun compatible = "gpio-keys"; 74*4882a593Smuzhiyun autorepeat; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&pwrbtn>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun power { 79*4882a593Smuzhiyun debounce-interval = <100>; 80*4882a593Smuzhiyun gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 81*4882a593Smuzhiyun label = "GPIO Key Power"; 82*4882a593Smuzhiyun linux,code = <KEY_POWER>; 83*4882a593Smuzhiyun wakeup-source; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun vendor_storage: vendor-storage { 88*4882a593Smuzhiyun compatible = "rockchip,ram-vendor-storage"; 89*4882a593Smuzhiyun memory-region = <&vendor_storage_rm>; 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun rga: rga@ff680000 { 94*4882a593Smuzhiyun compatible = "rockchip,rga2"; 95*4882a593Smuzhiyun dev_mode = <1>; 96*4882a593Smuzhiyun reg = <0x0 0xff680000 0x0 0x1000>; 97*4882a593Smuzhiyun interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 98*4882a593Smuzhiyun clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 99*4882a593Smuzhiyun clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 100*4882a593Smuzhiyun power-domains = <&power RK3399_PD_RGA>; 101*4882a593Smuzhiyun status = "okay"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun hdmi_dp_sound: hdmi-dp-sound { 105*4882a593Smuzhiyun status = "disabled"; 106*4882a593Smuzhiyun compatible = "rockchip,rk3399-hdmi-dp"; 107*4882a593Smuzhiyun rockchip,cpu = <&i2s2>; 108*4882a593Smuzhiyun rockchip,codec = <&hdmi>, <&cdn_dp>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun firmware { 112*4882a593Smuzhiyun firmware_android: android {}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun optee: optee { 115*4882a593Smuzhiyun compatible = "linaro,optee-tz"; 116*4882a593Smuzhiyun method = "smc"; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&uart2 { 122*4882a593Smuzhiyun status = "disabled"; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&vopb { 126*4882a593Smuzhiyun support-multi-area; 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&vopb_mmu { 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&vopl { 135*4882a593Smuzhiyun support-multi-area; 136*4882a593Smuzhiyun status = "okay"; 137*4882a593Smuzhiyun}; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun&vopl_mmu { 140*4882a593Smuzhiyun status = "okay"; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&hdmi { 144*4882a593Smuzhiyun #address-cells = <1>; 145*4882a593Smuzhiyun #size-cells = <0>; 146*4882a593Smuzhiyun #sound-dai-cells = <0>; 147*4882a593Smuzhiyun ddc-i2c-scl-high-time-ns = <9625>; 148*4882a593Smuzhiyun ddc-i2c-scl-low-time-ns = <10000>; 149*4882a593Smuzhiyun status = "okay"; 150*4882a593Smuzhiyun}; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun&display_subsystem { 153*4882a593Smuzhiyun status = "okay"; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun ports = <&vopb_out>, <&vopl_out>; 156*4882a593Smuzhiyun logo-memory-region = <&drm_logo>; 157*4882a593Smuzhiyun secure-memory-region = <&secure_memory>; 158*4882a593Smuzhiyun route { 159*4882a593Smuzhiyun route_hdmi: route-hdmi { 160*4882a593Smuzhiyun status = "disabled"; 161*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 162*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 163*4882a593Smuzhiyun logo,mode = "center"; 164*4882a593Smuzhiyun charge_logo,mode = "center"; 165*4882a593Smuzhiyun connect = <&vopb_out_hdmi>; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun route_dsi: route-dsi { 169*4882a593Smuzhiyun status = "disabled"; 170*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 171*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 172*4882a593Smuzhiyun logo,mode = "center"; 173*4882a593Smuzhiyun charge_logo,mode = "center"; 174*4882a593Smuzhiyun connect = <&vopb_out_dsi>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun route_dsi1: route-dsi1 { 178*4882a593Smuzhiyun status = "disabled"; 179*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 180*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 181*4882a593Smuzhiyun logo,mode = "center"; 182*4882a593Smuzhiyun charge_logo,mode = "center"; 183*4882a593Smuzhiyun connect = <&vopl_out_dsi1>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun route_edp: route-edp { 187*4882a593Smuzhiyun status = "disabled"; 188*4882a593Smuzhiyun logo,uboot = "logo.bmp"; 189*4882a593Smuzhiyun logo,kernel = "logo_kernel.bmp"; 190*4882a593Smuzhiyun logo,mode = "center"; 191*4882a593Smuzhiyun charge_logo,mode = "center"; 192*4882a593Smuzhiyun connect = <&vopb_out_edp>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun}; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&dsi { 198*4882a593Smuzhiyun panel@0 { 199*4882a593Smuzhiyun reg = <0>; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun ports { 202*4882a593Smuzhiyun #address-cells = <1>; 203*4882a593Smuzhiyun #size-cells = <0>; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun port@0 { 206*4882a593Smuzhiyun reg = <0>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun panel_in_dsi: endpoint { 209*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun }; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun ports { 216*4882a593Smuzhiyun #address-cells = <1>; 217*4882a593Smuzhiyun #size-cells = <0>; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun port@1 { 220*4882a593Smuzhiyun reg = <1>; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun dsi_out_panel: endpoint { 223*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&i2s2 { 230*4882a593Smuzhiyun #sound-dai-cells = <0>; 231*4882a593Smuzhiyun rockchip,bclk-fs = <128>; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&rkvdec { 235*4882a593Smuzhiyun status = "okay"; 236*4882a593Smuzhiyun}; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun&vdec_mmu { 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&usbdrd_dwc3_0 { 243*4882a593Smuzhiyun dr_mode = "otg"; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&iep { 247*4882a593Smuzhiyun status = "okay"; 248*4882a593Smuzhiyun}; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun&iep_mmu { 251*4882a593Smuzhiyun status = "okay"; 252*4882a593Smuzhiyun}; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun&mpp_srv { 255*4882a593Smuzhiyun status = "okay"; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&vdpu { 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&vepu { 263*4882a593Smuzhiyun status = "okay"; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun&vpu_mmu { 267*4882a593Smuzhiyun status = "okay"; 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&pvtm { 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&rng { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&pinctrl { 279*4882a593Smuzhiyun isp { 280*4882a593Smuzhiyun cif_clkout: cif-clkout { 281*4882a593Smuzhiyun rockchip,pins = 282*4882a593Smuzhiyun /*cif_clkout*/ 283*4882a593Smuzhiyun <2 RK_PB3 3 &pcfg_pull_none>; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun isp_dvp_d0d7: isp-dvp-d0d7 { 287*4882a593Smuzhiyun rockchip,pins = 288*4882a593Smuzhiyun /*cif_data0*/ 289*4882a593Smuzhiyun <2 RK_PA0 3 &pcfg_pull_none>, 290*4882a593Smuzhiyun /*cif_data1*/ 291*4882a593Smuzhiyun <2 RK_PA1 3 &pcfg_pull_none>, 292*4882a593Smuzhiyun /*cif_data2*/ 293*4882a593Smuzhiyun <2 RK_PA2 3 &pcfg_pull_none>, 294*4882a593Smuzhiyun /*cif_data3*/ 295*4882a593Smuzhiyun <2 RK_PA3 3 &pcfg_pull_none>, 296*4882a593Smuzhiyun /*cif_data4*/ 297*4882a593Smuzhiyun <2 RK_PA4 3 &pcfg_pull_none>, 298*4882a593Smuzhiyun /*cif_data5*/ 299*4882a593Smuzhiyun <2 RK_PA5 3 &pcfg_pull_none>, 300*4882a593Smuzhiyun /*cif_data6*/ 301*4882a593Smuzhiyun <2 RK_PA6 3 &pcfg_pull_none>, 302*4882a593Smuzhiyun /*cif_data7*/ 303*4882a593Smuzhiyun <2 RK_PA7 3 &pcfg_pull_none>, 304*4882a593Smuzhiyun /*cif_sync*/ 305*4882a593Smuzhiyun <2 RK_PB0 3 &pcfg_pull_none>, 306*4882a593Smuzhiyun /*cif_href*/ 307*4882a593Smuzhiyun <2 RK_PB1 3 &pcfg_pull_none>, 308*4882a593Smuzhiyun /*cif_clkin*/ 309*4882a593Smuzhiyun <2 RK_PB2 3 &pcfg_pull_none>; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun buttons { 314*4882a593Smuzhiyun pwrbtn: pwrbtn { 315*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun}; 319*4882a593Smuzhiyun 320