1 /*
2 * Copyright (c) 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/grf_rk3562.h>
13 #include <asm/arch/ioc_rk3562.h>
14 #include <asm/arch/rk_atags.h>
15 #include <linux/libfdt.h>
16 #include <fdt_support.h>
17 #include <asm/arch/clock.h>
18 #include <dt-bindings/clock/rk3562-cru.h>
19 #include <asm/arch-rockchip/rockchip_smccc.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 #define FIREWALL_DDR_BASE 0xfef00000
24 #define FW_DDR_MST3_REG 0x2c /* usb */
25 #define FW_DDR_MST4_REG 0x30 /* emmc */
26 #define FW_DDR_MST5_REG 0x34 /* fspi */
27 #define FW_DDR_MST6_REG 0x38 /* sdmmc mcu */
28 #define FW_DDR_CON_REG 0x80
29
30 #define PMU_GRF_BASE 0xff010000
31 #define PMU_GRF_SOC_CON9 0x0124
32
33 #define SYS_GRF_BASE 0xff030000
34 #define SYS_GRF_SOC_CON5 0x0414
35 #define SYS_GRF_SOC_CON6 0x0418
36
37 #define PERI_GRF_BASE 0xff040000
38 #define PERI_GRF_AUDIO_CON 0x0070
39
40 #define PIPEPHY_GRF_BASE 0xff098000
41 #define PIPEPHY_PIPE_CON5 0x0014
42
43 #define TOP_CRU_BASE 0xff100000
44 #define TOP_CRU_GATE_CON23 0x035c
45 #define TOP_CRU_SOFTRST_CON23 0x045c
46 #define TOP_CRU_CM0_GATEMASK 0x0680
47
48 #define PMU0_CRU_BASE 0xff110000
49
50 #define PMU1_CRU_BASE 0xff118000
51 #define PMU1_CRU_GATE_CON02 0x0188
52 #define PMU1_CRU_SOFTRST_CON02 0x0208
53 #define PMU1_CRU_CM0_GATEMASK 0x0420
54
55 #define PMU_BASE_ADDR 0xff258000
56 #define PMU2_BIU_IDLE_SFTCON0 0x110
57 #define PMU2_BIU_IDLE_ACK_STS0 0x120
58 #define PMU2_BIT_IDLE_STS0 0x128
59 #define PMU2_PWR_GATE_SFTCON0 0x210
60 #define PMU2_PWR_GATE_STS0 0x230
61 #define PMU2_MEM_SD_SFTCON0 0x300
62 /* PMU2_PWR_GATE_SFTCON0 */
63 #define PD_GPU_DWN_SFTENA BIT(0)
64 #define PD_VI_DWN_SFTENA BIT(5)
65 #define PD_VO_DWN_SFTENA BIT(6)
66 /* PMU2_BIU_IDLE_SFTCON0 */
67 #define IDLE_REQ_GPU_SFTENA BIT(1)
68 #define IDLE_REQ_VI_SFTENA BIT(3)
69 #define IDLE_REQ_VO_SFTENA BIT(4)
70 /* PMU2_BIU_IDLE_ACK_STS0 */
71 #define IDLE_ACK_GPU BIT(1)
72 #define IDLE_ACK_VI BIT(3)
73 #define IDLE_ACK_VO BIT(4)
74 /* PMU2_BIT_IDLE_STS0 */
75 #define IDLE_GPU BIT(1)
76 #define IDLE_VI BIT(3)
77 #define IDLE_VO BIT(4)
78
79 #define CRYPTO_PRIORITY_REG 0xfeeb0108
80 #define DCF_PRIORITY_REG 0xfee10408
81 #define DMA2DDR_PRIORITY_REG 0xfee03808
82 #define DMAC_PRIORITY_REG 0xfeeb0208
83 #define EMMC_PRIORITY_REG 0xfeeb0308
84 #define FSPI_PRIORITY_REG 0xfeeb0408
85 #define GMAC_PRIORITY_REG 0xfee10208
86 #define GPU_PRIORITY_REG 0xfee30008
87 #define ISP_PRIORITY_REG 0xfee70008
88 #define MAC100_PRIORITY_REG 0xfee10308
89 #define MCU_PRIORITY_REG 0xfee10008
90 #define PCIE_PRIORITY_REG 0xfeea0008
91 #define RKDMA_PRIORITY_REG 0xfeeb0508
92 #define SDMMC0_PRIORITY_REG 0xfeeb0608
93 #define SDMMC1_PRIORITY_REG 0xfeeb0708
94 #define USB2_PRIORITY_REG 0xfeeb0808
95 #define USB3_PRIORITY_REG 0xfeea0108
96 #define VICAP_PRIORITY_REG 0xfee70108
97 #define VOP_PRIORITY_REG 0xfee80008
98
99 #define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
100
101 #ifdef CONFIG_ARM64
102 #include <asm/armv8/mmu.h>
103
104 static struct mm_region rk3562_mem_map[] = {
105 {
106 .virt = 0x0UL,
107 .phys = 0x0UL,
108 .size = 0xfc000000UL,
109 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
110 PTE_BLOCK_INNER_SHARE
111 }, {
112 .virt = 0xfc000000UL,
113 .phys = 0xfc000000UL,
114 .size = 0x04000000UL,
115 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
116 PTE_BLOCK_NON_SHARE |
117 PTE_BLOCK_PXN | PTE_BLOCK_UXN
118 }, {
119 /* List terminator */
120 0,
121 }
122 };
123
124 struct mm_region *mem_map = rk3562_mem_map;
125 #endif
126
127 #define GPIO0_IOC_BASE 0xFF080000
128 #define GPIO1_IOC_BASE 0xFF060000
129 #define GPIO1A_IOMUX_SEL_L 0x0
130 #define GPIO1A_IOMUX_SEL_H 0x4
131 #define GPIO1B_IOMUX_SEL_L 0x8
132 #define GPIO1_IOC_GPIO1A_DS0 0x200
133 #define GPIO1_IOC_GPIO1A_DS1 0x204
134 #define GPIO1_IOC_GPIO1B_DS0 0x210
135
136 #define GPIO2_IOC_BASE 0xFF060000
137 #define GPIO2_IOC_IO_VSEL0 0x300
138 /* GPIO2_IOC_IO_VSEL0 */
139 #define POC_VCCIO2_VD_3V3 BIT(12)
140
141 #define GPIO3_IOC_BASE 0xFF070000
142 #define GPIO4_IOC_BASE 0xFF070000
143
144 /* UART0 iomux */
145 /* gpio0d0_sel */
146 #define UART0_RX_M0 1
147 #define UART0_RX_M0_OFFSET 0
148 #define UART0_RX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
149 /* gpio0d1_sel */
150 #define UART0_TX_M0 1
151 #define UART0_TX_M0_OFFSET 4
152 #define UART0_TX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
153
154 /* gpio1b3_sel */
155 #define UART0_RX_M1 2
156 #define UART0_RX_M1_OFFSET 12
157 #define UART0_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
158 /* gpio1b4_sel */
159 #define UART0_TX_M1 2
160 #define UART0_TX_M1_OFFSET 0
161 #define UART0_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
162
163 /* UART1 iomux */
164 /* gpio1d1_sel */
165 #define UART1_RX_M0 1
166 #define UART1_RX_M0_OFFSET 4
167 #define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
168 /* gpio1d2_sel */
169 #define UART1_TX_M0 1
170 #define UART1_TX_M0_OFFSET 8
171 #define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
172
173 /* gpio4a6_sel */
174 #define UART1_RX_M1 4
175 #define UART1_RX_M1_OFFSET 8
176 #define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
177 /* gpio4a5_sel */
178 #define UART1_TX_M1 4
179 #define UART1_TX_M1_OFFSET 4
180 #define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
181
182 /* UART2 iomux */
183 /* gpio0c1_sel */
184 #define UART2_RX_M0 1
185 #define UART2_RX_M0_OFFSET 4
186 #define UART2_RX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
187 /* gpio0c0_sel */
188 #define UART2_TX_M0 1
189 #define UART2_TX_M0_OFFSET 0
190 #define UART2_TX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
191
192 /* gpio3a1_sel */
193 #define UART2_RX_M1 2
194 #define UART2_RX_M1_OFFSET 4
195 #define UART2_RX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
196 /* gpio3a0_sel */
197 #define UART2_TX_M1 2
198 #define UART2_TX_M1_OFFSET 0
199 #define UART2_TX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
200
201 /* UART3 iomux */
202 /* gpio4b5_sel */
203 #define UART3_RX_M0 7
204 #define UART3_RX_M0_OFFSET 4
205 #define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
206 /* gpio4b4_sel */
207 #define UART3_TX_M0 7
208 #define UART3_TX_M0_OFFSET 0
209 #define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
210
211 /* gpio3c0_sel */
212 #define UART3_RX_M1 3
213 #define UART3_RX_M1_OFFSET 0
214 #define UART3_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
215 /* gpio3b7_sel */
216 #define UART3_TX_M1 3
217 #define UART3_TX_M1_OFFSET 12
218 #define UART3_TX_M1_ADDR (GPIO3_IOC_BASE + 0x4C)
219
220 /* UART4 iomux */
221 /* gpio3d1_sel */
222 #define UART4_RX_M0 4
223 #define UART4_RX_M0_OFFSET 4
224 #define UART4_RX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
225 /* gpio3d0_sel */
226 #define UART4_TX_M0 4
227 #define UART4_TX_M0_OFFSET 0
228 #define UART4_TX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
229
230 /* gpio1d5_sel */
231 #define UART4_RX_M1 3
232 #define UART4_RX_M1_OFFSET 4
233 #define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
234 /* gpio1d6_sel */
235 #define UART4_TX_M1 3
236 #define UART4_TX_M1_OFFSET 8
237 #define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
238
239 /* UART5 iomux */
240 /* gpio1b7_sel */
241 #define UART5_RX_M0 3
242 #define UART5_RX_M0_OFFSET 12
243 #define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0xC)
244 /* gpio1c0_sel */
245 #define UART5_TX_M0 3
246 #define UART5_TX_M0_OFFSET 0
247 #define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x10)
248
249 /* gpio3a7_sel */
250 #define UART5_RX_M1 5
251 #define UART5_RX_M1_OFFSET 12
252 #define UART5_RX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
253 /* gpio3a6_sel */
254 #define UART5_TX_M1 5
255 #define UART5_TX_M1_OFFSET 8
256 #define UART5_TX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
257
258 /* UART6 iomux */
259 /* gpio0c7_sel */
260 #define UART6_RX_M0 1
261 #define UART6_RX_M0_OFFSET 12
262 #define UART6_RX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
263 /* gpio0c6_sel */
264 #define UART6_TX_M0 1
265 #define UART6_TX_M0_OFFSET 8
266 #define UART6_TX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
267
268 /* gpio4b0_sel */
269 #define UART6_RX_M1 6
270 #define UART6_RX_M1_OFFSET 0
271 #define UART6_RX_M1_ADDR (GPIO4_IOC_BASE + 0x68)
272 /* gpio4a7_sel */
273 #define UART6_TX_M1 6
274 #define UART6_TX_M1_OFFSET 12
275 #define UART6_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
276
277 /* UART7 iomux */
278 /* gpio3c7_sel */
279 #define UART7_RX_M0 4
280 #define UART7_RX_M0_OFFSET 12
281 #define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
282 /* gpio3c4_sel */
283 #define UART7_TX_M0 4
284 #define UART7_TX_M0_OFFSET 0
285 #define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
286
287 /* gpio1b3_sel */
288 #define UART7_RX_M1 3
289 #define UART7_RX_M1_OFFSET 12
290 #define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
291 /* gpio1b4_sel */
292 #define UART7_TX_M1 3
293 #define UART7_TX_M1_OFFSET 0
294 #define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
295
296 /* UART8 iomux */
297 /* gpio3b3_sel */
298 #define UART8_RX_M0 3
299 #define UART8_RX_M0_OFFSET 12
300 #define UART8_RX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
301 /* gpio3b2_sel */
302 #define UART8_TX_M0 3
303 #define UART8_TX_M0_OFFSET 8
304 #define UART8_TX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
305
306 /* gpio3d5_sel */
307 #define UART8_RX_M1 4
308 #define UART8_RX_M1_OFFSET 4
309 #define UART8_RX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
310 /* gpio3d4_sel */
311 #define UART8_TX_M1 4
312 #define UART8_TX_M1_OFFSET 0
313 #define UART8_TX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
314
315 /* UART9 iomux */
316 /* gpio4b3_sel */
317 #define UART9_RX_M0 4
318 #define UART9_RX_M0_OFFSET 12
319 #define UART9_RX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
320 /* gpio4b2_sel */
321 #define UART9_TX_M0 4
322 #define UART9_TX_M0_OFFSET 8
323 #define UART9_TX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
324
325 /* gpio3c3_sel */
326 #define UART9_RX_M1 3
327 #define UART9_RX_M1_OFFSET 12
328 #define UART9_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
329 /* gpio3c2_sel */
330 #define UART9_TX_M1 3
331 #define UART9_TX_M1_OFFSET 8
332 #define UART9_TX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
333
334 #define set_uart_iomux(bits_offset, bits_val, addr) \
335 writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
336
337 #define set_uart_iomux_rx(ID, MODE) \
338 set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
339 #define set_uart_iomux_tx(ID, MODE) \
340 set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
341
board_debug_uart_init(void)342 void board_debug_uart_init(void)
343 {
344 /* UART 0 */
345 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff210000)
346
347 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
348 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
349
350 /* UART0_M0 Switch iomux */
351 set_uart_iomux_rx(0, 0);
352 set_uart_iomux_tx(0, 0);
353 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
354 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
355
356 /* UART0_M1 Switch iomux */
357 set_uart_iomux_rx(0, 1);
358 set_uart_iomux_tx(0, 1);
359 #endif
360 /* UART 1 */
361 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff670000)
362
363 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
364 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
365
366 /* UART1_M0 Switch iomux */
367 set_uart_iomux_rx(1, 0);
368 set_uart_iomux_tx(1, 0);
369 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
370 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
371
372 /* UART1_M1 Switch iomux */
373 set_uart_iomux_rx(1, 1);
374 set_uart_iomux_tx(1, 1);
375 #endif
376 /* UART 2 */
377 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff680000)
378
379 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
380 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
381
382 /* UART2_M0 Switch iomux */
383 set_uart_iomux_rx(2, 0);
384 set_uart_iomux_tx(2, 0);
385 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
386 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
387
388 /* UART2_M1 Switch iomux */
389 set_uart_iomux_rx(2, 1);
390 set_uart_iomux_tx(2, 1);
391 #endif
392 /* UART 3 */
393 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
394 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
395 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
396
397 /* UART3_M0 Switch iomux */
398 set_uart_iomux_rx(3, 0);
399 set_uart_iomux_tx(3, 0);
400 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
401 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
402
403 /* UART3_M1 Switch iomux */
404 set_uart_iomux_rx(3, 1);
405 set_uart_iomux_tx(3, 1);
406 #endif
407 /* UART 4 */
408 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6a0000)
409 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
410 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
411
412 /* UART4_M0 Switch iomux */
413 set_uart_iomux_rx(4, 0);
414 set_uart_iomux_tx(4, 0);
415 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
416 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
417
418 /* UART4_M1 Switch iomux */
419 set_uart_iomux_rx(4, 1);
420 set_uart_iomux_tx(4, 1);
421 #endif
422 /* UART 5 */
423 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6b0000)
424 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
425 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
426
427 /* UART5_M0 Switch iomux */
428 set_uart_iomux_rx(5, 0);
429 set_uart_iomux_tx(5, 0);
430 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
431 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
432
433 /* UART5_M1 Switch iomux */
434 set_uart_iomux_rx(5, 1);
435 set_uart_iomux_tx(5, 1);
436 #endif
437 /* UART 6 */
438 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6c0000)
439 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
440 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
441
442 /* UART6_M0 Switch iomux */
443 set_uart_iomux_rx(6, 0);
444 set_uart_iomux_tx(6, 0);
445 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
446 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
447
448 /* UART6_M1 Switch iomux */
449 set_uart_iomux_rx(6, 1);
450 set_uart_iomux_tx(6, 1);
451 #endif
452 /* UART 7 */
453 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6d0000)
454 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
455 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
456
457 /* UART7_M0 Switch iomux */
458 set_uart_iomux_rx(7, 0);
459 set_uart_iomux_tx(7, 0);
460 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
461 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
462
463 /* UART7_M1 Switch iomux */
464 set_uart_iomux_rx(7, 1);
465 set_uart_iomux_tx(7, 1);
466 #endif
467 /* UART 8 */
468 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6e0000)
469 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
470 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
471
472 /* UART8_M0 Switch iomux */
473 set_uart_iomux_rx(8, 0);
474 set_uart_iomux_tx(8, 0);
475 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
476 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
477
478 /* UART8_M1 Switch iomux */
479 set_uart_iomux_rx(8, 1);
480 set_uart_iomux_tx(8, 1);
481 #endif
482 /* UART 9 */
483 #elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6f0000)
484 #if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
485 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
486
487 /* UART9_M0 Switch iomux */
488 set_uart_iomux_rx(9, 0);
489 set_uart_iomux_tx(9, 0);
490 #elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
491 (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
492
493 /* UART9_M1 Switch iomux */
494 set_uart_iomux_rx(9, 1);
495 set_uart_iomux_tx(9, 1);
496 #endif
497 #endif
498 }
499
fit_standalone_release(char * id,uintptr_t entry_point)500 int fit_standalone_release(char *id, uintptr_t entry_point)
501 {
502 /* bus m0 configuration: */
503 /* open hclk_dcache / hclk_icache / clk_bus m0 rtc / fclk_bus_m0_core */
504 writel(0x03180000, TOP_CRU_BASE + TOP_CRU_GATE_CON23);
505
506 /* open bus m0 sclk / bus m0 hclk / bus m0 dclk */
507 writel(0x00070000, TOP_CRU_BASE + TOP_CRU_CM0_GATEMASK);
508
509 /* mcu_cache_peripheral_addr */
510 writel(0xa0000000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);
511 writel(0xffb40000, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
512
513 sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
514 ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
515 0xffff0000 | (entry_point >> 16));
516 sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
517 ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR, 0xffffa000);
518
519 /* release dcache / icache / bus m0 jtag / bus m0 */
520 writel(0x03280000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON23);
521
522 /* release pmu m0 jtag / pmu m0 */
523 /* writel(0x00050000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON02); */
524
525 return 0;
526 }
527
528 #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
qos_priority_init(void)529 static void qos_priority_init(void)
530 {
531 u32 delay;
532 u32 i;
533
534 /* power up vo,vi,gpu */
535 rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0,
536 PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA);
537 delay = 1000;
538 do {
539 udelay(1);
540 delay--;
541 if (delay == 0) {
542 printf("Fail to set domain. PMU2_PWR_GATE_STS0=0x%x\n",
543 readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0));
544 hang();
545 }
546 } while (readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0) &
547 (PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA));
548 /* power up vop memory */
549 for (i = 0; i < 16; i++)
550 rk_clrreg(PMU_BASE_ADDR + PMU2_MEM_SD_SFTCON0, BIT(i));
551
552 /* release vo,vi,gpu idle request */
553 rk_clrreg(PMU_BASE_ADDR + PMU2_BIU_IDLE_SFTCON0,
554 (IDLE_REQ_VO_SFTENA | IDLE_REQ_VI_SFTENA));
555
556 delay = 1000;
557 /* wait ack status */
558 do {
559 udelay(1);
560 delay--;
561 if (delay == 0) {
562 printf("Fail to get ack on domain. PMU2_BIU_IDLE_ACK_STS0=0x%x\n",
563 readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0));
564 hang();
565 }
566 } while (readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0) &
567 (IDLE_ACK_VO | IDLE_ACK_VI));
568
569 delay = 1000;
570 /* wait idle status */
571 do {
572 udelay(1);
573 delay--;
574 if (delay == 0) {
575 printf("Fail to set idle on domain. PMU2_BIT_IDLE_STS0=0x%x\n",
576 readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0));
577 hang();
578 }
579 } while (readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0) &
580 (IDLE_VO | IDLE_VI));
581
582 /*
583 * modify default qos priority setting, then
584 * Peri > VOP/ISP/VICAP > CPU > GPU/NPU/RKVDEC/RGA/Other
585 * (5) (4) (3) (2)
586 *
587 * NOTE: GPU qos init is in kernel, in case that vdd gpu is off now.
588 */
589 writel(QOS_PRIORITY_LEVEL(5, 5), CRYPTO_PRIORITY_REG);
590 writel(QOS_PRIORITY_LEVEL(5, 5), DMAC_PRIORITY_REG);
591 writel(QOS_PRIORITY_LEVEL(5, 5), EMMC_PRIORITY_REG);
592 writel(QOS_PRIORITY_LEVEL(5, 5), FSPI_PRIORITY_REG);
593 writel(QOS_PRIORITY_LEVEL(5, 5), GMAC_PRIORITY_REG);
594 writel(QOS_PRIORITY_LEVEL(5, 5), MAC100_PRIORITY_REG);
595 writel(QOS_PRIORITY_LEVEL(5, 5), MCU_PRIORITY_REG);
596 writel(QOS_PRIORITY_LEVEL(5, 5), RKDMA_PRIORITY_REG);
597 writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC0_PRIORITY_REG);
598 writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC1_PRIORITY_REG);
599 writel(QOS_PRIORITY_LEVEL(5, 5), USB2_PRIORITY_REG);
600 writel(QOS_PRIORITY_LEVEL(5, 5), USB3_PRIORITY_REG);
601 writel(QOS_PRIORITY_LEVEL(4, 4), ISP_PRIORITY_REG);
602 writel(QOS_PRIORITY_LEVEL(4, 4), VICAP_PRIORITY_REG);
603 writel(QOS_PRIORITY_LEVEL(4, 4), VOP_PRIORITY_REG);
604 writel(QOS_PRIORITY_LEVEL(2, 2), DCF_PRIORITY_REG);
605 writel(QOS_PRIORITY_LEVEL(2, 2), DMA2DDR_PRIORITY_REG);
606 writel(QOS_PRIORITY_LEVEL(2, 2), PCIE_PRIORITY_REG);
607 }
608
arch_cpu_init(void)609 int arch_cpu_init(void)
610 {
611 u32 val;
612
613 /* Set the emmc to access ddr memory */
614 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
615 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
616
617 /* Set the sdmmc to access ddr memory */
618 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
619 writel(val & 0xff0000ff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
620
621 /*
622 * Set SAIx_MCLK as input default
623 *
624 * It's safe to set mclk as input default to avoid high freq glitch
625 * which may make devices work unexpected. And then enabled by
626 * kernel stage or any state where user use it.
627 */
628 writel(0x0a100000, PERI_GRF_BASE + PERI_GRF_AUDIO_CON);
629
630 /* Assert reset the pipe phy to save power and de-assert when in use */
631 writel(0x00030001, PIPEPHY_GRF_BASE + PIPEPHY_PIPE_CON5);
632
633 #if defined(CONFIG_ROCKCHIP_SFC)
634 /* Set the fspi to access ddr memory */
635 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
636 writel(val & 0x00ffffff, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
637
638 /*
639 * Fix fspi io ds level:
640 *
641 * level 2 for 1V8
642 * level 3 for 3V3
643 */
644 if (readl(GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L) == 0x2222) {
645 if (readl(GPIO2_IOC_BASE + GPIO2_IOC_IO_VSEL0) & POC_VCCIO2_VD_3V3) {
646 writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
647 writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
648 writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
649 } else {
650 writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
651 writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
652 writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
653 }
654 }
655 #endif
656
657 qos_priority_init();
658
659 return 0;
660 }
661 #endif
662