Merge "feat(rockchip): increase FDT Buffer for Rockchip Devices" into integration

Merge "feat(rockchip): update uart baudrate for rk3399" into integration

feat(rk3576): support rk3576

rk3576 is an Octa-core soc with Cortex-a53/a72 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4

feat(rk3576): support rk3576

rk3576 is an Octa-core soc with Cortex-a53/a72 inside.
This patch supports the following functions:
1. basic platform setup
2. power up/off cpus
3. suspend/resume cpus
4. suspend/resume system
5. reset system
6. power off system

Change-Id: I67a019822bd4af13e4a3cdd09cf06202f4922cc4
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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Merge "fix(rme): map DEVICE0_BASE as EL3_PAS" into integration

feat(versal2): extended SMCCC payload for EEMI

Until Versal, the extended SMCCC payload was supported only for
QUERY_DATA, while other APIs used the legacy SMCCC format.

In Versal Gen 2, all EEMI A

feat(versal2): extended SMCCC payload for EEMI

Until Versal, the extended SMCCC payload was supported only for
QUERY_DATA, while other APIs used the legacy SMCCC format.

In Versal Gen 2, all EEMI APIs are supported with extended SMCCC
payload only, enabling a simplified and efficient pass-through
implementation.

Also, set TFA_NO_PM to 0 to enable power management by default.

Change-Id: I937be3c78ebe87c62f8697a0a82cdcd21c185f56
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM func

feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM functionality. Enable wakeup for
new peripherals

Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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feat(versal2): add dependency macro for PM

The pm_api_sys.c file has dependency on the PLAT_ARM_GICR_BASE macro.
Add the macro to fix compilation error when PM is enabled.

Change-Id: Ibd77dd38b4a2a

feat(versal2): add dependency macro for PM

The pm_api_sys.c file has dependency on the PLAT_ARM_GICR_BASE macro.
Add the macro to fix compilation error when PM is enabled.

Change-Id: Ibd77dd38b4a2a55614064c4ed0b1096acc658a5c
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesi

refactor(cpus): register DSU errata with the errata framework's wrappers

The existing DSU errata workarounds hijack the errata framework's inner
workings to register with it. However, that is undesirable as any change
to the framework may end up missing these workarounds. So convert the
checks and workarounds to macros and have them included with the
standard wrappers.

The only problem with this is the is_scu_present_in_dsu weak function.
Fortunately, it is only needed for 2 of the errata and only on 3 cores.
So drop it, assuming the default behaviour and have the callers handle
the exception.

Change-Id: Iefa36325804ea093e938f867b9a6f49a6984b8ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add suppo

Merge changes from topic "jw/gic-lca-support" into integration

* changes:
fix(rdn2): add LCA multichip data for RD-N2-Cfg2
fix(rdv3): add LCA multichip data for RD-V3-Cfg2
feat(gic): add support for local chip addressing

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Merge "fix(psci): check if a core is the last one in a requested power level" into integration

feat(rockchip): increase FDT Buffer for Rockchip Devices

Modify the FDT buffer for Rockchip devices to 384KiB. This is done to
allow us to pass mainline devicetrees with symbols through Arm Trusted

feat(rockchip): increase FDT Buffer for Rockchip Devices

Modify the FDT buffer for Rockchip devices to 384KiB. This is done to
allow us to pass mainline devicetrees with symbols through Arm Trusted
Firmware. 384KiB was chosen as 512KiB is very near the maximum
supported with the current reserved memory. As of kernel version 6.13,
the largest devicetree with symbols enabled is 215KiB, and the largest
Rockchip devicetree with symbols enabled is 176KiB
(rk3588-evb1-v10.dtb).

Change-Id: Iea9343d7a30ee26cad3ee5cc848980a93873ae34
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

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Merge "feat(qemu): add hob support for qemu platforms" into integration

fix(rme): map DEVICE0_BASE as EL3_PAS

To pass SMMUv3 Realm Page 0 address to RMM
in Boot Manifest, BL31 needs to read SMMU_ROOT_IDR0
register. BL31 at EL3 runs in Root mode, but
CoreSight and periph

fix(rme): map DEVICE0_BASE as EL3_PAS

To pass SMMUv3 Realm Page 0 address to RMM
in Boot Manifest, BL31 needs to read SMMU_ROOT_IDR0
register. BL31 at EL3 runs in Root mode, but
CoreSight and peripherals at DEVICE0_BASE
(0x2000_0000) including SMMUv3 at 0x2B40_0000 are
mapped as MT_SECURE which results in RAZ access
to all SMMUv3 registers after enabling MMU.
This patch changes MT_SECURE mapping to EL3_PAS
resulting in MT_SECURE (ENABLE_RME = 0), and
MT_ROOT (ENABLE_RME = 1).

Change-Id: I3d9ae7c86e4836dd6722fa64116a14d8c8aed8da
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refacto

Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refactor console to support transfer list
chore(xilinx): propagate error code
feat(versal2): retrieve DT address from transfer list
chore(versal2): move xfer-list file paths
fix(versal2): update transfer list as optional

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fix(versal2): pass tl address to bl32

Pass transfer list address to BL32 as an argument during boot time.

Change-Id: Ic63649b9c41cfae2365ec5911dcab63a7dd005ff
Signed-off-by: Maheedhar Bollapalli <m

fix(versal2): pass tl address to bl32

Pass transfer list address to BL32 as an argument during boot time.

Change-Id: Ic63649b9c41cfae2365ec5911dcab63a7dd005ff
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(xilinx): runtime console to handle dt failure

If the Device Tree is missing or parsing fails in the runtime
console, the console still gets registered with zeroed DT values,
leading to a panic d

fix(xilinx): runtime console to handle dt failure

If the Device Tree is missing or parsing fails in the runtime
console, the console still gets registered with zeroed DT values,
leading to a panic due to the absence of a console type.
Added fallback option and check for zero base address.

Change-Id: I5f5e0222685ba015ab7db2ecbd46d906f5ab9116
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
o

refactor(xilinx): refactor console to support transfer list

Refactor console to support DTB console in case of transfer list.
Simplify logic where SOC specific macros are moved to platform headers
or makefile where XLNX_DT_CFG macro describe if system is DT driven or not.

Change-Id: Id45c03a950b62e83e91a50e0485eacdb233ba745
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapal

chore(xilinx): propagate error code

Propagate error instead of making own error code.

Change-Id: I9300ad342e98ca0e730b091510d9d62747b81a5f
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44b9a0753809652f26bc1b7e061f5364229ba352
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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chore(versal2): move xfer-list file paths

Only Versal Gen 2 platform supports transfer list.
Move transfer list files to versal2 common path.

Change-Id: I2795270a77e2af5e012c82c7b5916fa1f90f0497
Si

chore(versal2): move xfer-list file paths

Only Versal Gen 2 platform supports transfer list.
Move transfer list files to versal2 common path.

Change-Id: I2795270a77e2af5e012c82c7b5916fa1f90f0497
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): update transfer list as optional

Updated transfer list feature as optional and user should explicitly
provide build time argument to enable transfer list.
In TL optional case TL addres

fix(versal2): update transfer list as optional

Updated transfer list feature as optional and user should explicitly
provide build time argument to enable transfer list.
In TL optional case TL address range is utilized as default dtb
address range. Updated default DT address to transfer list address.

Change-Id: Ieeaacb3e6fda4ad1da9330708e19d776bffb06c1
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes I3d7a5a92,I5b2d035e into integration

* changes:
fix(mt8196): remove EC_SUSPEND_PIN initial setting
fix(mt8196): remove SPM support for ES chip

Merge "fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31" into integration

Merge changes I712712d7,I1932500e,I75dda77e,I12f3b8a3,Ia72e5900 into integration

* changes:
refactor(rse)!: remove rse_comms_init
refactor(arm): switch to rse_mbx_init
refactor(rse): put MHU c

Merge changes I712712d7,I1932500e,I75dda77e,I12f3b8a3,Ia72e5900 into integration

* changes:
refactor(rse)!: remove rse_comms_init
refactor(arm): switch to rse_mbx_init
refactor(rse): put MHU code in a dedicated file
refactor(tc): add plat_rse_comms_init
refactor(arm)!: rename PLAT_MHU_VERSION flag

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fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31

When RESET_TO_BL31 was enabled, CNTFRQ_EL0 was left uninitialized,
leading to incorrect system counter frequency settings. This
impacted tim

fix(neoverse-rd): initialize CNTFRQ_EL0 for RESET_TO_BL31

When RESET_TO_BL31 was enabled, CNTFRQ_EL0 was left uninitialized,
leading to incorrect system counter frequency settings. This
impacted timer-dependent components, such as SMMUv3, causing
initialization failures and unpredictable behavior.

To fix this, CNTFRQ_EL0 is now explicitly set using
plat_get_syscnt_freq2(), ensuring the correct system timer
frequency and proper initialization of dependent components.

Signed-off-by: Lokesh B V <Lokesh.BV@Arm.com>
Change-Id: I808b17d25c87c4dce1bc2c8171a800b69b5c2908

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