allwinner: Relax PSCI entry point check

The DRAM controller supports up to 4GB of DRAM, and there are actually
boards out there where we can use at least 3GB of this.

Relax the PSCI entry point che

allwinner: Relax PSCI entry point check

The DRAM controller supports up to 4GB of DRAM, and there are actually
boards out there where we can use at least 3GB of this.

Relax the PSCI entry point check, to be not restricted to 2GB of DRAM.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: security: Fix SPC guard

The "#ifdef SUNXI_SPC_BASE" guard was meant to allow the build on SoCs
without a Secure Peripherals Controller, so that we skip that part of
the security setup. Bu

allwinner: security: Fix SPC guard

The "#ifdef SUNXI_SPC_BASE" guard was meant to allow the build on SoCs
without a Secure Peripherals Controller, so that we skip that part of
the security setup. But in the current position this will trigger a
warning about an unused variable.

Simply move the guard one line up to cover the variable as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: cpu-ops: avoid PSCI on/off output

The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more
obvious by changing the log level to "VERBOSE" and so avoiding it to
be printed

allwinner: cpu-ops: avoid PSCI on/off output

The "INFO" output in sunxi_cpu_ops.c is quite verbose, so make this more
obvious by changing the log level to "VERBOSE" and so avoiding it to
be printed in a normal (even debug) build.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: sun50i_a64: remove unneeded VER_REG offset

The relative VER_REG *offset* is the same across all known SoCs, so we
can define this offset near it's user.

Remove it from the memory map.

R

allwinner: sun50i_a64: remove unneeded VER_REG offset

The relative VER_REG *offset* is the same across all known SoCs, so we
can define this offset near it's user.

Remove it from the memory map.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: common: add missing header

Some code in sunxi_common.c requires symbols defined in sunxi_private.h,
so add the header to that file.
It was included via another header before, but let's ma

allwinner: common: add missing header

Some code in sunxi_common.c requires symbols defined in sunxi_private.h,
so add the header to that file.
It was included via another header before, but let's make this explicit.

Reported-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dis

allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS)
as an input using the 'SPD=<dispatcher name>' option during bl31 build.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

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Merge pull request #1429 from jeenu-arm/mmu-direct

Enable MMU without stack for xlat v2/DynamIQ

DynamIQ: Enable MMU without using stack

Having an active stack while enabling MMU has shown coherency problems.
This patch builds on top of translation library changes that introduces
MMU-enabling w

DynamIQ: Enable MMU without using stack

Having an active stack while enabling MMU has shown coherency problems.
This patch builds on top of translation library changes that introduces
MMU-enabling without using stacks.

Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while
enabling MMU only because of active stack. Now that we can enable MMU
without using stack, we can enable both MMU and data caches at the same
time.

NOTE: Since this feature depends on using translation table library v2,
disallow using translation table library v1 with HW_ASSISTED_COHERENCY.

Fixes ARM-software/tf-issues#566

Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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ARM platforms: Initialize cntfrq for BL1 Firmware update

Currenly the CNTFRQ register and system timer is initialized in BL31 for
use by the normal world. During firmware update, the NS-BL1 or NS-BL

ARM platforms: Initialize cntfrq for BL1 Firmware update

Currenly the CNTFRQ register and system timer is initialized in BL31 for
use by the normal world. During firmware update, the NS-BL1 or NS-BL2U
may need to access the system timer. Hence this patch duplicates the
CNTFRQ and system timer initialization in BL1 as well.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I1ede78b4ae64080fb418cb93f3e48b26d7b724dc

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Merge pull request #1445 from danielboulby-arm/db/DynamicAuthentication

Set FVP DYN_DISABLE_AUTH authentication default to 0

Set FVP DYN_DISABLE_AUTH authentication default to 0

Set the ability to dynamically disable Trusted Boot Board
authentication to be off by default

Change-Id: Ibd2aa179179f7d9b0e7731c6e450f200a8c675

Set FVP DYN_DISABLE_AUTH authentication default to 0

Set the ability to dynamically disable Trusted Boot Board
authentication to be off by default

Change-Id: Ibd2aa179179f7d9b0e7731c6e450f200a8c67529
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>

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Merge pull request #1448 from npoushin/npoushin/sgi575-coverity-fixes

npoushin/sgi575 coverity fixes

plat/arm: css: Sanitize the input to css_validate_power_state

In the case of the platform max power level being less than the system
power level, make sure to not overrun the array of power states.

plat/arm: css: Sanitize the input to css_validate_power_state

In the case of the platform max power level being less than the system
power level, make sure to not overrun the array of power states.

This fixes Coverity Scan OVERRUN defect CID 267021.

Change-Id: I52646ab9be2fceeb5c331b5dad7a6267991f4197
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>

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plat/arm: css: Convert CSS_SYSTEM_PWR_STATE from macro to inline function

This is to fix a number of Coverity Scan DEADCODE defects, CID numbers
listed below, as reported from
https://scan.coverity.

plat/arm: css: Convert CSS_SYSTEM_PWR_STATE from macro to inline function

This is to fix a number of Coverity Scan DEADCODE defects, CID numbers
listed below, as reported from
https://scan.coverity.com/projects/arm-software-arm-trusted-firmware

CID 267023
CID 267022
CID 267020

Change-Id: I2963a799b210149e84ccab5c5b9082267ddfe337
Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>

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allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dis

allwinner: Add BL32 (corresponds to Trusted OS) support

This patch is an attempt to run Trusted OS (OP-TEE OS being one of them) along
side BL31 image.

ATF supports multiple SPD's that can take dispatcher name (opteed for OP-TEE OS)
as an input using the 'SPD=<dispatcher name>' option during bl31 build.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

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Merge pull request #1441 from robertovargas-arm/mem_protect_board

Move mem-protect definitions to board specific files

Merge pull request #1406 from robertovargas-arm/uuid

Make TF UUID RFC 4122 compliant

Merge pull request #1437 from jeenu-arm/ras-remaining

SDEI dispatch changes to enable RAS use cases

Merge pull request #1427 from b49020/integration

Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform.

Arm platforms: Remove common RAS configuration source

The file arm_ras.c intended to provide common platform-specific RAS
configuration for Arm platforms. Because this file has symbol
definitions, i

Arm platforms: Remove common RAS configuration source

The file arm_ras.c intended to provide common platform-specific RAS
configuration for Arm platforms. Because this file has symbol
definitions, it's proving difficult to provide a common definition.

This patch therefore renames and makes the file specific to FVP. Other
platforms shall provide their own configuration in similar fashion.

Change-Id: I766fd238946e3e49cdb659680e1b45f41b237901
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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Merge pull request #1434 from soby-mathew/sm/fix_cntfrq

ARM Platforms: Update CNTFRQ register in CNTCTLBase frame

Merge pull request #1433 from sivadur/integration

xilinx: fix zynqmp build when tsp is enabled

synquacer: Add platform makefile and documentation

Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier wo

synquacer: Add platform makefile and documentation

Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier work regarding build and deploy steps for
Developerbox based on Synquacer SoCs. They deserve much of the credit
for this work although, since I assembled and tested things, any blame
is probably mine.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

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synquacer: Enable PSCI framework

PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
-

synquacer: Enable PSCI framework

PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
- CPU STANDBY
- SYSTEM RESET
- SYSTEM OFF

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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synquacer: Retrieve DRAM info from SCP firmware

Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pa

synquacer: Retrieve DRAM info from SCP firmware

Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>

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