1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arm_def.h> 9 #include <arm_xlat_tables.h> 10 #include <assert.h> 11 #include <bl1.h> 12 #include <bl_common.h> 13 #include <plat_arm.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <sp805.h> 17 #include <utils.h> 18 #include "../../../bl1/bl1_private.h" 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak bl1_early_platform_setup 22 #pragma weak bl1_plat_arch_setup 23 #pragma weak bl1_platform_setup 24 #pragma weak bl1_plat_sec_mem_layout 25 #pragma weak bl1_plat_prepare_exit 26 27 #define MAP_BL1_TOTAL MAP_REGION_FLAT( \ 28 bl1_tzram_layout.total_base, \ 29 bl1_tzram_layout.total_size, \ 30 MT_MEMORY | MT_RW | MT_SECURE) 31 #define MAP_BL1_CODE MAP_REGION_FLAT( \ 32 BL_CODE_BASE, \ 33 BL1_CODE_END - BL_CODE_BASE, \ 34 MT_CODE | MT_SECURE) 35 #define MAP_BL1_RO_DATA MAP_REGION_FLAT( \ 36 BL1_RO_DATA_BASE, \ 37 BL1_RO_DATA_END \ 38 - BL_RO_DATA_BASE, \ 39 MT_RO_DATA | MT_SECURE) 40 41 /* Data structure which holds the extents of the trusted SRAM for BL1*/ 42 static meminfo_t bl1_tzram_layout; 43 44 meminfo_t *bl1_plat_sec_mem_layout(void) 45 { 46 return &bl1_tzram_layout; 47 } 48 49 /******************************************************************************* 50 * BL1 specific platform actions shared between ARM standard platforms. 51 ******************************************************************************/ 52 void arm_bl1_early_platform_setup(void) 53 { 54 55 #if !ARM_DISABLE_TRUSTED_WDOG 56 /* Enable watchdog */ 57 sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); 58 #endif 59 60 /* Initialize the console to provide early debug support */ 61 arm_console_boot_init(); 62 63 /* Allow BL1 to see the whole Trusted RAM */ 64 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; 65 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; 66 67 #if !LOAD_IMAGE_V2 68 /* Calculate how much RAM BL1 is using and how much remains free */ 69 bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; 70 bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; 71 reserve_mem(&bl1_tzram_layout.free_base, 72 &bl1_tzram_layout.free_size, 73 BL1_RAM_BASE, 74 BL1_RAM_LIMIT - BL1_RAM_BASE); 75 #endif /* LOAD_IMAGE_V2 */ 76 } 77 78 void bl1_early_platform_setup(void) 79 { 80 arm_bl1_early_platform_setup(); 81 82 /* 83 * Initialize Interconnect for this cluster during cold boot. 84 * No need for locks as no other CPU is active. 85 */ 86 plat_arm_interconnect_init(); 87 /* 88 * Enable Interconnect coherency for the primary CPU's cluster. 89 */ 90 plat_arm_interconnect_enter_coherency(); 91 } 92 93 /****************************************************************************** 94 * Perform the very early platform specific architecture setup shared between 95 * ARM standard platforms. This only does basic initialization. Later 96 * architectural setup (bl1_arch_setup()) does not do anything platform 97 * specific. 98 *****************************************************************************/ 99 void arm_bl1_plat_arch_setup(void) 100 { 101 #if USE_COHERENT_MEM 102 /* ARM platforms dont use coherent memory in BL1 */ 103 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 104 #endif 105 106 const mmap_region_t bl_regions[] = { 107 MAP_BL1_TOTAL, 108 MAP_BL1_CODE, 109 MAP_BL1_RO_DATA, 110 {0} 111 }; 112 113 arm_setup_page_tables(bl_regions, plat_arm_get_mmap()); 114 #ifdef AARCH32 115 enable_mmu_secure(0); 116 #else 117 enable_mmu_el3(0); 118 #endif /* AARCH32 */ 119 } 120 121 void bl1_plat_arch_setup(void) 122 { 123 arm_bl1_plat_arch_setup(); 124 } 125 126 /* 127 * Perform the platform specific architecture setup shared between 128 * ARM standard platforms. 129 */ 130 void arm_bl1_platform_setup(void) 131 { 132 /* Initialise the IO layer and register platform IO devices */ 133 plat_arm_io_setup(); 134 #if LOAD_IMAGE_V2 135 arm_load_tb_fw_config(); 136 #endif 137 /* 138 * Allow access to the System counter timer module and program 139 * counter frequency for non secure images during FWU 140 */ 141 arm_configure_sys_timer(); 142 write_cntfrq_el0(plat_get_syscnt_freq2()); 143 } 144 145 void bl1_platform_setup(void) 146 { 147 arm_bl1_platform_setup(); 148 } 149 150 void bl1_plat_prepare_exit(entry_point_info_t *ep_info) 151 { 152 #if !ARM_DISABLE_TRUSTED_WDOG 153 /* Disable watchdog before leaving BL1 */ 154 sp805_stop(ARM_SP805_TWDG_BASE); 155 #endif 156 157 #ifdef EL3_PAYLOAD_BASE 158 /* 159 * Program the EL3 payload's entry point address into the CPUs mailbox 160 * in order to release secondary CPUs from their holding pen and make 161 * them jump there. 162 */ 163 arm_program_trusted_mailbox(ep_info->pc); 164 dsbsy(); 165 sev(); 166 #endif 167 } 168 169 /******************************************************************************* 170 * The following function checks if Firmware update is needed, 171 * by checking if TOC in FIP image is valid or not. 172 ******************************************************************************/ 173 unsigned int bl1_plat_get_next_image_id(void) 174 { 175 if (!arm_io_is_toc_valid()) 176 return NS_BL1U_IMAGE_ID; 177 178 return BL2_IMAGE_ID; 179 } 180