1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <desc_image_load.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_dt.h> 21 #include <stm32mp1_private.h> 22 #include <stm32mp1_pwr.h> 23 #include <stm32mp1_rcc.h> 24 #include <string.h> 25 #include <xlat_tables_v2.h> 26 27 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 28 u_register_t arg2, u_register_t arg3) 29 { 30 stm32mp1_save_boot_ctx_address(arg0); 31 } 32 33 void bl2_platform_setup(void) 34 { 35 INFO("BL2 runs SP_MIN setup\n"); 36 } 37 38 void bl2_el3_plat_arch_setup(void) 39 { 40 /* 41 * Disable the backup domain write protection. 42 * The protection is enable at each reset by hardware 43 * and must be disabled by software. 44 */ 45 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 46 47 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 48 ; 49 } 50 51 /* Reset backup domain on cold boot cases */ 52 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 53 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 54 55 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 56 0U) { 57 ; 58 } 59 60 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 61 } 62 63 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 64 BL_CODE_END - BL_CODE_BASE, 65 MT_CODE | MT_SECURE); 66 67 /* Prevent corruption of preloaded BL32 */ 68 mmap_add_region(BL32_BASE, BL32_BASE, 69 BL32_LIMIT - BL32_BASE, 70 MT_MEMORY | MT_RO | MT_SECURE); 71 72 /* Prevent corruption of preloaded Device Tree */ 73 mmap_add_region(DTB_BASE, DTB_BASE, 74 DTB_LIMIT - DTB_BASE, 75 MT_MEMORY | MT_RO | MT_SECURE); 76 77 configure_mmu(); 78 79 generic_delay_timer_init(); 80 81 if (dt_open_and_check() < 0) { 82 panic(); 83 } 84 85 if (stm32mp1_clk_probe() < 0) { 86 panic(); 87 } 88 89 if (stm32mp1_clk_init() < 0) { 90 panic(); 91 } 92 93 stm32mp1_io_setup(); 94 } 95