1 /* 2 * Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __STM32MP1_RCC_H__ 8 #define __STM32MP1_RCC_H__ 9 10 #include <utils_def.h> 11 12 #define RCC_TZCR U(0x00) 13 #define RCC_OCENSETR U(0x0C) 14 #define RCC_OCENCLRR U(0x10) 15 #define RCC_HSICFGR U(0x18) 16 #define RCC_CSICFGR U(0x1C) 17 #define RCC_MPCKSELR U(0x20) 18 #define RCC_ASSCKSELR U(0x24) 19 #define RCC_RCK12SELR U(0x28) 20 #define RCC_MPCKDIVR U(0x2C) 21 #define RCC_AXIDIVR U(0x30) 22 #define RCC_APB4DIVR U(0x3C) 23 #define RCC_APB5DIVR U(0x40) 24 #define RCC_RTCDIVR U(0x44) 25 #define RCC_MSSCKSELR U(0x48) 26 #define RCC_PLL1CR U(0x80) 27 #define RCC_PLL1CFGR1 U(0x84) 28 #define RCC_PLL1CFGR2 U(0x88) 29 #define RCC_PLL1FRACR U(0x8C) 30 #define RCC_PLL1CSGR U(0x90) 31 #define RCC_PLL2CR U(0x94) 32 #define RCC_PLL2CFGR1 U(0x98) 33 #define RCC_PLL2CFGR2 U(0x9C) 34 #define RCC_PLL2FRACR U(0xA0) 35 #define RCC_PLL2CSGR U(0xA4) 36 #define RCC_I2C46CKSELR U(0xC0) 37 #define RCC_SPI6CKSELR U(0xC4) 38 #define RCC_UART1CKSELR U(0xC8) 39 #define RCC_RNG1CKSELR U(0xCC) 40 #define RCC_CPERCKSELR U(0xD0) 41 #define RCC_STGENCKSELR U(0xD4) 42 #define RCC_DDRITFCR U(0xD8) 43 #define RCC_MP_BOOTCR U(0x100) 44 #define RCC_MP_SREQSETR U(0x104) 45 #define RCC_MP_SREQCLRR U(0x108) 46 #define RCC_MP_GCR U(0x10C) 47 #define RCC_MP_APRSTCR U(0x110) 48 #define RCC_MP_APRSTSR U(0x114) 49 #define RCC_BDCR U(0x140) 50 #define RCC_RDLSICR U(0x144) 51 #define RCC_APB4RSTSETR U(0x180) 52 #define RCC_APB4RSTCLRR U(0x184) 53 #define RCC_APB5RSTSETR U(0x188) 54 #define RCC_APB5RSTCLRR U(0x18C) 55 #define RCC_AHB5RSTSETR U(0x190) 56 #define RCC_AHB5RSTCLRR U(0x194) 57 #define RCC_AHB6RSTSETR U(0x198) 58 #define RCC_AHB6RSTCLRR U(0x19C) 59 #define RCC_TZAHB6RSTSETR U(0x1A0) 60 #define RCC_TZAHB6RSTCLRR U(0x1A4) 61 #define RCC_MP_APB4ENSETR U(0x200) 62 #define RCC_MP_APB4ENCLRR U(0x204) 63 #define RCC_MP_APB5ENSETR U(0x208) 64 #define RCC_MP_APB5ENCLRR U(0x20C) 65 #define RCC_MP_AHB5ENSETR U(0x210) 66 #define RCC_MP_AHB5ENCLRR U(0x214) 67 #define RCC_MP_AHB6ENSETR U(0x218) 68 #define RCC_MP_AHB6ENCLRR U(0x21C) 69 #define RCC_MP_TZAHB6ENSETR U(0x220) 70 #define RCC_MP_TZAHB6ENCLRR U(0x224) 71 #define RCC_MP_APB4LPENSETR U(0x300) 72 #define RCC_MP_APB4LPENCLRR U(0x304) 73 #define RCC_MP_APB5LPENSETR U(0x308) 74 #define RCC_MP_APB5LPENCLRR U(0x30C) 75 #define RCC_MP_AHB5LPENSETR U(0x310) 76 #define RCC_MP_AHB5LPENCLRR U(0x314) 77 #define RCC_MP_AHB6LPENSETR U(0x318) 78 #define RCC_MP_AHB6LPENCLRR U(0x31C) 79 #define RCC_MP_TZAHB6LPENSETR U(0x320) 80 #define RCC_MP_TZAHB6LPENCLRR U(0x324) 81 #define RCC_BR_RSTSCLRR U(0x400) 82 #define RCC_MP_GRSTCSETR U(0x404) 83 #define RCC_MP_RSTSCLRR U(0x408) 84 #define RCC_MP_IWDGFZSETR U(0x40C) 85 #define RCC_MP_IWDGFZCLRR U(0x410) 86 #define RCC_MP_CIER U(0x414) 87 #define RCC_MP_CIFR U(0x418) 88 #define RCC_PWRLPDLYCR U(0x41C) 89 #define RCC_MP_RSTSSETR U(0x420) 90 #define RCC_MCO1CFGR U(0x800) 91 #define RCC_MCO2CFGR U(0x804) 92 #define RCC_OCRDYR U(0x808) 93 #define RCC_DBGCFGR U(0x80C) 94 #define RCC_RCK3SELR U(0x820) 95 #define RCC_RCK4SELR U(0x824) 96 #define RCC_TIMG1PRER U(0x828) 97 #define RCC_TIMG2PRER U(0x82C) 98 #define RCC_APB1DIVR U(0x834) 99 #define RCC_APB2DIVR U(0x838) 100 #define RCC_APB3DIVR U(0x83C) 101 #define RCC_PLL3CR U(0x880) 102 #define RCC_PLL3CFGR1 U(0x884) 103 #define RCC_PLL3CFGR2 U(0x888) 104 #define RCC_PLL3FRACR U(0x88C) 105 #define RCC_PLL3CSGR U(0x890) 106 #define RCC_PLL4CR U(0x894) 107 #define RCC_PLL4CFGR1 U(0x898) 108 #define RCC_PLL4CFGR2 U(0x89C) 109 #define RCC_PLL4FRACR U(0x8A0) 110 #define RCC_PLL4CSGR U(0x8A4) 111 #define RCC_I2C12CKSELR U(0x8C0) 112 #define RCC_I2C35CKSELR U(0x8C4) 113 #define RCC_SAI1CKSELR U(0x8C8) 114 #define RCC_SAI2CKSELR U(0x8CC) 115 #define RCC_SAI3CKSELR U(0x8D0) 116 #define RCC_SAI4CKSELR U(0x8D4) 117 #define RCC_SPI2S1CKSELR U(0x8D8) 118 #define RCC_SPI2S23CKSELR U(0x8DC) 119 #define RCC_SPI45CKSELR U(0x8E0) 120 #define RCC_UART6CKSELR U(0x8E4) 121 #define RCC_UART24CKSELR U(0x8E8) 122 #define RCC_UART35CKSELR U(0x8EC) 123 #define RCC_UART78CKSELR U(0x8F0) 124 #define RCC_SDMMC12CKSELR U(0x8F4) 125 #define RCC_SDMMC3CKSELR U(0x8F8) 126 #define RCC_ETHCKSELR U(0x8FC) 127 #define RCC_QSPICKSELR U(0x900) 128 #define RCC_FMCCKSELR U(0x904) 129 #define RCC_FDCANCKSELR U(0x90C) 130 #define RCC_SPDIFCKSELR U(0x914) 131 #define RCC_CECCKSELR U(0x918) 132 #define RCC_USBCKSELR U(0x91C) 133 #define RCC_RNG2CKSELR U(0x920) 134 #define RCC_DSICKSELR U(0x924) 135 #define RCC_ADCCKSELR U(0x928) 136 #define RCC_LPTIM45CKSELR U(0x92C) 137 #define RCC_LPTIM23CKSELR U(0x930) 138 #define RCC_LPTIM1CKSELR U(0x934) 139 #define RCC_APB1RSTSETR U(0x980) 140 #define RCC_APB1RSTCLRR U(0x984) 141 #define RCC_APB2RSTSETR U(0x988) 142 #define RCC_APB2RSTCLRR U(0x98C) 143 #define RCC_APB3RSTSETR U(0x990) 144 #define RCC_APB3RSTCLRR U(0x994) 145 #define RCC_AHB2RSTSETR U(0x998) 146 #define RCC_AHB2RSTCLRR U(0x99C) 147 #define RCC_AHB3RSTSETR U(0x9A0) 148 #define RCC_AHB3RSTCLRR U(0x9A4) 149 #define RCC_AHB4RSTSETR U(0x9A8) 150 #define RCC_AHB4RSTCLRR U(0x9AC) 151 #define RCC_MP_APB1ENSETR U(0xA00) 152 #define RCC_MP_APB1ENCLRR U(0xA04) 153 #define RCC_MP_APB2ENSETR U(0xA08) 154 #define RCC_MP_APB2ENCLRR U(0xA0C) 155 #define RCC_MP_APB3ENSETR U(0xA10) 156 #define RCC_MP_APB3ENCLRR U(0xA14) 157 #define RCC_MP_AHB2ENSETR U(0xA18) 158 #define RCC_MP_AHB2ENCLRR U(0xA1C) 159 #define RCC_MP_AHB3ENSETR U(0xA20) 160 #define RCC_MP_AHB3ENCLRR U(0xA24) 161 #define RCC_MP_AHB4ENSETR U(0xA28) 162 #define RCC_MP_AHB4ENCLRR U(0xA2C) 163 #define RCC_MP_MLAHBENSETR U(0xA38) 164 #define RCC_MP_MLAHBENCLRR U(0xA3C) 165 #define RCC_MP_APB1LPENSETR U(0xB00) 166 #define RCC_MP_APB1LPENCLRR U(0xB04) 167 #define RCC_MP_APB2LPENSETR U(0xB08) 168 #define RCC_MP_APB2LPENCLRR U(0xB0C) 169 #define RCC_MP_APB3LPENSETR U(0xB10) 170 #define RCC_MP_APB3LPENCLRR U(0xB14) 171 #define RCC_MP_AHB2LPENSETR U(0xB18) 172 #define RCC_MP_AHB2LPENCLRR U(0xB1C) 173 #define RCC_MP_AHB3LPENSETR U(0xB20) 174 #define RCC_MP_AHB3LPENCLRR U(0xB24) 175 #define RCC_MP_AHB4LPENSETR U(0xB28) 176 #define RCC_MP_AHB4LPENCLRR U(0xB2C) 177 #define RCC_MP_AXIMLPENSETR U(0xB30) 178 #define RCC_MP_AXIMLPENCLRR U(0xB34) 179 #define RCC_MP_MLAHBLPENSETR U(0xB38) 180 #define RCC_MP_MLAHBLPENCLRR U(0xB3C) 181 #define RCC_VERR U(0xFF4) 182 #define RCC_IDR U(0xFF8) 183 #define RCC_SIDR U(0xFFC) 184 185 /* Values for RCC_TZCR register */ 186 #define RCC_TZCR_TZEN BIT(0) 187 188 /* Used for most of RCC_<x>SELR registers */ 189 #define RCC_SELR_SRC_MASK GENMASK(2, 0) 190 #define RCC_SELR_REFCLK_SRC_MASK GENMASK(1, 0) 191 #define RCC_SELR_SRCRDY BIT(31) 192 193 /* Values of RCC_MPCKSELR register */ 194 #define RCC_MPCKSELR_HSI 0x00000000 195 #define RCC_MPCKSELR_HSE 0x00000001 196 #define RCC_MPCKSELR_PLL 0x00000002 197 #define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 198 199 /* Values of RCC_ASSCKSELR register */ 200 #define RCC_ASSCKSELR_HSI 0x00000000 201 #define RCC_ASSCKSELR_HSE 0x00000001 202 #define RCC_ASSCKSELR_PLL 0x00000002 203 204 /* Values of RCC_MSSCKSELR register */ 205 #define RCC_MSSCKSELR_HSI 0x00000000 206 #define RCC_MSSCKSELR_HSE 0x00000001 207 #define RCC_MSSCKSELR_CSI 0x00000002 208 #define RCC_MSSCKSELR_PLL 0x00000003 209 210 /* Values of RCC_CPERCKSELR register */ 211 #define RCC_CPERCKSELR_HSI 0x00000000 212 #define RCC_CPERCKSELR_CSI 0x00000001 213 #define RCC_CPERCKSELR_HSE 0x00000002 214 215 /* Used for most of DIVR register: max div for RTC */ 216 #define RCC_DIVR_DIV_MASK GENMASK(5, 0) 217 #define RCC_DIVR_DIVRDY BIT(31) 218 219 /* Masks for specific DIVR registers */ 220 #define RCC_APBXDIV_MASK GENMASK(2, 0) 221 #define RCC_MPUDIV_MASK GENMASK(2, 0) 222 #define RCC_AXIDIV_MASK GENMASK(2, 0) 223 224 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 225 #define RCC_MP_ENCLRR_OFFSET U(4) 226 227 /* Fields of RCC_BDCR register */ 228 #define RCC_BDCR_LSEON BIT(0) 229 #define RCC_BDCR_LSEBYP BIT(1) 230 #define RCC_BDCR_LSERDY BIT(2) 231 #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) 232 #define RCC_BDCR_LSEDRV_SHIFT 4 233 #define RCC_BDCR_LSECSSON BIT(8) 234 #define RCC_BDCR_RTCCKEN BIT(20) 235 #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) 236 #define RCC_BDCR_RTCSRC_SHIFT 16 237 #define RCC_BDCR_VSWRST BIT(31) 238 239 /* Fields of RCC_RDLSICR register */ 240 #define RCC_RDLSICR_LSION BIT(0) 241 #define RCC_RDLSICR_LSIRDY BIT(1) 242 243 /* Used for all RCC_PLL<n>CR registers */ 244 #define RCC_PLLNCR_PLLON BIT(0) 245 #define RCC_PLLNCR_PLLRDY BIT(1) 246 #define RCC_PLLNCR_DIVPEN BIT(4) 247 #define RCC_PLLNCR_DIVQEN BIT(5) 248 #define RCC_PLLNCR_DIVREN BIT(6) 249 #define RCC_PLLNCR_DIVEN_SHIFT 4 250 251 /* Used for all RCC_PLL<n>CFGR1 registers */ 252 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 253 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) 254 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 255 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) 256 /* Only for PLL3 and PLL4 */ 257 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 258 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) 259 260 /* Used for all RCC_PLL<n>CFGR2 registers */ 261 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) 262 #define RCC_PLLNCFGR2_DIVP_SHIFT 0 263 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) 264 #define RCC_PLLNCFGR2_DIVQ_SHIFT 8 265 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) 266 #define RCC_PLLNCFGR2_DIVR_SHIFT 16 267 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) 268 269 /* Used for all RCC_PLL<n>FRACR registers */ 270 #define RCC_PLLNFRACR_FRACV_SHIFT 3 271 #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) 272 #define RCC_PLLNFRACR_FRACLE BIT(16) 273 274 /* Used for all RCC_PLL<n>CSGR registers */ 275 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 276 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) 277 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 278 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) 279 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 280 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) 281 282 /* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ 283 #define RCC_OCENR_HSION BIT(0) 284 #define RCC_OCENR_CSION BIT(4) 285 #define RCC_OCENR_HSEON BIT(8) 286 #define RCC_OCENR_HSEBYP BIT(10) 287 #define RCC_OCENR_HSECSSON BIT(11) 288 289 /* Fields of RCC_OCRDYR register */ 290 #define RCC_OCRDYR_HSIRDY BIT(0) 291 #define RCC_OCRDYR_HSIDIVRDY BIT(2) 292 #define RCC_OCRDYR_CSIRDY BIT(4) 293 #define RCC_OCRDYR_HSERDY BIT(8) 294 295 /* Fields of RCC_DDRITFCR register */ 296 #define RCC_DDRITFCR_DDRC1EN BIT(0) 297 #define RCC_DDRITFCR_DDRC1LPEN BIT(1) 298 #define RCC_DDRITFCR_DDRC2EN BIT(2) 299 #define RCC_DDRITFCR_DDRC2LPEN BIT(3) 300 #define RCC_DDRITFCR_DDRPHYCEN BIT(4) 301 #define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) 302 #define RCC_DDRITFCR_DDRCAPBEN BIT(6) 303 #define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) 304 #define RCC_DDRITFCR_AXIDCGEN BIT(8) 305 #define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) 306 #define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) 307 #define RCC_DDRITFCR_DDRCAPBRST BIT(14) 308 #define RCC_DDRITFCR_DDRCAXIRST BIT(15) 309 #define RCC_DDRITFCR_DDRCORERST BIT(16) 310 #define RCC_DDRITFCR_DPHYAPBRST BIT(17) 311 #define RCC_DDRITFCR_DPHYRST BIT(18) 312 #define RCC_DDRITFCR_DPHYCTLRST BIT(19) 313 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) 314 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 315 #define RCC_DDRITFCR_DDRCKMOD_SSR 0 316 #define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) 317 #define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) 318 #define RCC_DDRITFCR_GSKPCTRL BIT(24) 319 320 /* Fields of RCC_HSICFGR register */ 321 #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) 322 323 /* Used for RCC_MCO related operations */ 324 #define RCC_MCOCFG_MCOON BIT(12) 325 #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) 326 #define RCC_MCOCFG_MCODIV_SHIFT 4 327 #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) 328 329 /* Fields of RCC_DBGCFGR register */ 330 #define RCC_DBGCFGR_DBGCKEN BIT(8) 331 332 /* RCC register fields for reset reasons */ 333 #define RCC_MP_RSTSCLRR_PORRSTF BIT(0) 334 #define RCC_MP_RSTSCLRR_BORRSTF BIT(1) 335 #define RCC_MP_RSTSCLRR_PADRSTF BIT(2) 336 #define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) 337 #define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) 338 #define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) 339 #define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) 340 #define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) 341 #define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) 342 #define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) 343 344 /* Global Reset Register */ 345 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) 346 347 /* Clock Source Interrupt Flag Register */ 348 #define RCC_MP_CIFR_MASK U(0x110F1F) 349 #define RCC_MP_CIFR_WKUPF BIT(20) 350 351 /* Stop Request Set Register */ 352 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) 353 #define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) 354 355 /* Stop Request Clear Register */ 356 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) 357 #define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) 358 359 /* Values of RCC_UART24CKSELR register */ 360 #define RCC_UART24CKSELR_HSI 0x00000002 361 362 /* Values of RCC_MP_APB1ENSETR register */ 363 #define RCC_MP_APB1ENSETR_UART4EN BIT(16) 364 365 /* Values of RCC_MP_AHB4ENSETR register */ 366 #define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6) 367 368 #endif /* __STM32MP1_RCC_H__ */ 369