1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <desc_image_load.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_dt.h> 21 #include <stm32mp1_private.h> 22 #include <stm32mp1_context.h> 23 #include <stm32mp1_pwr.h> 24 #include <stm32mp1_rcc.h> 25 #include <string.h> 26 #include <xlat_tables_v2.h> 27 28 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 29 u_register_t arg2, u_register_t arg3) 30 { 31 stm32mp1_save_boot_ctx_address(arg0); 32 } 33 34 void bl2_platform_setup(void) 35 { 36 INFO("BL2 runs SP_MIN setup\n"); 37 } 38 39 void bl2_el3_plat_arch_setup(void) 40 { 41 boot_api_context_t *boot_context = 42 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 43 44 /* 45 * Disable the backup domain write protection. 46 * The protection is enable at each reset by hardware 47 * and must be disabled by software. 48 */ 49 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 50 51 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 52 ; 53 } 54 55 /* Reset backup domain on cold boot cases */ 56 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 57 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 58 59 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 60 0U) { 61 ; 62 } 63 64 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 65 } 66 67 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 68 BL_CODE_END - BL_CODE_BASE, 69 MT_CODE | MT_SECURE); 70 71 /* Prevent corruption of preloaded BL32 */ 72 mmap_add_region(BL32_BASE, BL32_BASE, 73 BL32_LIMIT - BL32_BASE, 74 MT_MEMORY | MT_RO | MT_SECURE); 75 76 /* Prevent corruption of preloaded Device Tree */ 77 mmap_add_region(DTB_BASE, DTB_BASE, 78 DTB_LIMIT - DTB_BASE, 79 MT_MEMORY | MT_RO | MT_SECURE); 80 81 configure_mmu(); 82 83 generic_delay_timer_init(); 84 85 if (dt_open_and_check() < 0) { 86 panic(); 87 } 88 89 if (stm32mp1_clk_probe() < 0) { 90 panic(); 91 } 92 93 if (stm32mp1_clk_init() < 0) { 94 panic(); 95 } 96 97 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 98 boot_context->boot_interface_instance) != 99 0) { 100 ERROR("Cannot save boot interface\n"); 101 } 102 103 stm32mp1_io_setup(); 104 } 105