1/* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <platform_def.h> 11#include <stm32_gpio.h> 12#include <stm32mp1_rcc.h> 13 14#define GPIO_BANK_G_ADDRESS 0x50008000 15#define GPIO_TX_PORT 11 16#define GPIO_TX_SHIFT (GPIO_TX_PORT << 1) 17#define GPIO_TX_ALT_SHIFT ((GPIO_TX_PORT - GPIO_ALT_LOWER_LIMIT) << 2) 18#define STM32MP1_HSI_CLK 64000000 19 20 .globl platform_mem_init 21 .globl plat_report_exception 22 .globl plat_get_my_entrypoint 23 .globl plat_secondary_cold_boot_setup 24 .globl plat_reset_handler 25 .globl plat_is_my_cpu_primary 26 .globl plat_my_core_pos 27 .globl plat_crash_console_init 28 .globl plat_crash_console_flush 29 .globl plat_crash_console_putc 30 .globl plat_panic_handler 31 32func platform_mem_init 33 /* Nothing to do, don't need to init SYSRAM */ 34 bx lr 35endfunc platform_mem_init 36 37func plat_report_exception 38 bx lr 39endfunc plat_report_exception 40 41func plat_reset_handler 42 bx lr 43endfunc plat_reset_handler 44 45 /* ------------------------------------------------------------------ 46 * unsigned long plat_get_my_entrypoint (void); 47 * 48 * Main job of this routine is to distinguish between a cold and warm 49 * boot. 50 * 51 * Currently supports only cold boot 52 * ------------------------------------------------------------------ 53 */ 54func plat_get_my_entrypoint 55 mov r0, #0 56 bx lr 57endfunc plat_get_my_entrypoint 58 59 /* --------------------------------------------- 60 * void plat_secondary_cold_boot_setup (void); 61 * 62 * Cold-booting secondary CPUs is not supported. 63 * --------------------------------------------- 64 */ 65func plat_secondary_cold_boot_setup 66 b . 67endfunc plat_secondary_cold_boot_setup 68 69 /* ----------------------------------------------------- 70 * unsigned int plat_is_my_cpu_primary (void); 71 * 72 * Find out whether the current cpu is the primary cpu. 73 * ----------------------------------------------------- 74 */ 75func plat_is_my_cpu_primary 76 ldcopr r0, MPIDR 77 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) 78 and r0, r1 79 cmp r0, #STM32MP1_PRIMARY_CPU 80 moveq r0, #1 81 movne r0, #0 82 bx lr 83endfunc plat_is_my_cpu_primary 84 85 /* ------------------------------------------- 86 * int plat_stm32mp1_get_core_pos(int mpidr); 87 * 88 * Return CorePos = (ClusterId * 4) + CoreId 89 * ------------------------------------------- 90 */ 91func plat_stm32mp1_get_core_pos 92 and r1, r0, #MPIDR_CPU_MASK 93 and r0, r0, #MPIDR_CLUSTER_MASK 94 add r0, r1, r0, LSR #6 95 bx lr 96endfunc plat_stm32mp1_get_core_pos 97 98 /* ------------------------------------ 99 * unsigned int plat_my_core_pos(void) 100 * ------------------------------------ 101 */ 102func plat_my_core_pos 103 ldcopr r0, MPIDR 104 b plat_stm32mp1_get_core_pos 105endfunc plat_my_core_pos 106 107 /* --------------------------------------------- 108 * int plat_crash_console_init(void) 109 * 110 * Initialize the crash console without a C Runtime stack. 111 * --------------------------------------------- 112 */ 113func plat_crash_console_init 114 /* Enable GPIOs for UART4 TX */ 115 ldr r1, =(RCC_BASE + RCC_MP_AHB4ENSETR) 116 ldr r2, [r1] 117 /* Configure GPIO G11 */ 118 orr r2, r2, #RCC_MP_AHB4ENSETR_GPIOGEN 119 str r2, [r1] 120 ldr r1, =GPIO_BANK_G_ADDRESS 121 /* Set GPIO mode alternate */ 122 ldr r2, [r1, #GPIO_MODE_OFFSET] 123 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT) 124 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT) 125 str r2, [r1, #GPIO_MODE_OFFSET] 126 /* Set GPIO speed low */ 127 ldr r2, [r1, #GPIO_SPEED_OFFSET] 128 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT) 129 str r2, [r1, #GPIO_SPEED_OFFSET] 130 /* Set no-pull */ 131 ldr r2, [r1, #GPIO_PUPD_OFFSET] 132 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT) 133 str r2, [r1, #GPIO_PUPD_OFFSET] 134 /* Set alternate AF6 */ 135 ldr r2, [r1, #GPIO_AFRH_OFFSET] 136 bic r2, r2, #(GPIO_ALTERNATE_MASK << GPIO_TX_ALT_SHIFT) 137 orr r2, r2, #(GPIO_ALTERNATE_6 << GPIO_TX_ALT_SHIFT) 138 str r2, [r1, #GPIO_AFRH_OFFSET] 139 140 /* Enable UART clock, with HSI source */ 141 ldr r1, =(RCC_BASE + RCC_UART24CKSELR) 142 mov r2, #RCC_UART24CKSELR_HSI 143 str r2, [r1] 144 ldr r1, =(RCC_BASE + RCC_MP_APB1ENSETR) 145 ldr r2, [r1] 146 orr r2, r2, #RCC_MP_APB1ENSETR_UART4EN 147 str r2, [r1] 148 149 ldr r0, =STM32MP1_DEBUG_USART_BASE 150 ldr r1, =STM32MP1_HSI_CLK 151 ldr r2, =STM32MP1_UART_BAUDRATE 152 b console_core_init 153endfunc plat_crash_console_init 154 155 /* --------------------------------------------- 156 * int plat_crash_console_flush(void) 157 * 158 * Flush the crash console without a C Runtime stack. 159 * --------------------------------------------- 160 */ 161func plat_crash_console_flush 162 ldr r1, =STM32MP1_DEBUG_USART_BASE 163 b console_core_flush 164endfunc plat_crash_console_flush 165 166 /* --------------------------------------------- 167 * int plat_crash_console_putc(int c) 168 * 169 * Print a character on the crash console without a C Runtime stack. 170 * Clobber list : r1 - r3 171 * 172 * In case of bootloading through uart, we keep console crash as this. 173 * Characters could be sent to the programmer, but will be ignored. 174 * No specific code in that case. 175 * --------------------------------------------- 176 */ 177func plat_crash_console_putc 178 ldr r1, =STM32MP1_DEBUG_USART_BASE 179 b console_core_putc 180endfunc plat_crash_console_putc 181