1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <boot_api.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <delay_timer.h> 14 #include <desc_image_load.h> 15 #include <generic_delay_timer.h> 16 #include <mmio.h> 17 #include <platform.h> 18 #include <platform_def.h> 19 #include <stm32mp1_clk.h> 20 #include <stm32mp1_dt.h> 21 #include <stm32mp1_pmic.h> 22 #include <stm32mp1_private.h> 23 #include <stm32mp1_context.h> 24 #include <stm32mp1_pwr.h> 25 #include <stm32mp1_rcc.h> 26 #include <stm32mp1_reset.h> 27 #include <string.h> 28 #include <xlat_tables_v2.h> 29 30 void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1, 31 u_register_t arg2, u_register_t arg3) 32 { 33 stm32mp1_save_boot_ctx_address(arg0); 34 } 35 36 void bl2_platform_setup(void) 37 { 38 if (dt_check_pmic()) { 39 initialize_pmic(); 40 } 41 42 INFO("BL2 runs SP_MIN setup\n"); 43 } 44 45 void bl2_el3_plat_arch_setup(void) 46 { 47 int32_t result; 48 struct dt_node_info dt_dev_info; 49 const char *board_model; 50 boot_api_context_t *boot_context = 51 (boot_api_context_t *)stm32mp1_get_boot_ctx_address(); 52 uint32_t clk_rate; 53 54 /* 55 * Disable the backup domain write protection. 56 * The protection is enable at each reset by hardware 57 * and must be disabled by software. 58 */ 59 mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP); 60 61 while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) { 62 ; 63 } 64 65 /* Reset backup domain on cold boot cases */ 66 if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 67 mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 68 69 while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) == 70 0U) { 71 ; 72 } 73 74 mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST); 75 } 76 77 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 78 BL_CODE_END - BL_CODE_BASE, 79 MT_CODE | MT_SECURE); 80 81 /* Prevent corruption of preloaded BL32 */ 82 mmap_add_region(BL32_BASE, BL32_BASE, 83 BL32_LIMIT - BL32_BASE, 84 MT_MEMORY | MT_RO | MT_SECURE); 85 86 /* Prevent corruption of preloaded Device Tree */ 87 mmap_add_region(DTB_BASE, DTB_BASE, 88 DTB_LIMIT - DTB_BASE, 89 MT_MEMORY | MT_RO | MT_SECURE); 90 91 configure_mmu(); 92 93 generic_delay_timer_init(); 94 95 if (dt_open_and_check() < 0) { 96 panic(); 97 } 98 99 if (stm32mp1_clk_probe() < 0) { 100 panic(); 101 } 102 103 if (stm32mp1_clk_init() < 0) { 104 panic(); 105 } 106 107 result = dt_get_stdout_uart_info(&dt_dev_info); 108 109 if ((result <= 0) || 110 (dt_dev_info.status == 0U) || 111 (dt_dev_info.clock < 0) || 112 (dt_dev_info.reset < 0)) { 113 goto skip_console_init; 114 } 115 116 if (dt_set_stdout_pinctrl() != 0) { 117 goto skip_console_init; 118 } 119 120 if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) { 121 goto skip_console_init; 122 } 123 124 stm32mp1_reset_assert((uint32_t)dt_dev_info.reset); 125 udelay(2); 126 stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset); 127 mdelay(1); 128 129 clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock); 130 131 if (console_init(dt_dev_info.base, clk_rate, 132 STM32MP1_UART_BAUDRATE) == 0) { 133 panic(); 134 } 135 136 board_model = dt_get_board_model(); 137 if (board_model != NULL) { 138 NOTICE("%s\n", board_model); 139 } 140 141 skip_console_init: 142 143 if (stm32_save_boot_interface(boot_context->boot_interface_selected, 144 boot_context->boot_interface_instance) != 145 0) { 146 ERROR("Cannot save boot interface\n"); 147 } 148 149 stm32mp1_io_setup(); 150 } 151