1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <arch.h> 7 #include <arch_helpers.h> 8 #include <arm_xlat_tables.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <plat_arm.h> 13 #include <platform_def.h> 14 #include <platform.h> 15 #include <secure_partition.h> 16 17 extern const mmap_region_t plat_arm_mmap[]; 18 19 /* Weak definitions may be overridden in specific ARM standard platform */ 20 #pragma weak plat_get_ns_image_entrypoint 21 #pragma weak plat_arm_get_mmap 22 23 /* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid 24 * conflicts with the definition in plat/common. */ 25 #if ERROR_DEPRECATED 26 #pragma weak plat_get_syscnt_freq2 27 #endif 28 29 /* 30 * Set up the page tables for the generic and platform-specific memory regions. 31 * The size of the Trusted SRAM seen by the BL image must be specified as well 32 * as an array specifying the generic memory regions which can be; 33 * - Code section; 34 * - Read-only data section; 35 * - Coherent memory region, if applicable. 36 */ 37 38 void arm_setup_page_tables(const mmap_region_t bl_regions[], 39 const mmap_region_t plat_regions[]) 40 { 41 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 42 const mmap_region_t *regions = bl_regions; 43 44 while (regions->size != 0U) { 45 VERBOSE("Region: 0x%lx - 0x%lx has attributes 0x%x\n", 46 regions->base_va, 47 (regions->base_va + regions->size), 48 regions->attr); 49 regions++; 50 } 51 #endif 52 /* 53 * Map the Trusted SRAM with appropriate memory attributes. 54 * Subsequent mappings will adjust the attributes for specific regions. 55 */ 56 mmap_add(bl_regions); 57 /* Now (re-)map the platform-specific memory regions */ 58 mmap_add(plat_regions); 59 60 /* Create the page tables to reflect the above mappings */ 61 init_xlat_tables(); 62 } 63 64 uintptr_t plat_get_ns_image_entrypoint(void) 65 { 66 #ifdef PRELOADED_BL33_BASE 67 return PRELOADED_BL33_BASE; 68 #else 69 return PLAT_ARM_NS_IMAGE_OFFSET; 70 #endif 71 } 72 73 /******************************************************************************* 74 * Gets SPSR for BL32 entry 75 ******************************************************************************/ 76 uint32_t arm_get_spsr_for_bl32_entry(void) 77 { 78 /* 79 * The Secure Payload Dispatcher service is responsible for 80 * setting the SPSR prior to entry into the BL32 image. 81 */ 82 return 0; 83 } 84 85 /******************************************************************************* 86 * Gets SPSR for BL33 entry 87 ******************************************************************************/ 88 #ifndef AARCH32 89 uint32_t arm_get_spsr_for_bl33_entry(void) 90 { 91 unsigned int mode; 92 uint32_t spsr; 93 94 /* Figure out what mode we enter the non-secure world in */ 95 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 96 97 /* 98 * TODO: Consider the possibility of specifying the SPSR in 99 * the FIP ToC and allowing the platform to have a say as 100 * well. 101 */ 102 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 103 return spsr; 104 } 105 #else 106 /******************************************************************************* 107 * Gets SPSR for BL33 entry 108 ******************************************************************************/ 109 uint32_t arm_get_spsr_for_bl33_entry(void) 110 { 111 unsigned int hyp_status, mode, spsr; 112 113 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 114 115 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 116 117 /* 118 * TODO: Consider the possibility of specifying the SPSR in 119 * the FIP ToC and allowing the platform to have a say as 120 * well. 121 */ 122 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 123 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 124 return spsr; 125 } 126 #endif /* AARCH32 */ 127 128 /******************************************************************************* 129 * Configures access to the system counter timer module. 130 ******************************************************************************/ 131 #ifdef ARM_SYS_TIMCTL_BASE 132 void arm_configure_sys_timer(void) 133 { 134 unsigned int reg_val; 135 136 /* Read the frequency of the system counter */ 137 unsigned int freq_val = plat_get_syscnt_freq2(); 138 139 #if ARM_CONFIG_CNTACR 140 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 141 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 142 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 143 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); 144 #endif /* ARM_CONFIG_CNTACR */ 145 146 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); 147 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 148 149 /* 150 * Initialize CNTFRQ register in CNTCTLBase frame. The CNTFRQ 151 * system register initialized during psci_arch_setup() is different 152 * from this and has to be updated independently. 153 */ 154 mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); 155 156 #ifdef PLAT_juno 157 /* 158 * Initialize CNTFRQ register in Non-secure CNTBase frame. 159 * This is only required for Juno, because it doesn't follow ARM ARM 160 * in that the value updated in CNTFRQ is not reflected in CNTBASE_CNTFRQ. 161 * Hence update the value manually. 162 */ 163 mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASE_CNTFRQ, freq_val); 164 #endif 165 } 166 #endif /* ARM_SYS_TIMCTL_BASE */ 167 168 /******************************************************************************* 169 * Returns ARM platform specific memory map regions. 170 ******************************************************************************/ 171 const mmap_region_t *plat_arm_get_mmap(void) 172 { 173 return plat_arm_mmap; 174 } 175 176 #ifdef ARM_SYS_CNTCTL_BASE 177 178 unsigned int plat_get_syscnt_freq2(void) 179 { 180 unsigned int counter_base_frequency; 181 182 /* Read the frequency from Frequency modes table */ 183 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); 184 185 /* The first entry of the frequency modes table must not be 0 */ 186 if (counter_base_frequency == 0) 187 panic(); 188 189 return counter_base_frequency; 190 } 191 192 #endif /* ARM_SYS_CNTCTL_BASE */ 193 194 #if SDEI_SUPPORT 195 /* 196 * Translate SDEI entry point to PA, and perform standard ARM entry point 197 * validation on it. 198 */ 199 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode) 200 { 201 uint64_t par, pa; 202 uint32_t scr_el3; 203 204 /* Doing Non-secure address translation requires SCR_EL3.NS set */ 205 scr_el3 = read_scr_el3(); 206 write_scr_el3(scr_el3 | SCR_NS_BIT); 207 isb(); 208 209 assert((client_mode == MODE_EL2) || (client_mode == MODE_EL1)); 210 if (client_mode == MODE_EL2) { 211 /* 212 * Translate entry point to Physical Address using the EL2 213 * translation regime. 214 */ 215 ats1e2r(ep); 216 } else { 217 /* 218 * Translate entry point to Physical Address using the EL1&0 219 * translation regime, including stage 2. 220 */ 221 ats12e1r(ep); 222 } 223 isb(); 224 par = read_par_el1(); 225 226 /* Restore original SCRL_EL3 */ 227 write_scr_el3(scr_el3); 228 isb(); 229 230 /* If the translation resulted in fault, return failure */ 231 if ((par & PAR_F_MASK) != 0) 232 return -1; 233 234 /* Extract Physical Address from PAR */ 235 pa = (par & (PAR_ADDR_MASK << PAR_ADDR_SHIFT)); 236 237 /* Perform NS entry point validation on the physical address */ 238 return arm_validate_ns_entrypoint(pa); 239 } 240 #endif 241