feat(d128): add support for FEAT_D128

This patch disables trapping to EL3 when the FEAT_D128
specific registers are accessed by setting the SCR_EL3.D128En bit.

If FEAT_D128 is implemented, then FEA

feat(d128): add support for FEAT_D128

This patch disables trapping to EL3 when the FEAT_D128
specific registers are accessed by setting the SCR_EL3.D128En bit.

If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented.
With FEAT_SYSREG128 certain system registers are treated as 128-bit,
so we should be context saving and restoring 128-bits instead of 64-bit
when FEAT_D128 is enabled.

FEAT_SYSREG128 adds support for MRRS and MSRR instruction which
helps us to read write to 128-bit system register.
Refer to Arm Architecture Manual for further details.

Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.

Change-Id: I1a53db5eac29e56c8fbdcd4961ede3abfcb2411a
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(intel): update Agilex5 warm reset subroutines

Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secon

fix(intel): update Agilex5 warm reset subroutines

Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secondary core boot request markup in BL31.
Perform CACHE flush/clean ops in case of warm reset request also.

Change-Id: I7d33e362a3a513c60c8333e062ce832aa7facf38
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): add in JTAG ID for Linux FCS

This is for SMMU and Remapper enabled/disabled for
Linux FCS feature. The JTAG ID is to determine which
Agilex5 model shall be implemented.

Change-Id: Ib10d

fix(intel): add in JTAG ID for Linux FCS

This is for SMMU and Remapper enabled/disabled for
Linux FCS feature. The JTAG ID is to determine which
Agilex5 model shall be implemented.

Change-Id: Ib10d0062de8f6e27413af3dd271d97b9c2e5c079
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): update BL2 platform specific functions

Update and initialize the BL2 EL3 functions for agilex5
platform.

Change-Id: I673c622dfe4ff71d77edfa0866ebf6cd7163d793
Signed-off-by: Girisha Den

feat(intel): update BL2 platform specific functions

Update and initialize the BL2 EL3 functions for agilex5
platform.

Change-Id: I673c622dfe4ff71d77edfa0866ebf6cd7163d793
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n

feat(intel): add build option for boot source

Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.

Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.

Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): correct macro naming" into integration

Merge "feat(intel): pinmux and power manager config for Agilex5 platform" into integration

Merge "fix(intel): update all the platforms hand-off data offset value" into integration

Merge "feat(cpus): add support for cortex-a720ae" into integration

Merge "fix(tc): retain NS timer frame ID for TC2 as 0" into integration

fix(intel): correct macro naming

Correct macro naming to meet define macro standard.

Change-Id: Id0a091d67ef879a0f4c048bd9c2169c603ff4ce9
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

Merge "fix(allwinner): enable dtb modifications for CPU idle states to the rich OS" into integration

feat(intel): pinmux and power manager config for Agilex5 platform

Read the hand-off data and configure the pinmux
select, IO control, IO delay and use FPGA switch.
Configure the power manager PSS SR

feat(intel): pinmux and power manager config for Agilex5 platform

Read the hand-off data and configure the pinmux
select, IO control, IO delay and use FPGA switch.
Configure the power manager PSS SRAM power gate.

Change-Id: I2241018cbf2828182e8af84ddb214ce57e9f242a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Ic

fix(intel): update all the platforms hand-off data offset value

Move the hand-off data offset value from the common
platform header file to each socfpga platform specific
header file.

Change-Id: Icfe917f788814c329659c44e298cf05d6e3d0dd9
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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refactor(fvp): add support for cluster power-on

All new FVP's have incorporated the following PYSR bits

bit 31 is cluster ON status
bit 30 is core ON status
bit 29 is thread ON status

So add suppo

refactor(fvp): add support for cluster power-on

All new FVP's have incorporated the following PYSR bits

bit 31 is cluster ON status
bit 30 is core ON status
bit 29 is thread ON status

So add support to check cluster power ON which is supported from
affinity-level-2

But older cores with no DSU still uses affinity-level-1 for cluster
power-on status.

Ref: https://developer.arm.com/documentation/100964/1125/Base-Platform/Base---components

Change-Id: Id86811b14685d9ca900021301e5e8b7d52189963
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge "fix(intel): fix CCU for cache maintenance" into integration

Merge "fix(intel): flush L1/L2/L3/Sys cache before HPS cold reset" into integration

Merge "fix(intel): update preloaded_bl33_base for legacy product" into integration

Merge "feat(intel): direct boot from TF-A to Linux for Agilex" into integration

chore(fvp): use correct dts for dynamiq cores

The default dts doesn't describe the core topology correctly - it uses a
two level affinity, while new cores use 3 level with MPIDR_EL1.MT set.
As a res

chore(fvp): use correct dts for dynamiq cores

The default dts doesn't describe the core topology correctly - it uses a
two level affinity, while new cores use 3 level with MPIDR_EL1.MT set.
As a result Linux doesn't discover secondary cores correctly unless this
is specifically provided on the command line. CI already accounts for
this in tf_config/fvp-dynamiq-aarch64-only.

Change-Id: I137b213cfc48d98b8856c113d4ec0bf6474d3e2d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <m

fix(stm32mp2): set PLAT_MAX_PWR_LVL to one

Set maximum power level to 1 as power management isn't implemented yet.

Change-Id: I26cefbb5e199944d371bf06a76b2c41f73d38585
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_U

feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_UNUSED_NS_EL2 defined to Iiitialize the unused EL2
registers.

Change BL33 spsr parameter in bl2_mem_params_descs[] to use MODE_EL2
or MODE_EL1 depending on this flag. Default to MODE_EL1 as kernel
isn't able to boot at EL2 yet.

Change-Id: I6a8b35280d454d8140d7b28f0a5fc9b9a5093d6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>

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feat(stm32mp2): disable unsupported features

SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.

Change-Id: I323fb74103

feat(stm32mp2): disable unsupported features

SPE and SVE for non-secure world are not supported on Arm v8.0.
Disable the corresponding flags. This also saves a bit of memory.

Change-Id: I323fb7410393ea9711759be4c47848316fb68860
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>

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feat(amd): populate handoff from TL

Handoff structures are populated by executable entry point
information tag based bl32/bl33 entries present in transfer list.

The upstream code is having problem

feat(amd): populate handoff from TL

Handoff structures are populated by executable entry point
information tag based bl32/bl33 entries present in transfer list.

The upstream code is having problem with the last TL entry
particularly when the tags for two entries are same.
While tlc tool dumps all entries correctly, transfer_list_dump() in
upstream code does not provide information about the last entry in TL.

Enabling TRANSFER_LIST also enables BL1_SOURCES and BL2_SOURCES in
transfer_list.mk thereby enabling bl1/bl2 builds.
bl1/bl2 builds are disabled by turning off NEED_BL1/NEED_BL2
build flags.

Change-Id: I55ddccc1ab266cc5a609423d304a5e5c282e17f6
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge changes I8d62253e,I320a0585 into integration

* changes:
feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup
feat(stm32mp2): add BL31 device tree support