1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include <arch_helpers.h> 10 #include <assert.h> 11 #include <common/debug.h> 12 #include <common/tbbr/tbbr_img_def.h> 13 #include <drivers/cadence/cdns_nand.h> 14 #include <drivers/cadence/cdns_sdmmc.h> 15 #include <drivers/io/io_block.h> 16 #include <drivers/io/io_driver.h> 17 #include <drivers/io/io_fip.h> 18 #include <drivers/io/io_memmap.h> 19 #include <drivers/io/io_mtd.h> 20 #include <drivers/io/io_storage.h> 21 #include <drivers/mmc.h> 22 #include <drivers/partition/partition.h> 23 #include <lib/mmio.h> 24 #include <tools_share/firmware_image_package.h> 25 26 #include "drivers/sdmmc/sdmmc.h" 27 #include "socfpga_private.h" 28 #include "socfpga_ros.h" 29 30 31 #define PLAT_FIP_BASE (0) 32 #define PLAT_FIP_MAX_SIZE (0x8000000) 33 #define PLAT_MMC_DATA_BASE (0x10000000) 34 #define PLAT_MMC_DATA_SIZE (0x100000) 35 36 static const io_dev_connector_t *fip_dev_con; 37 static const io_dev_connector_t *boot_dev_con; 38 39 static io_mtd_dev_spec_t nand_dev_spec; 40 41 static uintptr_t fip_dev_handle; 42 static uintptr_t boot_dev_handle; 43 44 static const io_uuid_spec_t bl2_uuid_spec = { 45 .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, 46 }; 47 48 static const io_uuid_spec_t bl31_uuid_spec = { 49 .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, 50 }; 51 52 static const io_uuid_spec_t bl33_uuid_spec = { 53 .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, 54 }; 55 56 # if ARM_LINUX_KERNEL_AS_BL33 != 0 57 static const io_uuid_spec_t nt_fw_config_uuid_spec = { 58 .uuid = UUID_NT_FW_CONFIG, 59 }; 60 # endif 61 62 uintptr_t a2_lba_offset; 63 const char a2[] = {0xa2, 0x0}; 64 65 static const io_block_spec_t gpt_block_spec = { 66 .offset = 0, 67 .length = MMC_BLOCK_SIZE 68 }; 69 70 static int check_fip(const uintptr_t spec); 71 static int check_dev(const uintptr_t spec); 72 73 static io_block_dev_spec_t boot_dev_spec; 74 static int (*register_io_dev)(const io_dev_connector_t **); 75 76 static io_block_spec_t fip_spec = { 77 .offset = PLAT_FIP_BASE, 78 .length = PLAT_FIP_MAX_SIZE, 79 }; 80 81 struct plat_io_policy { 82 uintptr_t *dev_handle; 83 uintptr_t image_spec; 84 int (*check)(const uintptr_t spec); 85 }; 86 87 static const struct plat_io_policy policies[] = { 88 [FIP_IMAGE_ID] = { 89 &boot_dev_handle, 90 (uintptr_t)&fip_spec, 91 check_dev 92 }, 93 [BL2_IMAGE_ID] = { 94 &fip_dev_handle, 95 (uintptr_t)&bl2_uuid_spec, 96 check_fip 97 }, 98 [BL31_IMAGE_ID] = { 99 &fip_dev_handle, 100 (uintptr_t)&bl31_uuid_spec, 101 check_fip 102 }, 103 [BL33_IMAGE_ID] = { 104 &fip_dev_handle, 105 (uintptr_t) &bl33_uuid_spec, 106 check_fip 107 }, 108 # if ARM_LINUX_KERNEL_AS_BL33 != 0 109 [NT_FW_CONFIG_ID] = { 110 &fip_dev_handle, 111 (uintptr_t)&nt_fw_config_uuid_spec, 112 check_fip 113 }, 114 # endif 115 [GPT_IMAGE_ID] = { 116 &boot_dev_handle, 117 (uintptr_t) &gpt_block_spec, 118 check_dev 119 }, 120 }; 121 122 static int check_dev(const uintptr_t spec) 123 { 124 int result; 125 uintptr_t local_handle; 126 127 result = io_dev_init(boot_dev_handle, (uintptr_t)NULL); 128 if (result == 0) { 129 result = io_open(boot_dev_handle, spec, &local_handle); 130 if (result == 0) 131 io_close(local_handle); 132 } 133 return result; 134 } 135 136 static int check_fip(const uintptr_t spec) 137 { 138 int result; 139 uintptr_t local_image_handle; 140 141 result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 142 if (result == 0) { 143 result = io_open(fip_dev_handle, spec, &local_image_handle); 144 if (result == 0) 145 io_close(local_image_handle); 146 } 147 return result; 148 } 149 150 void socfpga_io_setup(int boot_source, unsigned long offset) 151 { 152 int result; 153 fip_spec.offset = offset; 154 155 switch (boot_source) { 156 case BOOT_SOURCE_SDMMC: 157 register_io_dev = ®ister_io_dev_block; 158 boot_dev_spec.buffer.offset = PLAT_MMC_DATA_BASE; 159 boot_dev_spec.buffer.length = SOCFPGA_MMC_BLOCK_SIZE; 160 boot_dev_spec.ops.read = SDMMC_READ_BLOCKS; 161 boot_dev_spec.ops.write = SDMMC_WRITE_BLOCKS; 162 boot_dev_spec.block_size = MMC_BLOCK_SIZE; 163 break; 164 165 case BOOT_SOURCE_QSPI: 166 register_io_dev = ®ister_io_dev_memmap; 167 break; 168 169 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 170 case BOOT_SOURCE_NAND: 171 register_io_dev = ®ister_io_dev_mtd; 172 nand_dev_spec.ops.init = cdns_nand_init_mtd; 173 nand_dev_spec.ops.read = cdns_nand_read; 174 nand_dev_spec.ops.write = NULL; 175 break; 176 #endif 177 178 default: 179 ERROR("Unsupported boot source\n"); 180 panic(); 181 break; 182 } 183 184 result = (*register_io_dev)(&boot_dev_con); 185 assert(result == 0); 186 187 result = register_io_dev_fip(&fip_dev_con); 188 assert(result == 0); 189 190 if (boot_source == BOOT_SOURCE_NAND) { 191 result = io_dev_open(boot_dev_con, (uintptr_t)&nand_dev_spec, 192 &boot_dev_handle); 193 } else { 194 result = io_dev_open(boot_dev_con, (uintptr_t)&boot_dev_spec, 195 &boot_dev_handle); 196 } 197 assert(result == 0); 198 199 result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); 200 assert(result == 0); 201 202 if (boot_source == BOOT_SOURCE_SDMMC) { 203 partition_init(GPT_IMAGE_ID); 204 fip_spec.offset = get_partition_entry(a2)->start; 205 } 206 207 (void)result; 208 } 209 210 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 211 uintptr_t *image_spec) 212 { 213 int result; 214 const struct plat_io_policy *policy; 215 216 assert(image_id < ARRAY_SIZE(policies)); 217 218 policy = &policies[image_id]; 219 result = policy->check(policy->image_spec); 220 assert(result == 0); 221 222 *image_spec = policy->image_spec; 223 *dev_handle = *(policy->dev_handle); 224 225 return result; 226 } 227