1# 2# Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25ifeq (${HW_ASSISTED_COHERENCY}, 0) 26FVP_DT_PREFIX := fvp-base-gicv3-psci 27else 28FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 29endif 30# fdts is wrong otherwise 31 32# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 33# the FVP platform. This option defaults to 256. 34FVP_TRUSTED_SRAM_SIZE := 256 35 36# Macro to enable helpers for running SPM tests. Disabled by default. 37PLAT_TEST_SPM := 0 38 39# By default dont build CPUs with no FVP model. 40BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 41 42ENABLE_FEAT_AMU := 2 43ENABLE_FEAT_AMUv1p1 := 2 44ENABLE_FEAT_HCX := 2 45ENABLE_FEAT_RNG := 2 46ENABLE_FEAT_TWED := 2 47ENABLE_FEAT_GCS := 2 48 49ifeq (${ARCH}, aarch64) 50 51ifeq (${SPM_MM}, 0) 52ifeq (${CTX_INCLUDE_FPREGS}, 0) 53 ENABLE_SME_FOR_NS := 2 54 ENABLE_SME2_FOR_NS := 2 55else 56 ENABLE_SVE_FOR_NS := 0 57 ENABLE_SME_FOR_NS := 0 58 ENABLE_SME2_FOR_NS := 0 59endif 60endif 61 62 ENABLE_BRBE_FOR_NS := 2 63 ENABLE_TRBE_FOR_NS := 2 64endif 65 66ENABLE_SYS_REG_TRACE_FOR_NS := 2 67ENABLE_FEAT_CSV2_2 := 2 68ENABLE_FEAT_CSV2_3 := 2 69ENABLE_FEAT_DEBUGV8P9 := 2 70ENABLE_FEAT_DIT := 2 71ENABLE_FEAT_PAN := 2 72ENABLE_FEAT_VHE := 2 73CTX_INCLUDE_NEVE_REGS := 2 74ENABLE_FEAT_SEL2 := 2 75ENABLE_TRF_FOR_NS := 2 76ENABLE_FEAT_ECV := 2 77ENABLE_FEAT_FGT := 2 78ENABLE_FEAT_FGT2 := 2 79ENABLE_FEAT_TCR2 := 2 80ENABLE_FEAT_S2PIE := 2 81ENABLE_FEAT_S1PIE := 2 82ENABLE_FEAT_S2POE := 2 83ENABLE_FEAT_S1POE := 2 84ENABLE_FEAT_MTE2 := 2 85 86# The FVP platform depends on this macro to build with correct GIC driver. 87$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 88 89# Pass FVP_CLUSTER_COUNT to the build system. 90$(eval $(call add_define,FVP_CLUSTER_COUNT)) 91 92# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 93$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 94 95# Pass FVP_MAX_PE_PER_CPU to the build system. 96$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 97 98# Pass FVP_GICR_REGION_PROTECTION to the build system. 99$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 100 101# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 102$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 103 104# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 105# choose the CCI driver , else the CCN driver 106ifeq ($(FVP_CLUSTER_COUNT), 0) 107$(error "Incorrect cluster count specified for FVP port") 108else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 109FVP_INTERCONNECT_DRIVER := FVP_CCI 110else 111FVP_INTERCONNECT_DRIVER := FVP_CCN 112endif 113 114$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 115 116# Choose the GIC sources depending upon the how the FVP will be invoked 117ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 118 119# The GIC model (GIC-600 or GIC-500) will be detected at runtime 120GICV3_SUPPORT_GIC600 := 1 121GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 122 123# Include GICv3 driver files 124include drivers/arm/gic/v3/gicv3.mk 125 126FVP_GIC_SOURCES := ${GICV3_SOURCES} \ 127 plat/common/plat_gicv3.c \ 128 plat/arm/common/arm_gicv3.c 129 130 ifeq ($(filter 1,${RESET_TO_BL2} \ 131 ${RESET_TO_BL31} ${RESET_TO_SP_MIN}),) 132 FVP_GIC_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 133 endif 134 135else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 136 137# No GICv4 extension 138GIC_ENABLE_V4_EXTN := 0 139$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 140 141# Include GICv2 driver files 142include drivers/arm/gic/v2/gicv2.mk 143 144FVP_GIC_SOURCES := ${GICV2_SOURCES} \ 145 plat/common/plat_gicv2.c \ 146 plat/arm/common/arm_gicv2.c 147 148FVP_DT_PREFIX := fvp-base-gicv2-psci 149else 150$(error "Incorrect GIC driver chosen on FVP port") 151endif 152 153ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 154FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 155else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 156FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 157 plat/arm/common/arm_ccn.c 158else 159$(error "Incorrect CCN driver chosen on FVP port") 160endif 161 162FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 163 plat/arm/board/fvp/fvp_security.c \ 164 plat/arm/common/arm_tzc400.c 165 166 167PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 168 -Iinclude/lib/psa 169 170 171PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 172 173FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 174 175ifeq (${ARCH}, aarch64) 176 177# select a different set of CPU files, depending on whether we compile for 178# hardware assisted coherency cores or not 179ifeq (${HW_ASSISTED_COHERENCY}, 0) 180# Cores used without DSU 181 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 182 lib/cpus/aarch64/cortex_a53.S \ 183 lib/cpus/aarch64/cortex_a57.S \ 184 lib/cpus/aarch64/cortex_a72.S \ 185 lib/cpus/aarch64/cortex_a73.S 186else 187# Cores used with DSU only 188 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 189 # AArch64-only cores 190 # TODO: add all cores to the appropriate lists 191 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 192 lib/cpus/aarch64/cortex_a65ae.S \ 193 lib/cpus/aarch64/cortex_a76.S \ 194 lib/cpus/aarch64/cortex_a76ae.S \ 195 lib/cpus/aarch64/cortex_a77.S \ 196 lib/cpus/aarch64/cortex_a78.S \ 197 lib/cpus/aarch64/cortex_a78_ae.S \ 198 lib/cpus/aarch64/cortex_a78c.S \ 199 lib/cpus/aarch64/cortex_a710.S \ 200 lib/cpus/aarch64/cortex_a715.S \ 201 lib/cpus/aarch64/cortex_a720.S \ 202 lib/cpus/aarch64/neoverse_n_common.S \ 203 lib/cpus/aarch64/neoverse_n1.S \ 204 lib/cpus/aarch64/neoverse_n2.S \ 205 lib/cpus/aarch64/neoverse_v1.S \ 206 lib/cpus/aarch64/neoverse_e1.S \ 207 lib/cpus/aarch64/cortex_x2.S \ 208 lib/cpus/aarch64/cortex_x4.S 209 endif 210 # AArch64/AArch32 cores 211 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 212 lib/cpus/aarch64/cortex_a75.S 213endif 214 215#Build AArch64-only CPUs with no FVP model yet. 216ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 217 FVP_CPU_LIBS += lib/cpus/aarch64/neoverse_n3.S \ 218 lib/cpus/aarch64/cortex_gelas.S \ 219 lib/cpus/aarch64/nevis.S \ 220 lib/cpus/aarch64/travis.S 221endif 222 223else 224FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 225 lib/cpus/aarch32/cortex_a57.S \ 226 lib/cpus/aarch32/cortex_a53.S 227endif 228 229BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 230 drivers/arm/sp805/sp805.c \ 231 drivers/delay_timer/delay_timer.c \ 232 drivers/io/io_semihosting.c \ 233 lib/semihosting/semihosting.c \ 234 lib/semihosting/${ARCH}/semihosting_call.S \ 235 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 236 plat/arm/board/fvp/fvp_bl1_setup.c \ 237 plat/arm/board/fvp/fvp_cpu_pwr.c \ 238 plat/arm/board/fvp/fvp_err.c \ 239 plat/arm/board/fvp/fvp_io_storage.c \ 240 plat/arm/board/fvp/fvp_topology.c \ 241 ${FVP_CPU_LIBS} \ 242 ${FVP_INTERCONNECT_SOURCES} 243 244ifeq (${USE_SP804_TIMER},1) 245BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 246else 247BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 248endif 249 250 251BL2_SOURCES += drivers/arm/sp805/sp805.c \ 252 drivers/io/io_semihosting.c \ 253 lib/utils/mem_region.c \ 254 lib/semihosting/semihosting.c \ 255 lib/semihosting/${ARCH}/semihosting_call.S \ 256 plat/arm/board/fvp/fvp_bl2_setup.c \ 257 plat/arm/board/fvp/fvp_err.c \ 258 plat/arm/board/fvp/fvp_io_storage.c \ 259 plat/arm/common/arm_nor_psci_mem_protect.c \ 260 ${FVP_SECURITY_SOURCES} 261 262 263ifeq (${COT_DESC_IN_DTB},1) 264BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 265endif 266 267ifeq (${ENABLE_RME},1) 268BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 269 plat/arm/board/fvp/fvp_cpu_pwr.c 270 271BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 272 plat/arm/board/fvp/fvp_realm_attest_key.c 273endif 274 275ifeq (${ENABLE_FEAT_RNG_TRAP},1) 276BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 277endif 278 279ifeq (${RESET_TO_BL2},1) 280BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 281 plat/arm/board/fvp/fvp_cpu_pwr.c \ 282 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 283 ${FVP_CPU_LIBS} \ 284 ${FVP_INTERCONNECT_SOURCES} 285endif 286 287ifeq (${USE_SP804_TIMER},1) 288BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 289endif 290 291BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 292 ${FVP_SECURITY_SOURCES} 293 294ifeq (${USE_SP804_TIMER},1) 295BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 296endif 297 298BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 299 drivers/arm/smmu/smmu_v3.c \ 300 drivers/delay_timer/delay_timer.c \ 301 drivers/cfi/v2m/v2m_flash.c \ 302 lib/utils/mem_region.c \ 303 plat/arm/board/fvp/fvp_bl31_setup.c \ 304 plat/arm/board/fvp/fvp_console.c \ 305 plat/arm/board/fvp/fvp_pm.c \ 306 plat/arm/board/fvp/fvp_topology.c \ 307 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 308 plat/arm/board/fvp/fvp_cpu_pwr.c \ 309 plat/arm/common/arm_nor_psci_mem_protect.c \ 310 ${FVP_CPU_LIBS} \ 311 ${FVP_GIC_SOURCES} \ 312 ${FVP_INTERCONNECT_SOURCES} \ 313 ${FVP_SECURITY_SOURCES} 314 315# Support for fconf in BL31 316# Added separately from the above list for better readability 317ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 318BL31_SOURCES += lib/fconf/fconf.c \ 319 lib/fconf/fconf_dyn_cfg_getter.c \ 320 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 321 322BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 323 324ifeq (${SEC_INT_DESC_IN_FCONF},1) 325BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 326endif 327 328endif 329 330ifeq (${USE_SP804_TIMER},1) 331BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 332else 333BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 334endif 335 336# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 337ifdef UNIX_MK 338FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 339FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 340 341FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 342$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 343 344ifeq (${TRANSFER_LIST}, 1) 345FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 346 ${PLAT}_tb_fw_config.dts \ 347 ) 348else 349FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 350 ${PLAT}_fw_config.dts \ 351 ${PLAT}_tb_fw_config.dts \ 352 ${PLAT}_soc_fw_config.dts \ 353 ${PLAT}_nt_fw_config.dts \ 354 ) 355 356FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 357FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 358FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 359 360ifeq (${SPD},tspd) 361FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 362FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 363 364# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 365$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 366endif 367 368ifeq (${SPD},spmd) 369 370ifeq ($(ARM_SPMC_MANIFEST_DTS),) 371ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 372endif 373 374FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 375FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 376 377# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 378$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 379endif 380 381# Add the FW_CONFIG to FIP and specify the same to certtool 382$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 383# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 384$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 385# Add the NT_FW_CONFIG to FIP and specify the same to certtool 386$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 387endif 388 389# Add the TB_FW_CONFIG to FIP and specify the same to certtool 390$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 391# Add the HW_CONFIG to FIP and specify the same to certtool 392$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 393endif 394 395ifeq (${TRANSFER_LIST}, 1) 396include lib/transfer_list/transfer_list.mk 397 398ifeq ($(RESET_TO_BL31), 1) 399HW_CONFIG := ${FVP_HW_CONFIG} 400FW_HANDOFF_SIZE := 20000 401 402TRANSFER_LIST_DTB_OFFSET := 0x20 403$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 404endif 405endif 406 407# Enable dynamic mitigation support by default 408DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 409 410ifneq (${ENABLE_FEAT_AMU},0) 411BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 412 lib/cpus/aarch64/cpuamu_helpers.S 413 414ifeq (${HW_ASSISTED_COHERENCY}, 1) 415BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 416 lib/cpus/aarch64/neoverse_n1_pubsub.c 417endif 418endif 419 420ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 421 ifeq (${ENABLE_FEAT_RAS},1) 422 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 423 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 424 else 425 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c 426 endif 427 else 428 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ea.c 429 endif 430endif 431 432ifneq (${ENABLE_STACK_PROTECTOR},0) 433PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 434endif 435 436# Enable the dynamic translation tables library. 437ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 438 ifeq (${ARCH},aarch32) 439 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 440 else # AArch64 441 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 442 endif 443endif 444 445ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 446 ifeq (${ARCH},aarch32) 447 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 448 else # AArch64 449 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 450 ifeq (${SPD},tspd) 451 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 452 endif 453 endif 454endif 455 456ifeq (${USE_DEBUGFS},1) 457 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 458endif 459 460# Add support for platform supplied linker script for BL31 build 461$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) 462 463ifneq (${RESET_TO_BL2}, 0) 464 override BL1_SOURCES = 465endif 466 467include plat/arm/board/common/board_common.mk 468include plat/arm/common/arm_common.mk 469 470ifeq (${MEASURED_BOOT},1) 471BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 472 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 473 lib/psa/measured_boot.c 474 475BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 476 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 477 lib/psa/measured_boot.c 478endif 479 480ifeq (${DRTM_SUPPORT}, 1) 481BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 482 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 483 plat/arm/board/fvp/fvp_drtm_err.c \ 484 plat/arm/board/fvp/fvp_drtm_measurement.c \ 485 plat/arm/board/fvp/fvp_drtm_stub.c \ 486 plat/arm/common/arm_dyn_cfg.c \ 487 plat/arm/board/fvp/fvp_err.c 488endif 489 490ifeq (${TRUSTED_BOARD_BOOT}, 1) 491BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 492BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 493 494# FVP being a development platform, enable capability to disable Authentication 495# dynamically if TRUSTED_BOARD_BOOT is set. 496DYN_DISABLE_AUTH := 1 497endif 498 499ifeq (${SPMC_AT_EL3}, 1) 500PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 501endif 502 503PSCI_OS_INIT_MODE := 1 504 505ifeq (${SPD},spmd) 506BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 507endif 508 509# Test specific macros, keep them at bottom of this file 510$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 511ifeq (${PLATFORM_TEST_EA_FFH}, 1) 512 ifeq (${FFH_SUPPORT}, 0) 513 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 514 endif 515 516endif 517 518$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 519ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 520 ifeq (${ENABLE_FEAT_RAS}, 0) 521 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 522 endif 523 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 524 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 525 endif 526endif 527 528$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 529ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 530 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 531 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 532 endif 533 ifeq (${ENABLE_SPMD_LP}, 0) 534 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 535 endif 536 ifeq (${ENABLE_FEAT_RAS}, 0) 537 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 538 endif 539 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 540 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 541 endif 542endif 543 544ifeq (${ERRATA_ABI_SUPPORT}, 1) 545include plat/arm/board/fvp/fvp_cpu_errata.mk 546endif 547 548# Build macro necessary for running SPM tests on FVP platform 549$(eval $(call add_define,PLAT_TEST_SPM)) 550