1 /* 2 * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <common/tbbr/tbbr_img_def.h> 15 #include <plat/common/common_def.h> 16 #include "socfpga_plat_def.h" 17 18 /* Platform Type */ 19 #define PLAT_SOCFPGA_STRATIX10 1 20 #define PLAT_SOCFPGA_AGILEX 2 21 #define PLAT_SOCFPGA_N5X 3 22 #define PLAT_SOCFPGA_AGILEX5 4 23 #define SIMICS_RUN 1 24 #define MAX_IO_MTD_DEVICES U(1) 25 26 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ 27 #define PLAT_CPU_RELEASE_ADDR 0xffd12210 28 29 /* Magic word to indicate L2 reset is completed */ 30 #define L2_RESET_DONE_STATUS 0x1228E5E7 31 32 /* Define next boot image name and offset */ 33 /* Get non-secure image entrypoint for BL33. Zephyr and Linux */ 34 #ifdef PRELOADED_BL33_BASE 35 #define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE 36 #else 37 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 38 #define PLAT_NS_IMAGE_OFFSET 0x80200000 39 #else 40 #define PLAT_NS_IMAGE_OFFSET 0x10000000 41 #endif 42 #endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */ 43 44 #define PLAT_QSPI_DATA_BASE (0x3C00000) 45 #define PLAT_NAND_DATA_BASE (0x0200000) 46 #define PLAT_SDMMC_DATA_BASE (0x0) 47 48 49 /******************************************************************************* 50 * Platform binary types for linking 51 ******************************************************************************/ 52 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 53 #define PLATFORM_LINKER_ARCH aarch64 54 55 /* SoCFPGA supports up to 124GB RAM */ 56 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 57 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 58 59 60 /******************************************************************************* 61 * Generic platform constants 62 ******************************************************************************/ 63 #define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0 64 65 /* Size of cacheable stacks */ 66 #define PLATFORM_STACK_SIZE 0x2000 67 68 /* PSCI related constant */ 69 #define PLAT_NUM_POWER_DOMAINS 5 70 #define PLAT_MAX_PWR_LVL 1 71 #define PLAT_MAX_RET_STATE 1 72 #define PLAT_MAX_OFF_STATE 2 73 #define PLATFORM_SYSTEM_COUNT U(1) 74 #define PLATFORM_CLUSTER_COUNT U(1) 75 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 76 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 77 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 78 PLATFORM_CLUSTER0_CORE_COUNT) 79 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 80 81 /* Interrupt related constant */ 82 83 #define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29 84 85 #define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8 86 #define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9 87 #define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10 88 #define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11 89 #define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12 90 #define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13 91 #define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14 92 #define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15 93 94 #define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 95 #define TSP_SEC_MEM_BASE BL32_BASE 96 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) 97 98 99 /******************************************************************************* 100 * BL31 specific defines. 101 ******************************************************************************/ 102 /* 103 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 104 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 105 * little space for growth. 106 */ 107 108 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 109 110 #define BL1_RO_BASE (0xffe00000) 111 #define BL1_RO_LIMIT (0xffe0f000) 112 #define BL1_RW_BASE (0xffe10000) 113 #define BL1_RW_LIMIT (0xffe1ffff) 114 #define BL1_RW_SIZE (0x14000) 115 116 #define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET 117 118 #define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16) 119 #define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8) 120 121 #define CMP_ENTRY 0xFFE3EFF8 122 123 #define PLAT_SEC_WARM_ENTRY 0 124 125 /******************************************************************************* 126 * Platform specific page table and MMU setup constants 127 ******************************************************************************/ 128 #define MAX_XLAT_TABLES 8 129 #define MAX_MMAP_REGIONS 16 130 131 /******************************************************************************* 132 * Declarations and constants to access the mailboxes safely. Each mailbox is 133 * aligned on the biggest cache line size in the platform. This is known only 134 * to the platform as it might have a combination of integrated and external 135 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 136 * line at any cache level. They could belong to different cpus/clusters & 137 * get written while being protected by different locks causing corruption of 138 * a valid mailbox address. 139 ******************************************************************************/ 140 #define CACHE_WRITEBACK_SHIFT 6 141 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 142 143 /******************************************************************************* 144 * UART related constants 145 ******************************************************************************/ 146 #define CRASH_CONSOLE_BASE PLAT_UART0_BASE 147 #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE 148 149 #define PLAT_BAUDRATE (115200) 150 #define PLAT_UART_CLOCK (100000000) 151 152 /******************************************************************************* 153 * PHY related constants 154 ******************************************************************************/ 155 156 #define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII 157 #define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII 158 #define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII 159 160 /******************************************************************************* 161 * GIC related constants 162 ******************************************************************************/ 163 #define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE 164 #define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE 165 166 /******************************************************************************* 167 * System counter frequency related constants 168 ******************************************************************************/ 169 170 /* 171 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 172 * terminology. On a GICv2 system or mode, the lists will be merged and treated 173 * as Group 0 interrupts. 174 */ 175 #define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \ 176 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \ 177 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \ 178 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \ 179 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 180 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \ 181 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 182 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \ 183 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \ 185 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \ 187 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 188 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \ 189 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 190 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \ 191 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \ 193 GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE) 194 195 #define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp) 196 197 #define MAX_IO_HANDLES 4 198 #define MAX_IO_DEVICES 4 199 #define MAX_IO_BLOCK_DEVICES 2 200 201 #ifndef __ASSEMBLER__ 202 struct socfpga_bl31_params { 203 param_header_t h; 204 image_info_t *bl31_image_info; 205 entry_point_info_t *bl32_ep_info; 206 image_info_t *bl32_image_info; 207 entry_point_info_t *bl33_ep_info; 208 image_info_t *bl33_image_info; 209 }; 210 #endif 211 212 #endif /* PLATFORM_DEF_H */ 213