1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved. 4 * Copyright (c) 2024, Altera Corporation. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLAT_SOCFPGA_DEF_H 10 #define PLAT_SOCFPGA_DEF_H 11 12 #include "agilex5_memory_controller.h" 13 #include "agilex5_system_manager.h" 14 15 #include <platform_def.h> 16 17 /* Platform Setting */ 18 #define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX5 19 #define BOOT_SOURCE BOOT_SOURCE_SDMMC 20 #define MMC_DEVICE_TYPE 1 /* MMC = 0, SD = 1 */ 21 #define XLAT_TABLES_V2 U(1) 22 #define PLAT_PRIMARY_CPU_A55 0x000 23 #define PLAT_PRIMARY_CPU_A76 0x200 24 #define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT 25 #define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT 26 #define PLAT_L2_RESET_REQ 0xB007C0DE 27 #define PLAT_TIMER_BASE_ADDR 0x10D01000 28 29 /* System Counter */ 30 /* TODO: Update back to 400MHz. 31 * This shall be updated to read from L4 clock instead of hardcoded. 32 */ 33 #define PLAT_SYS_COUNTER_FREQ_IN_TICKS U(400000000) 34 #define PLAT_SYS_COUNTER_FREQ_IN_MHZ U(400) 35 36 /* FPGA config helpers */ 37 #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x80400000 38 #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x82000000 39 40 /* QSPI Setting */ 41 #define CAD_QSPIDATA_OFST 0x10900000 42 #define CAD_QSPI_OFFSET 0x108d2000 43 44 /* SDMMC Setting */ 45 # if ARM_LINUX_KERNEL_AS_BL33 46 #define SOCFPGA_MMC_BLOCK_SIZE U(32768) 47 # else 48 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 49 # endif 50 51 /* Register Mapping */ 52 #define SOCFPGA_CCU_NOC_REG_BASE 0x1c000000 53 #define SOCFPGA_F2SDRAMMGR_REG_BASE 0x18001000 54 55 #define SOCFPGA_MMC_REG_BASE 0x10808000 56 #define SOCFPGA_MEMCTRL_REG_BASE 0x108CC000 57 #define SOCFPGA_RSTMGR_REG_BASE 0x10d11000 58 #define SOCFPGA_SYSMGR_REG_BASE 0x10d12000 59 #define SOCFPGA_PINMUX_REG_BASE 0x10d13000 60 #define SOCFPGA_NAND_REG_BASE 0x10B80000 61 #define SOCFPGA_ECC_QSPI_REG_BASE 0x10A22000 62 63 #define SOCFPGA_L4_PER_SCR_REG_BASE 0x10d21000 64 #define SOCFPGA_L4_SYS_SCR_REG_BASE 0x10d21100 65 #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0x10d21200 66 #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0x10d21300 67 68 /* Define maximum page size for NAND flash devices */ 69 #define PLATFORM_MTD_MAX_PAGE_SIZE U(0x2000) 70 71 /******************************************************************************* 72 * Platform memory map related constants 73 ******************************************************************************/ 74 #define DRAM_BASE (0x80000000) 75 #define DRAM_SIZE (0x80000000) 76 77 #define OCRAM_BASE (0x00000000) 78 #define OCRAM_SIZE (0x00080000) 79 80 #define MEM64_BASE (0x0080000000) 81 #define MEM64_SIZE (0x0080000000) 82 83 //128MB PSS 84 #define PSS_BASE (0x10000000) 85 #define PSS_SIZE (0x08000000) 86 87 //64MB MPFE 88 #define MPFE_BASE (0x18000000) 89 #define MPFE_SIZE (0x04000000) 90 91 //16MB CCU 92 #define CCU_BASE (0x1C000000) 93 #define CCU_SIZE (0x01000000) 94 95 //1MB GIC 96 #define GIC_BASE (0x1D000000) 97 #define GIC_SIZE (0x00100000) 98 99 #define BL2_BASE (0x00000000) 100 #define BL2_LIMIT (0x0007E000) 101 102 #define BL31_BASE (0x80000000) 103 #define BL31_LIMIT (0x82000000) 104 /******************************************************************************* 105 * UART related constants 106 ******************************************************************************/ 107 #define PLAT_UART0_BASE (0x10C02000) 108 #define PLAT_UART1_BASE (0x10C02100) 109 110 /******************************************************************************* 111 * WDT related constants 112 ******************************************************************************/ 113 #define WDT_BASE (0x10D00200) 114 115 /******************************************************************************* 116 * GIC related constants 117 ******************************************************************************/ 118 #define PLAT_GIC_BASE (0x1D000000) 119 #define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x20000) 120 #define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x00000) 121 #define PLAT_GICR_BASE (PLAT_GIC_BASE + 0x60000) 122 123 #define PLAT_INTEL_SOCFPGA_GICR_BASE PLAT_GICR_BASE 124 125 /******************************************************************************* 126 * SDMMC related pointer function 127 ******************************************************************************/ 128 #define SDMMC_READ_BLOCKS sdmmc_read_blocks 129 #define SDMMC_WRITE_BLOCKS sdmmc_write_blocks 130 131 /******************************************************************************* 132 * sysmgr.boot_scratch_cold6 & 7 (64bit) are used to indicate L2 reset 133 * is done and HPS should trigger warm reset via RMR_EL3. 134 ******************************************************************************/ 135 #define L2_RESET_DONE_REG 0x10D12218 136 137 #endif /* PLAT_SOCFPGA_DEF_H */ 138