1# 2# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Extra partitions used to find FIP, contains: 8# metadata (2) and fsbl-m (2) and the FIP partitions (default is 2). 9STM32_EXTRA_PARTS := 6 10 11include plat/st/common/common.mk 12 13CRASH_REPORTING := 1 14ENABLE_PIE := 1 15PROGRAMMABLE_RESET_ADDRESS := 1 16BL2_IN_XIP_MEM := 1 17 18# Disable features unsupported in ARMv8.0 19ENABLE_SPE_FOR_NS := 0 20ENABLE_SVE_FOR_NS := 0 21 22# Default Device tree 23DTB_FILE_NAME ?= stm32mp257f-ev1.dtb 24 25STM32MP25 := 1 26 27# STM32 image header version v2.2 28STM32_HEADER_VERSION_MAJOR := 2 29STM32_HEADER_VERSION_MINOR := 2 30 31# Set load address for serial boot devices 32DWL_BUFFER_BASE ?= 0x87000000 33 34# DDR types 35STM32MP_DDR3_TYPE ?= 0 36STM32MP_DDR4_TYPE ?= 0 37STM32MP_LPDDR4_TYPE ?= 0 38ifeq (${STM32MP_DDR3_TYPE},1) 39DDR_TYPE := ddr3 40endif 41ifeq (${STM32MP_DDR4_TYPE},1) 42DDR_TYPE := ddr4 43endif 44ifeq (${STM32MP_LPDDR4_TYPE},1) 45DDR_TYPE := lpddr4 46endif 47 48# DDR features 49STM32MP_DDR_DUAL_AXI_PORT := 1 50STM32MP_DDR_FIP_IO_STORAGE := 1 51 52# Device tree 53BL2_DTSI := stm32mp25-bl2.dtsi 54FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME))) 55BL31_DTSI := stm32mp25-bl31.dtsi 56FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dts,$(DTB_FILE_NAME))) 57 58# Macros and rules to build TF binary 59STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) 60STM32_LD_FILE := plat/st/stm32mp2/${ARCH}/stm32mp2.ld.S 61STM32_BINARY_MAPPING := plat/st/stm32mp2/${ARCH}/stm32mp2.S 62 63STM32MP_FW_CONFIG_NAME := $(patsubst %.dtb,%-fw-config.dtb,$(DTB_FILE_NAME)) 64STM32MP_FW_CONFIG := ${BUILD_PLAT}/fdts/$(STM32MP_FW_CONFIG_NAME) 65STM32MP_SOC_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl31.dtb,$(DTB_FILE_NAME))) 66ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 67STM32MP_DDR_FW_PATH ?= drivers/st/ddr/phy/firmware/bin/stm32mp2 68STM32MP_DDR_FW_NAME := ${DDR_TYPE}_pmu_train.bin 69STM32MP_DDR_FW := ${STM32MP_DDR_FW_PATH}/${STM32MP_DDR_FW_NAME} 70endif 71FDT_SOURCES += $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(STM32MP_FW_CONFIG_NAME))) 72# Add the FW_CONFIG to FIP and specify the same to certtool 73$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_FW_CONFIG},--fw-config)) 74# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 75$(eval $(call TOOL_ADD_IMG,STM32MP_SOC_FW_CONFIG,--soc-fw-config)) 76ifeq (${STM32MP_DDR_FIP_IO_STORAGE},1) 77# Add the FW_DDR to FIP and specify the same to certtool 78$(eval $(call TOOL_ADD_IMG,STM32MP_DDR_FW,--ddr-fw)) 79endif 80 81# Enable flags for C files 82$(eval $(call assert_booleans,\ 83 $(sort \ 84 STM32MP_DDR_DUAL_AXI_PORT \ 85 STM32MP_DDR_FIP_IO_STORAGE \ 86 STM32MP_DDR3_TYPE \ 87 STM32MP_DDR4_TYPE \ 88 STM32MP_LPDDR4_TYPE \ 89 STM32MP25 \ 90))) 91 92$(eval $(call assert_numerics,\ 93 $(sort \ 94 PLAT_PARTITION_MAX_ENTRIES \ 95 STM32_HEADER_VERSION_MAJOR \ 96 STM32_TF_A_COPIES \ 97))) 98 99$(eval $(call add_defines,\ 100 $(sort \ 101 DWL_BUFFER_BASE \ 102 PLAT_DEF_FIP_UUID \ 103 PLAT_PARTITION_MAX_ENTRIES \ 104 PLAT_TBBR_IMG_DEF \ 105 STM32_TF_A_COPIES \ 106 STM32MP_DDR_DUAL_AXI_PORT \ 107 STM32MP_DDR_FIP_IO_STORAGE \ 108 STM32MP_DDR3_TYPE \ 109 STM32MP_DDR4_TYPE \ 110 STM32MP_LPDDR4_TYPE \ 111 STM32MP25 \ 112))) 113 114# STM32MP2x is based on Cortex-A35, which is Armv8.0, and does not support BTI 115# Disable mbranch-protection to avoid adding useless code 116TF_CFLAGS += -mbranch-protection=none 117 118# Include paths and source files 119PLAT_INCLUDES += -Iplat/st/stm32mp2/include/ 120PLAT_INCLUDES += -Idrivers/st/ddr/phy/phyinit/include/ 121PLAT_INCLUDES += -Idrivers/st/ddr/phy/firmware/include/ 122 123PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S 124PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S 125PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S 126 127PLAT_BL_COMMON_SOURCES += drivers/st/pmic/stm32mp_pmic2.c \ 128 drivers/st/pmic/stpmic2.c \ 129 130PLAT_BL_COMMON_SOURCES += drivers/st/i2c/stm32_i2c.c 131 132PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/stm32mp2_private.c 133 134PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c \ 135 drivers/st/reset/stm32mp2_reset.c \ 136 plat/st/stm32mp2/stm32mp2_syscfg.c 137 138PLAT_BL_COMMON_SOURCES += drivers/st/clk/clk-stm32-core.c \ 139 drivers/st/clk/clk-stm32mp2.c 140 141BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c 142 143BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c \ 144 plat/st/stm32mp2/plat_ddr.c 145 146ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),) 147BL2_SOURCES += drivers/st/mmc/stm32_sdmmc2.c 148endif 149 150ifeq (${STM32MP_USB_PROGRAMMER},1) 151BL2_SOURCES += plat/st/stm32mp2/stm32mp2_usb_dfu.c 152endif 153 154BL2_SOURCES += drivers/st/ddr/stm32mp2_ddr.c \ 155 drivers/st/ddr/stm32mp2_ddr_helpers.c \ 156 drivers/st/ddr/stm32mp2_ram.c 157 158BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_c_initphyconfig.c \ 159 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_calcmb.c \ 160 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_i_loadpieimage.c \ 161 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_initstruct.c \ 162 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_isdbytedisabled.c \ 163 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_loadpieprodcode.c \ 164 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_mapdrvstren.c \ 165 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_progcsrskiptrain.c \ 166 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_reginterface.c \ 167 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_restore_sequence.c \ 168 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_sequence.c \ 169 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_softsetmb.c \ 170 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_custompretrain.c \ 171 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_saveretregs.c 172 173BL2_SOURCES += drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_d_loadimem.c \ 174 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_f_loaddmem.c \ 175 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_g_execfw.c \ 176 drivers/st/ddr/phy/phyinit/src/ddrphy_phyinit_writeoutmem.c \ 177 drivers/st/ddr/phy/phyinit/usercustom/ddrphy_phyinit_usercustom_g_waitfwdone.c 178 179# BL31 sources 180BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 181 182BL31_SOURCES += plat/st/stm32mp2/bl31_plat_setup.c \ 183 plat/st/stm32mp2/stm32mp2_pm.c \ 184 plat/st/stm32mp2/stm32mp2_topology.c 185# Generic GIC v2 186include drivers/arm/gic/v2/gicv2.mk 187 188BL31_SOURCES += ${GICV2_SOURCES} \ 189 plat/common/plat_gicv2.c \ 190 plat/st/common/stm32mp_gic.c 191 192# Generic PSCI 193BL31_SOURCES += plat/common/plat_psci_common.c 194 195# Compilation rules 196.PHONY: check_ddr_type 197.SUFFIXES: 198 199bl2: check_ddr_type 200 201check_ddr_type: 202 $(eval DDR_TYPE = $(shell echo $$(($(STM32MP_DDR3_TYPE) + \ 203 $(STM32MP_DDR4_TYPE) + \ 204 $(STM32MP_LPDDR4_TYPE))))) 205 @if [ ${DDR_TYPE} != 1 ]; then \ 206 echo "One and only one DDR type must be defined"; \ 207 false; \ 208 fi 209 210# Create DTB file for BL31 211${BUILD_PLAT}/fdts/%-bl31.dts: fdts/%.dts fdts/${BL31_DTSI} | $$(@D)/ 212 @echo '#include "$(patsubst fdts/%,%,$<)"' > $@ 213 @echo '#include "${BL31_DTSI}"' >> $@ 214 215${BUILD_PLAT}/fdts/%-bl31.dtb: ${BUILD_PLAT}/fdts/%-bl31.dts 216 217include plat/st/common/common_rules.mk 218