| 3a2cc2e2 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
Define CPUECTLR_TIMER_2TICKS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Iecb5ed
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
Define CPUECTLR_TIMER_2TICKS.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Iecb5ede82939e8502d2f1bc74ec3bfe2a00be65c
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| a2047853 | 10-Sep-2021 |
Jiafei Pan <Jiafei.Pan@nxp.com> |
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: J
feat(plat/nxp/common): define default PSCI features if not defined
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced
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