1 /* 2 * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/debug.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/mmio.h> 15 #include <lib/xlat_tables/xlat_tables_v2.h> 16 #include <plat/common/platform.h> 17 18 #include "iic_dvfs.h" 19 #include "micro_delay.h" 20 #include "pwrc.h" 21 #include "rcar_def.h" 22 #include "rcar_private.h" 23 #include "cpg_registers.h" 24 25 /* 26 * Someday there will be a generic power controller api. At the moment each 27 * platform has its own pwrc so just exporting functions should be acceptable. 28 */ 29 RCAR_INSTANTIATE_LOCK 30 31 #define WUP_IRQ_SHIFT (0U) 32 #define WUP_FIQ_SHIFT (8U) 33 #define WUP_CSD_SHIFT (16U) 34 #define BIT_SOFTRESET (1U << 15) 35 #define BIT_CA53_SCU (1U << 21) 36 #define BIT_CA57_SCU (1U << 12) 37 #define REQ_RESUME (1U << 1) 38 #define REQ_OFF (1U << 0) 39 #define STATUS_PWRUP (1U << 4) 40 #define STATUS_PWRDOWN (1U << 0) 41 #define STATE_CA57_CPU (27U) 42 #define STATE_CA53_CPU (22U) 43 #define MODE_L2_DOWN (0x00000002U) 44 #define CPU_PWR_OFF (0x00000003U) 45 #define RCAR_PSTR_MASK (0x00000003U) 46 #define ST_ALL_STANDBY (0x00003333U) 47 /* Suspend to ram */ 48 #define DBSC4_REG_BASE (0xE6790000U) 49 #define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U) 50 #define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U) 51 #define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U) 52 #define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U) 53 #define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U) 54 #define DBSC4_REG_DBCALCNF (DBSC4_REG_BASE + 0x0424U) 55 #define DBSC4_REG_DBDFIPMSTRCNF (DBSC4_REG_BASE + 0x0520U) 56 #define DBSC4_REG_DBPDLK0 (DBSC4_REG_BASE + 0x0620U) 57 #define DBSC4_REG_DBPDRGA0 (DBSC4_REG_BASE + 0x0624U) 58 #define DBSC4_REG_DBPDRGD0 (DBSC4_REG_BASE + 0x0628U) 59 #define DBSC4_REG_DBCAM0CTRL0 (DBSC4_REG_BASE + 0x0940U) 60 #define DBSC4_REG_DBCAM0STAT0 (DBSC4_REG_BASE + 0x0980U) 61 #define DBSC4_REG_DBCAM1STAT0 (DBSC4_REG_BASE + 0x0990U) 62 #define DBSC4_REG_DBCAM2STAT0 (DBSC4_REG_BASE + 0x09A0U) 63 #define DBSC4_REG_DBCAM3STAT0 (DBSC4_REG_BASE + 0x09B0U) 64 #define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0)) 65 #define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0)) 66 #define DBSC4_BIT_DBCAMxSTAT0 (0x00000001U) 67 #define DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN (0x00000001U) 68 #define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U) 69 #define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U) 70 #define DBSC4_SET_DBCMD_OPC_PD (0x08000000U) 71 #define DBSC4_SET_DBCMD_OPC_MRW (0x0E000000U) 72 #define DBSC4_SET_DBCMD_CH_ALL (0x00800000U) 73 #define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U) 74 #define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U) 75 #define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U) 76 #define DBSC4_SET_DBCMD_ARG_MRW_ODTC (0x00000B00U) 77 #define DBSC4_SET_DBSYSCNT0_WRITE_ENABLE (0x00001234U) 78 #define DBSC4_SET_DBSYSCNT0_WRITE_DISABLE (0x00000000U) 79 #define DBSC4_SET_DBPDLK0_PHY_ACCESS (0x0000A55AU) 80 #define DBSC4_SET_DBPDRGA0_ACIOCR0 (0x0000001AU) 81 #define DBSC4_SET_DBPDRGD0_ACIOCR0 (0x33C03C11U) 82 #define DBSC4_SET_DBPDRGA0_DXCCR (0x00000020U) 83 #define DBSC4_SET_DBPDRGD0_DXCCR (0x00181006U) 84 #define DBSC4_SET_DBPDRGA0_PGCR1 (0x00000003U) 85 #define DBSC4_SET_DBPDRGD0_PGCR1 (0x0380C600U) 86 #define DBSC4_SET_DBPDRGA0_ACIOCR1 (0x0000001BU) 87 #define DBSC4_SET_DBPDRGD0_ACIOCR1 (0xAAAAAAAAU) 88 #define DBSC4_SET_DBPDRGA0_ACIOCR3 (0x0000001DU) 89 #define DBSC4_SET_DBPDRGD0_ACIOCR3 (0xAAAAAAAAU) 90 #define DBSC4_SET_DBPDRGA0_ACIOCR5 (0x0000001FU) 91 #define DBSC4_SET_DBPDRGD0_ACIOCR5 (0x000000AAU) 92 #define DBSC4_SET_DBPDRGA0_DX0GCR2 (0x000000A2U) 93 #define DBSC4_SET_DBPDRGD0_DX0GCR2 (0xAAAA0000U) 94 #define DBSC4_SET_DBPDRGA0_DX1GCR2 (0x000000C2U) 95 #define DBSC4_SET_DBPDRGD0_DX1GCR2 (0xAAAA0000U) 96 #define DBSC4_SET_DBPDRGA0_DX2GCR2 (0x000000E2U) 97 #define DBSC4_SET_DBPDRGD0_DX2GCR2 (0xAAAA0000U) 98 #define DBSC4_SET_DBPDRGA0_DX3GCR2 (0x00000102U) 99 #define DBSC4_SET_DBPDRGD0_DX3GCR2 (0xAAAA0000U) 100 #define DBSC4_SET_DBPDRGA0_ZQCR (0x00000090U) 101 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 (0x04058904U) 102 #define DBSC4_SET_DBPDRGD0_ZQCR_MD19_1 (0x04058A04U) 103 #define DBSC4_SET_DBPDRGA0_DX0GCR0 (0x000000A0U) 104 #define DBSC4_SET_DBPDRGD0_DX0GCR0 (0x7C0002E5U) 105 #define DBSC4_SET_DBPDRGA0_DX1GCR0 (0x000000C0U) 106 #define DBSC4_SET_DBPDRGD0_DX1GCR0 (0x7C0002E5U) 107 #define DBSC4_SET_DBPDRGA0_DX2GCR0 (0x000000E0U) 108 #define DBSC4_SET_DBPDRGD0_DX2GCR0 (0x7C0002E5U) 109 #define DBSC4_SET_DBPDRGA0_DX3GCR0 (0x00000100U) 110 #define DBSC4_SET_DBPDRGD0_DX3GCR0 (0x7C0002E5U) 111 #define DBSC4_SET_DBPDRGA0_DX0GCR1 (0x000000A1U) 112 #define DBSC4_SET_DBPDRGD0_DX0GCR1 (0x55550000U) 113 #define DBSC4_SET_DBPDRGA0_DX1GCR1 (0x000000C1U) 114 #define DBSC4_SET_DBPDRGD0_DX1GCR1 (0x55550000U) 115 #define DBSC4_SET_DBPDRGA0_DX2GCR1 (0x000000E1U) 116 #define DBSC4_SET_DBPDRGD0_DX2GCR1 (0x55550000U) 117 #define DBSC4_SET_DBPDRGA0_DX3GCR1 (0x00000101U) 118 #define DBSC4_SET_DBPDRGD0_DX3GCR1 (0x55550000U) 119 #define DBSC4_SET_DBPDRGA0_DX0GCR3 (0x000000A3U) 120 #define DBSC4_SET_DBPDRGD0_DX0GCR3 (0x00008484U) 121 #define DBSC4_SET_DBPDRGA0_DX1GCR3 (0x000000C3U) 122 #define DBSC4_SET_DBPDRGD0_DX1GCR3 (0x00008484U) 123 #define DBSC4_SET_DBPDRGA0_DX2GCR3 (0x000000E3U) 124 #define DBSC4_SET_DBPDRGD0_DX2GCR3 (0x00008484U) 125 #define DBSC4_SET_DBPDRGA0_DX3GCR3 (0x00000103U) 126 #define DBSC4_SET_DBPDRGD0_DX3GCR3 (0x00008484U) 127 #define RST_BASE (0xE6160000U) 128 #define RST_MODEMR (RST_BASE + 0x0060U) 129 #define RST_MODEMR_BIT0 (0x00000001U) 130 131 #define RCAR_CNTCR_OFF (0x00U) 132 #define RCAR_CNTCVL_OFF (0x08U) 133 #define RCAR_CNTCVU_OFF (0x0CU) 134 #define RCAR_CNTFID_OFF (0x20U) 135 136 #define RCAR_CNTCR_EN ((uint32_t)1U << 0U) 137 #define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U) 138 139 #if PMIC_ROHM_BD9571 140 #define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4)) 141 #define PMIC_BKUP_MODE_CNT (0x20U) 142 #define PMIC_QLLM_CNT (0x27U) 143 #define PMIC_RETRY_MAX (100U) 144 #endif /* PMIC_ROHM_BD9571 */ 145 #define SCTLR_EL3_M_BIT ((uint32_t)1U << 0) 146 #define RCAR_CA53CPU_NUM_MAX (4U) 147 #define RCAR_CA57CPU_NUM_MAX (4U) 148 #define IS_A53A57(c) ((c) == RCAR_CLUSTER_A53A57) 149 #define IS_CA57(c) ((c) == RCAR_CLUSTER_CA57) 150 #define IS_CA53(c) ((c) == RCAR_CLUSTER_CA53) 151 152 #ifndef __ASSEMBLER__ 153 IMPORT_SYM(unsigned long, __system_ram_start__, SYSTEM_RAM_START); 154 IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END); 155 IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START); 156 #endif 157 158 uint32_t rcar_pwrc_status(uint64_t mpidr) 159 { 160 uint32_t ret = 0; 161 uint64_t cm, cpu; 162 uint32_t reg; 163 uint32_t c; 164 165 rcar_lock_get(); 166 167 c = rcar_pwrc_get_cluster(); 168 cm = mpidr & MPIDR_CLUSTER_MASK; 169 170 if (!IS_A53A57(c) && cm != 0) { 171 ret = RCAR_INVALID; 172 goto done; 173 } 174 175 reg = mmio_read_32(RCAR_PRR); 176 cpu = mpidr & MPIDR_CPU_MASK; 177 178 if (IS_CA53(c)) 179 if (reg & (1 << (STATE_CA53_CPU + cpu))) 180 ret = RCAR_INVALID; 181 if (IS_CA57(c)) 182 if (reg & (1 << (STATE_CA57_CPU + cpu))) 183 ret = RCAR_INVALID; 184 done: 185 rcar_lock_release(); 186 187 return ret; 188 } 189 190 static void scu_power_up(uint64_t mpidr) 191 { 192 uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer; 193 uint32_t c, sysc_reg_bit; 194 195 c = rcar_pwrc_get_mpidr_cluster(mpidr); 196 reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR; 197 sysc_reg_bit = IS_CA57(c) ? BIT_CA57_SCU : BIT_CA53_SCU; 198 reg_pwron = IS_CA57(c) ? RCAR_PWRONCR5 : RCAR_PWRONCR3; 199 reg_pwrer = IS_CA57(c) ? RCAR_PWRER5 : RCAR_PWRER3; 200 reg_pwrsr = IS_CA57(c) ? RCAR_PWRSR5 : RCAR_PWRSR3; 201 202 if ((mmio_read_32(reg_pwrsr) & STATUS_PWRDOWN) == 0) 203 return; 204 205 if (mmio_read_32(reg_cpumcr) != 0) 206 mmio_write_32(reg_cpumcr, 0); 207 208 mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit); 209 mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit); 210 211 do { 212 while ((mmio_read_32(RCAR_SYSCSR) & REQ_RESUME) == 0) 213 ; 214 mmio_write_32(reg_pwron, 1); 215 } while (mmio_read_32(reg_pwrer) & 1); 216 217 while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0) 218 ; 219 mmio_write_32(RCAR_SYSCISR, sysc_reg_bit); 220 while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0) 221 ; 222 } 223 224 void rcar_pwrc_cpuon(uint64_t mpidr) 225 { 226 uint32_t res_data, on_data; 227 uintptr_t res_reg, on_reg; 228 uint32_t limit, c; 229 uint64_t cpu; 230 231 rcar_lock_get(); 232 233 c = rcar_pwrc_get_mpidr_cluster(mpidr); 234 res_reg = IS_CA53(c) ? RCAR_CA53RESCNT : RCAR_CA57RESCNT; 235 on_reg = IS_CA53(c) ? RCAR_CA53WUPCR : RCAR_CA57WUPCR; 236 limit = IS_CA53(c) ? 0x5A5A0000 : 0xA5A50000; 237 238 res_data = mmio_read_32(res_reg) | limit; 239 scu_power_up(mpidr); 240 cpu = mpidr & MPIDR_CPU_MASK; 241 on_data = 1 << cpu; 242 mmio_write_32(CPG_CPGWPR, ~on_data); 243 mmio_write_32(on_reg, on_data); 244 mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu)))); 245 246 rcar_lock_release(); 247 } 248 249 void rcar_pwrc_cpuoff(uint64_t mpidr) 250 { 251 uint32_t c; 252 uintptr_t reg; 253 uint64_t cpu; 254 255 rcar_lock_get(); 256 257 cpu = mpidr & MPIDR_CPU_MASK; 258 c = rcar_pwrc_get_mpidr_cluster(mpidr); 259 reg = IS_CA53(c) ? RCAR_CA53CPU0CR : RCAR_CA57CPU0CR; 260 261 if (read_mpidr_el1() != mpidr) 262 panic(); 263 264 mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF); 265 mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF); 266 267 rcar_lock_release(); 268 } 269 270 void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr) 271 { 272 uint32_t c, shift_irq, shift_fiq; 273 uintptr_t reg; 274 uint64_t cpu; 275 276 rcar_lock_get(); 277 278 cpu = mpidr & MPIDR_CPU_MASK; 279 c = rcar_pwrc_get_mpidr_cluster(mpidr); 280 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57; 281 282 shift_irq = WUP_IRQ_SHIFT + cpu; 283 shift_fiq = WUP_FIQ_SHIFT + cpu; 284 285 mmio_write_32(reg, ~((uint32_t) 1 << shift_irq) & 286 ~((uint32_t) 1 << shift_fiq)); 287 rcar_lock_release(); 288 } 289 290 void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr) 291 { 292 uint32_t c, shift_irq, shift_fiq; 293 uintptr_t reg; 294 uint64_t cpu; 295 296 rcar_lock_get(); 297 298 cpu = mpidr & MPIDR_CPU_MASK; 299 c = rcar_pwrc_get_mpidr_cluster(mpidr); 300 reg = IS_CA53(c) ? RCAR_WUPMSKCA53 : RCAR_WUPMSKCA57; 301 302 shift_irq = WUP_IRQ_SHIFT + cpu; 303 shift_fiq = WUP_FIQ_SHIFT + cpu; 304 305 mmio_write_32(reg, ((uint32_t) 1 << shift_irq) | 306 ((uint32_t) 1 << shift_fiq)); 307 rcar_lock_release(); 308 } 309 310 void rcar_pwrc_clusteroff(uint64_t mpidr) 311 { 312 uint32_t c, product, cut, reg; 313 uintptr_t dst; 314 315 rcar_lock_get(); 316 317 reg = mmio_read_32(RCAR_PRR); 318 product = reg & PRR_PRODUCT_MASK; 319 cut = reg & PRR_CUT_MASK; 320 321 c = rcar_pwrc_get_mpidr_cluster(mpidr); 322 dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR; 323 324 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) { 325 goto done; 326 } 327 328 if (product == PRR_PRODUCT_H3 && cut <= PRR_PRODUCT_20) { 329 goto done; 330 } 331 332 /* all of the CPUs in the cluster is in the CoreStandby mode */ 333 mmio_write_32(dst, MODE_L2_DOWN); 334 done: 335 rcar_lock_release(); 336 } 337 338 static uint64_t rcar_pwrc_saved_cntpct_el0; 339 static uint32_t rcar_pwrc_saved_cntfid; 340 341 #if RCAR_SYSTEM_SUSPEND 342 static void rcar_pwrc_save_timer_state(void) 343 { 344 rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0(); 345 346 rcar_pwrc_saved_cntfid = 347 mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF)); 348 } 349 #endif /* RCAR_SYSTEM_SUSPEND */ 350 351 void rcar_pwrc_restore_timer_state(void) 352 { 353 /* Stop timer before restoring counter value */ 354 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U); 355 356 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF), 357 (uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU)); 358 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF), 359 (uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U)); 360 361 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF), 362 rcar_pwrc_saved_cntfid); 363 364 /* Start generic timer back */ 365 write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2()); 366 367 mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 368 (RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN)); 369 } 370 371 #if !PMIC_ROHM_BD9571 372 void rcar_pwrc_system_reset(void) 373 { 374 mmio_write_32(RCAR_SRESCR, 0x5AA50000U | BIT_SOFTRESET); 375 } 376 #endif /* PMIC_ROHM_BD9571 */ 377 378 #define RST_CA53_CPU0_BARH (0xE6160080U) 379 #define RST_CA53_CPU0_BARL (0xE6160084U) 380 #define RST_CA57_CPU0_BARH (0xE61600C0U) 381 #define RST_CA57_CPU0_BARL (0xE61600C4U) 382 383 void rcar_pwrc_setup(void) 384 { 385 uintptr_t rst_barh; 386 uintptr_t rst_barl; 387 uint32_t i, j; 388 uint64_t reset = (uint64_t) (&plat_secondary_reset) & 0xFFFFFFFF; 389 390 const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = { 391 RCAR_CLUSTER_CA53, 392 RCAR_CLUSTER_CA57 393 }; 394 const uintptr_t reg_barh[PLATFORM_CLUSTER_COUNT] = { 395 RST_CA53_CPU0_BARH, 396 RST_CA57_CPU0_BARH 397 }; 398 const uintptr_t reg_barl[PLATFORM_CLUSTER_COUNT] = { 399 RST_CA53_CPU0_BARL, 400 RST_CA57_CPU0_BARL 401 }; 402 403 for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) { 404 rst_barh = reg_barh[i]; 405 rst_barl = reg_barl[i]; 406 for (j = 0; j < rcar_pwrc_get_cpu_num(cluster[i]); j++) { 407 mmio_write_32(rst_barh, 0); 408 mmio_write_32(rst_barl, (uint32_t) reset); 409 rst_barh += 0x10; 410 rst_barl += 0x10; 411 } 412 } 413 414 rcar_lock_init(); 415 } 416 417 #if RCAR_SYSTEM_SUSPEND 418 #define DBCAM_FLUSH(__bit) \ 419 do { \ 420 ; \ 421 } while (!(mmio_read_32(DBSC4_REG_DBCAM##__bit##STAT0) & DBSC4_BIT_DBCAMxSTAT0)) 422 423 424 static void __attribute__ ((section(".system_ram"))) 425 rcar_pwrc_set_self_refresh(void) 426 { 427 uint32_t reg = mmio_read_32(RCAR_PRR); 428 uint32_t cut, product; 429 430 product = reg & PRR_PRODUCT_MASK; 431 cut = reg & PRR_CUT_MASK; 432 433 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) { 434 goto self_refresh; 435 } 436 437 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) { 438 goto self_refresh; 439 } 440 441 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE); 442 443 self_refresh: 444 445 /* DFI_PHYMSTR_ACK setting */ 446 mmio_write_32(DBSC4_REG_DBDFIPMSTRCNF, 447 mmio_read_32(DBSC4_REG_DBDFIPMSTRCNF) & 448 (~DBSC4_BIT_DBDFIPMSTRCNF_PMSTREN)); 449 450 /* Set the Self-Refresh mode */ 451 mmio_write_32(DBSC4_REG_DBACEN, 0); 452 453 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) 454 rcar_micro_delay(100); 455 else if (product == PRR_PRODUCT_H3) { 456 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); 457 DBCAM_FLUSH(0); 458 DBCAM_FLUSH(1); 459 DBCAM_FLUSH(2); 460 DBCAM_FLUSH(3); 461 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); 462 } else if (product == PRR_PRODUCT_M3) { 463 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); 464 DBCAM_FLUSH(0); 465 DBCAM_FLUSH(1); 466 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); 467 } else { 468 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); 469 DBCAM_FLUSH(0); 470 mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); 471 } 472 473 /* Set the SDRAM calibration configuration register */ 474 mmio_write_32(DBSC4_REG_DBCALCNF, 0); 475 476 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL | 477 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL; 478 mmio_write_32(DBSC4_REG_DBCMD, reg); 479 while (mmio_read_32(DBSC4_REG_DBWAIT)) 480 ; 481 482 /* Self-Refresh entry command */ 483 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL | 484 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER; 485 mmio_write_32(DBSC4_REG_DBCMD, reg); 486 while (mmio_read_32(DBSC4_REG_DBWAIT)) 487 ; 488 489 /* Mode Register Write command. (ODT disabled) */ 490 reg = DBSC4_SET_DBCMD_OPC_MRW | DBSC4_SET_DBCMD_CH_ALL | 491 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_MRW_ODTC; 492 mmio_write_32(DBSC4_REG_DBCMD, reg); 493 while (mmio_read_32(DBSC4_REG_DBWAIT)) 494 ; 495 496 /* Power Down entry command */ 497 reg = DBSC4_SET_DBCMD_OPC_PD | DBSC4_SET_DBCMD_CH_ALL | 498 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER; 499 mmio_write_32(DBSC4_REG_DBCMD, reg); 500 while (mmio_read_32(DBSC4_REG_DBWAIT)) 501 ; 502 503 /* Set the auto-refresh enable register */ 504 mmio_write_32(DBSC4_REG_DBRFEN, 0U); 505 rcar_micro_delay(1U); 506 507 if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30) 508 return; 509 510 if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20) 511 return; 512 513 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE); 514 } 515 516 static void __attribute__ ((section(".system_ram"))) 517 rcar_pwrc_set_self_refresh_e3(void) 518 { 519 uint32_t ddr_md; 520 uint32_t reg; 521 522 ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & RST_MODEMR_BIT0; 523 524 /* Write enable */ 525 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE); 526 mmio_write_32(DBSC4_REG_DBACEN, 0); 527 DBCAM_FLUSH(0); 528 529 reg = DBSC4_SET_DBCMD_OPC_PRE | DBSC4_SET_DBCMD_CH_ALL | 530 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ALL; 531 mmio_write_32(DBSC4_REG_DBCMD, reg); 532 while (mmio_read_32(DBSC4_REG_DBWAIT)) 533 ; 534 535 reg = DBSC4_SET_DBCMD_OPC_SR | DBSC4_SET_DBCMD_CH_ALL | 536 DBSC4_SET_DBCMD_RANK_ALL | DBSC4_SET_DBCMD_ARG_ENTER; 537 mmio_write_32(DBSC4_REG_DBCMD, reg); 538 while (mmio_read_32(DBSC4_REG_DBWAIT)) 539 ; 540 541 /* 542 * Set the auto-refresh enable register 543 * Set the ARFEN bit to 0 in the DBRFEN 544 */ 545 mmio_write_32(DBSC4_REG_DBRFEN, 0); 546 547 mmio_write_32(DBSC4_REG_DBPDLK0, DBSC4_SET_DBPDLK0_PHY_ACCESS); 548 549 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR0); 550 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR0); 551 552 /* DDR_DXCCR */ 553 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DXCCR); 554 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DXCCR); 555 556 /* DDR_PGCR1 */ 557 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_PGCR1); 558 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_PGCR1); 559 560 /* DDR_ACIOCR1 */ 561 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR1); 562 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR1); 563 564 /* DDR_ACIOCR3 */ 565 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR3); 566 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR3); 567 568 /* DDR_ACIOCR5 */ 569 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ACIOCR5); 570 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_ACIOCR5); 571 572 /* DDR_DX0GCR2 */ 573 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR2); 574 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR2); 575 576 /* DDR_DX1GCR2 */ 577 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR2); 578 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR2); 579 580 /* DDR_DX2GCR2 */ 581 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR2); 582 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR2); 583 584 /* DDR_DX3GCR2 */ 585 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR2); 586 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR2); 587 588 /* DDR_ZQCR */ 589 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_ZQCR); 590 591 mmio_write_32(DBSC4_REG_DBPDRGD0, ddr_md == 0 ? 592 DBSC4_SET_DBPDRGD0_ZQCR_MD19_0 : 593 DBSC4_SET_DBPDRGD0_ZQCR_MD19_1); 594 595 /* DDR_DX0GCR0 */ 596 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR0); 597 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR0); 598 599 /* DDR_DX1GCR0 */ 600 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR0); 601 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR0); 602 603 /* DDR_DX2GCR0 */ 604 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR0); 605 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR0); 606 607 /* DDR_DX3GCR0 */ 608 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR0); 609 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR0); 610 611 /* DDR_DX0GCR1 */ 612 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR1); 613 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR1); 614 615 /* DDR_DX1GCR1 */ 616 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR1); 617 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR1); 618 619 /* DDR_DX2GCR1 */ 620 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR1); 621 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR1); 622 623 /* DDR_DX3GCR1 */ 624 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR1); 625 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR1); 626 627 /* DDR_DX0GCR3 */ 628 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX0GCR3); 629 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX0GCR3); 630 631 /* DDR_DX1GCR3 */ 632 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX1GCR3); 633 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX1GCR3); 634 635 /* DDR_DX2GCR3 */ 636 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX2GCR3); 637 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX2GCR3); 638 639 /* DDR_DX3GCR3 */ 640 mmio_write_32(DBSC4_REG_DBPDRGA0, DBSC4_SET_DBPDRGA0_DX3GCR3); 641 mmio_write_32(DBSC4_REG_DBPDRGD0, DBSC4_SET_DBPDRGD0_DX3GCR3); 642 643 /* Write disable */ 644 mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE); 645 } 646 647 void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline)) 648 rcar_pwrc_go_suspend_to_ram(void) 649 { 650 #if PMIC_ROHM_BD9571 651 int32_t rc = -1, qllm = -1; 652 uint8_t mode; 653 uint32_t i; 654 #endif 655 uint32_t reg, product; 656 657 reg = mmio_read_32(RCAR_PRR); 658 product = reg & PRR_PRODUCT_MASK; 659 660 if (product != PRR_PRODUCT_E3) 661 rcar_pwrc_set_self_refresh(); 662 else 663 rcar_pwrc_set_self_refresh_e3(); 664 665 #if PMIC_ROHM_BD9571 666 /* Set QLLM Cnt Disable */ 667 for (i = 0; (i < PMIC_RETRY_MAX) && (qllm != 0); i++) 668 qllm = rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, 0); 669 670 /* Set trigger of power down to PMIV */ 671 for (i = 0; (i < PMIC_RETRY_MAX) && (rc != 0) && (qllm == 0); i++) { 672 rc = rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode); 673 if (rc == 0) { 674 mode |= BIT_BKUP_CTRL_OUT; 675 rc = rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode); 676 } 677 } 678 #endif 679 wfi(); 680 681 while (1) 682 ; 683 } 684 685 void rcar_pwrc_set_suspend_to_ram(void) 686 { 687 uintptr_t jump = (uintptr_t) &rcar_pwrc_go_suspend_to_ram; 688 uintptr_t stack = (uintptr_t) (DEVICE_SRAM_STACK_BASE + 689 DEVICE_SRAM_STACK_SIZE); 690 uint32_t sctlr; 691 692 rcar_pwrc_save_timer_state(); 693 694 /* disable MMU */ 695 sctlr = (uint32_t) read_sctlr_el3(); 696 sctlr &= (uint32_t) ~SCTLR_EL3_M_BIT; 697 write_sctlr_el3((uint64_t) sctlr); 698 699 rcar_pwrc_switch_stack(jump, stack, NULL); 700 } 701 702 void rcar_pwrc_init_suspend_to_ram(void) 703 { 704 #if PMIC_ROHM_BD9571 705 uint8_t mode; 706 707 if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) 708 panic(); 709 710 mode &= (uint8_t) (~BIT_BKUP_CTRL_OUT); 711 if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) 712 panic(); 713 #endif 714 } 715 716 void rcar_pwrc_suspend_to_ram(void) 717 { 718 #if RCAR_SYSTEM_RESET_KEEPON_DDR 719 int32_t error; 720 721 error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0); 722 if (error) { 723 ERROR("Failed send KEEP10 init ret=%d\n", error); 724 return; 725 } 726 #endif 727 rcar_pwrc_set_suspend_to_ram(); 728 } 729 #endif 730 731 void rcar_pwrc_code_copy_to_system_ram(void) 732 { 733 int ret __attribute__ ((unused)); /* in assert */ 734 uint32_t attr; 735 struct device_sram_t { 736 uintptr_t base; 737 size_t len; 738 } sram = { 739 .base = (uintptr_t) DEVICE_SRAM_BASE, 740 .len = DEVICE_SRAM_SIZE, 741 }; 742 struct ddr_code_t { 743 void *base; 744 size_t len; 745 } code = { 746 .base = (void *) SRAM_COPY_START, 747 .len = SYSTEM_RAM_END - SYSTEM_RAM_START, 748 }; 749 750 attr = MT_MEMORY | MT_RW | MT_SECURE | MT_EXECUTE_NEVER; 751 ret = xlat_change_mem_attributes(sram.base, sram.len, attr); 752 assert(ret == 0); 753 754 memcpy((void *)sram.base, code.base, code.len); 755 flush_dcache_range((uint64_t) sram.base, code.len); 756 757 /* Invalidate instruction cache */ 758 plat_invalidate_icache(); 759 dsb(); 760 isb(); 761 762 attr = MT_MEMORY | MT_RO | MT_SECURE | MT_EXECUTE; 763 ret = xlat_change_mem_attributes(sram.base, sram.len, attr); 764 assert(ret == 0); 765 } 766 767 uint32_t rcar_pwrc_get_cluster(void) 768 { 769 uint32_t reg; 770 771 reg = mmio_read_32(RCAR_PRR); 772 773 if (reg & (1U << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX))) 774 return RCAR_CLUSTER_CA57; 775 776 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX))) 777 return RCAR_CLUSTER_CA53; 778 779 return RCAR_CLUSTER_A53A57; 780 } 781 782 uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr) 783 { 784 uint32_t c = rcar_pwrc_get_cluster(); 785 786 if (IS_A53A57(c)) { 787 if (mpidr & MPIDR_CLUSTER_MASK) 788 return RCAR_CLUSTER_CA53; 789 790 return RCAR_CLUSTER_CA57; 791 } 792 793 return c; 794 } 795 796 #if RCAR_LSI == RCAR_D3 797 uint32_t rcar_pwrc_get_cpu_num(uint32_t c) 798 { 799 return 1; 800 } 801 #else 802 uint32_t rcar_pwrc_get_cpu_num(uint32_t c) 803 { 804 uint32_t reg = mmio_read_32(RCAR_PRR); 805 uint32_t count = 0, i; 806 807 if (IS_A53A57(c) || IS_CA53(c)) { 808 if (reg & (1 << (STATE_CA53_CPU + RCAR_CA53CPU_NUM_MAX))) 809 goto count_ca57; 810 811 for (i = 0; i < RCAR_CA53CPU_NUM_MAX; i++) { 812 if (reg & (1 << (STATE_CA53_CPU + i))) 813 continue; 814 count++; 815 } 816 } 817 818 count_ca57: 819 if (IS_A53A57(c) || IS_CA57(c)) { 820 if (reg & (1U << (STATE_CA57_CPU + RCAR_CA57CPU_NUM_MAX))) 821 goto done; 822 823 for (i = 0; i < RCAR_CA57CPU_NUM_MAX; i++) { 824 if (reg & (1 << (STATE_CA57_CPU + i))) 825 continue; 826 count++; 827 } 828 } 829 830 done: 831 return count; 832 } 833 #endif 834 835 int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr) 836 { 837 uint64_t i; 838 uint64_t j; 839 uint64_t cpu_count; 840 uintptr_t reg_PSTR; 841 uint32_t status; 842 uint64_t my_cpu; 843 int32_t rtn; 844 uint32_t my_cluster_type; 845 const uint32_t cluster_type[PLATFORM_CLUSTER_COUNT] = { 846 RCAR_CLUSTER_CA53, 847 RCAR_CLUSTER_CA57 848 }; 849 const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = { 850 RCAR_CA53PSTR, 851 RCAR_CA57PSTR 852 }; 853 854 my_cluster_type = rcar_pwrc_get_cluster(); 855 856 rtn = 0; 857 my_cpu = mpidr & ((uint64_t)(MPIDR_CPU_MASK)); 858 for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) { 859 cpu_count = rcar_pwrc_get_cpu_num(cluster_type[i]); 860 reg_PSTR = registerPSTR[i]; 861 for (j = 0U; j < cpu_count; j++) { 862 if ((my_cluster_type != cluster_type[i]) || (my_cpu != j)) { 863 status = mmio_read_32(reg_PSTR) >> (j * 4U); 864 if ((status & 0x00000003U) == 0U) { 865 rtn--; 866 } 867 } 868 } 869 } 870 871 return rtn; 872 } 873