1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #if STM32MP_USE_STM32IMAGE 29 #ifdef AARCH32_SP_OPTEE 30 #define OPTEE_HEADER_IMAGE_NAME "teeh" 31 #define OPTEE_CORE_IMAGE_NAME "teex" 32 #define OPTEE_PAGED_IMAGE_NAME "teed" 33 #define OPTEE_HEADER_BINARY_TYPE U(0x20) 34 #define OPTEE_CORE_BINARY_TYPE U(0x21) 35 #define OPTEE_PAGED_BINARY_TYPE U(0x22) 36 #endif 37 38 /* SSBL = second stage boot loader */ 39 #define BL33_IMAGE_NAME "ssbl" 40 #define BL33_BINARY_TYPE U(0x0) 41 #else /* STM32MP_USE_STM32IMAGE */ 42 #define FIP_IMAGE_NAME "fip" 43 #endif /* STM32MP_USE_STM32IMAGE */ 44 45 #define STM32MP_PRIMARY_CPU U(0x0) 46 #define STM32MP_SECONDARY_CPU U(0x1) 47 48 #define PLATFORM_CLUSTER_COUNT U(1) 49 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 50 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 51 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 52 PLATFORM_CLUSTER0_CORE_COUNT) 53 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 54 55 #define MAX_IO_DEVICES U(4) 56 #define MAX_IO_HANDLES U(4) 57 #define MAX_IO_BLOCK_DEVICES U(1) 58 #define MAX_IO_MTD_DEVICES U(1) 59 60 /******************************************************************************* 61 * BL2 specific defines. 62 ******************************************************************************/ 63 /* 64 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 65 * size plus a little space for growth. 66 */ 67 #define BL2_BASE STM32MP_BL2_BASE 68 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 69 STM32MP_BL2_SIZE) 70 71 /******************************************************************************* 72 * BL32 specific defines. 73 ******************************************************************************/ 74 #if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) 75 #if ENABLE_PIE 76 #define BL32_BASE 0 77 #define BL32_LIMIT STM32MP_BL32_SIZE 78 #else 79 #define BL32_BASE STM32MP_BL32_BASE 80 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 81 STM32MP_BL32_SIZE) 82 #endif 83 #endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */ 84 85 /******************************************************************************* 86 * BL33 specific defines. 87 ******************************************************************************/ 88 #define BL33_BASE STM32MP_BL33_BASE 89 90 /* 91 * Load address of BL33 for this platform port 92 */ 93 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 94 95 /* 96 * SSBL offset in case it's stored in eMMC boot partition. 97 * We can fix it to 256K because TF-A size can't be bigger than SRAM 98 */ 99 #define PLAT_EMMC_BOOT_SSBL_OFFSET U(0x40000) 100 101 /******************************************************************************* 102 * DTB specific defines. 103 ******************************************************************************/ 104 #define DTB_BASE STM32MP_DTB_BASE 105 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 106 STM32MP_DTB_SIZE) 107 108 /******************************************************************************* 109 * Platform specific page table and MMU setup constants 110 ******************************************************************************/ 111 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 112 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 113 114 /******************************************************************************* 115 * Declarations and constants to access the mailboxes safely. Each mailbox is 116 * aligned on the biggest cache line size in the platform. This is known only 117 * to the platform as it might have a combination of integrated and external 118 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 119 * line at any cache level. They could belong to different cpus/clusters & 120 * get written while being protected by different locks causing corruption of 121 * a valid mailbox address. 122 ******************************************************************************/ 123 #define CACHE_WRITEBACK_SHIFT 6 124 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 125 126 /* 127 * Secure Interrupt: based on the standard ARM mapping 128 */ 129 #define ARM_IRQ_SEC_PHY_TIMER U(29) 130 131 #define ARM_IRQ_SEC_SGI_0 U(8) 132 #define ARM_IRQ_SEC_SGI_1 U(9) 133 #define ARM_IRQ_SEC_SGI_2 U(10) 134 #define ARM_IRQ_SEC_SGI_3 U(11) 135 #define ARM_IRQ_SEC_SGI_4 U(12) 136 #define ARM_IRQ_SEC_SGI_5 U(13) 137 #define ARM_IRQ_SEC_SGI_6 U(14) 138 #define ARM_IRQ_SEC_SGI_7 U(15) 139 140 #define STM32MP1_IRQ_TZC400 U(36) 141 #define STM32MP1_IRQ_TAMPSERRS U(229) 142 #define STM32MP1_IRQ_AXIERRIRQ U(244) 143 144 /* 145 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 146 * terminology. On a GICv2 system or mode, the lists will be merged and treated 147 * as Group 0 interrupts. 148 */ 149 #define PLATFORM_G1S_PROPS(grp) \ 150 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 151 GIC_HIGHEST_SEC_PRIORITY, \ 152 grp, GIC_INTR_CFG_LEVEL), \ 153 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 154 GIC_HIGHEST_SEC_PRIORITY, \ 155 grp, GIC_INTR_CFG_LEVEL), \ 156 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 157 GIC_HIGHEST_SEC_PRIORITY, \ 158 grp, GIC_INTR_CFG_LEVEL), \ 159 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 160 GIC_HIGHEST_SEC_PRIORITY, \ 161 grp, GIC_INTR_CFG_EDGE), \ 162 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 163 GIC_HIGHEST_SEC_PRIORITY, \ 164 grp, GIC_INTR_CFG_EDGE), \ 165 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 166 GIC_HIGHEST_SEC_PRIORITY, \ 167 grp, GIC_INTR_CFG_EDGE), \ 168 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 169 GIC_HIGHEST_SEC_PRIORITY, \ 170 grp, GIC_INTR_CFG_EDGE), \ 171 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 172 GIC_HIGHEST_SEC_PRIORITY, \ 173 grp, GIC_INTR_CFG_EDGE), \ 174 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 175 GIC_HIGHEST_SEC_PRIORITY, \ 176 grp, GIC_INTR_CFG_EDGE) 177 178 #define PLATFORM_G0_PROPS(grp) \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 180 GIC_HIGHEST_SEC_PRIORITY, \ 181 grp, GIC_INTR_CFG_EDGE), \ 182 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 183 GIC_HIGHEST_SEC_PRIORITY, \ 184 grp, GIC_INTR_CFG_EDGE) 185 186 /* 187 * Power 188 */ 189 #define PLAT_MAX_PWR_LVL U(1) 190 191 /* Local power state for power domains in Run state. */ 192 #define ARM_LOCAL_STATE_RUN U(0) 193 /* Local power state for retention. Valid only for CPU power domains */ 194 #define ARM_LOCAL_STATE_RET U(1) 195 /* Local power state for power-down. Valid for CPU and cluster power domains */ 196 #define ARM_LOCAL_STATE_OFF U(2) 197 /* 198 * This macro defines the deepest retention state possible. 199 * A higher state id will represent an invalid or a power down state. 200 */ 201 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 202 /* 203 * This macro defines the deepest power down states possible. Any state ID 204 * higher than this is invalid. 205 */ 206 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 207 208 /******************************************************************************* 209 * Size of the per-cpu data in bytes that should be reserved in the generic 210 * per-cpu data structure for the FVP port. 211 ******************************************************************************/ 212 #define PLAT_PCPU_DATA_SIZE 2 213 214 /******************************************************************************* 215 * Number of parallel entry slots in SMT SCMI server entry context. For this 216 * platform, SCMI server is reached through SMC only, hence the number of 217 * entry slots. 218 ******************************************************************************/ 219 #define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT 220 221 #endif /* PLATFORM_DEF_H */ 222