1# 2# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7# Include GICv2 driver files 8include drivers/arm/gic/v2/gicv2.mk 9 10JUNO_GIC_SOURCES := ${GICV2_SOURCES} \ 11 plat/common/plat_gicv2.c \ 12 plat/arm/common/arm_gicv2.c 13 14JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ 15 plat/arm/common/arm_cci.c 16 17JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ 18 plat/arm/board/juno/juno_security.c \ 19 plat/arm/board/juno/juno_trng.c \ 20 plat/arm/common/arm_tzc400.c 21 22ifneq (${ENABLE_STACK_PROTECTOR}, 0) 23JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c 24endif 25 26# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the 27# SCP during power management operations and for SCP RAM Firmware transfer. 28CSS_USE_SCMI_SDS_DRIVER := 1 29 30PLAT_INCLUDES := -Iplat/arm/board/juno/include 31 32PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \ 33 plat/arm/board/juno/juno_common.c 34 35# Flag to enable support for AArch32 state on JUNO 36JUNO_AARCH32_EL3_RUNTIME := 0 37$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME)) 38$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME)) 39 40# Flag to enable support for TZMP1 on JUNO 41JUNO_TZMP1 := 0 42$(eval $(call assert_boolean,JUNO_TZMP1)) 43ifeq (${JUNO_TZMP1}, 1) 44$(eval $(call add_define,JUNO_TZMP1)) 45endif 46 47TRNG_SUPPORT := 1 48 49ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 50# Include BL32 in FIP 51NEED_BL32 := yes 52# BL31 is not required 53override BL31_SOURCES = 54 55# The BL32 needs to be built separately invoking the AARCH32 compiler and 56# be specifed via `BL32` build option. 57 ifneq (${ARCH}, aarch32) 58 override BL32_SOURCES = 59 endif 60endif 61 62ifeq (${ARCH},aarch64) 63BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 64 lib/cpus/aarch64/cortex_a57.S \ 65 lib/cpus/aarch64/cortex_a72.S \ 66 plat/arm/board/juno/juno_err.c \ 67 plat/arm/board/juno/juno_bl1_setup.c \ 68 drivers/arm/sp805/sp805.c \ 69 ${JUNO_INTERCONNECT_SOURCES} \ 70 ${JUNO_SECURITY_SOURCES} 71 72BL2_SOURCES += drivers/arm/sp805/sp805.c \ 73 lib/utils/mem_region.c \ 74 plat/arm/board/juno/juno_err.c \ 75 plat/arm/board/juno/juno_bl2_setup.c \ 76 plat/arm/common/arm_nor_psci_mem_protect.c \ 77 ${JUNO_SECURITY_SOURCES} 78 79BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} 80 81BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \ 82 lib/cpus/aarch64/cortex_a53.S \ 83 lib/cpus/aarch64/cortex_a57.S \ 84 lib/cpus/aarch64/cortex_a72.S \ 85 lib/utils/mem_region.c \ 86 plat/arm/board/juno/juno_pm.c \ 87 plat/arm/board/juno/juno_topology.c \ 88 plat/arm/common/arm_nor_psci_mem_protect.c \ 89 ${JUNO_GIC_SOURCES} \ 90 ${JUNO_INTERCONNECT_SOURCES} \ 91 ${JUNO_SECURITY_SOURCES} 92 93ifeq (${CSS_USE_SCMI_SDS_DRIVER},1) 94BL1_SOURCES += drivers/arm/css/sds/sds.c 95endif 96 97ifeq (${TRUSTED_BOARD_BOOT}, 1) 98BL1_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 99BL2_SOURCES += plat/arm/board/juno/juno_trusted_boot.c 100endif 101 102endif 103 104ifneq (${RESET_TO_BL31},0) 105 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \ 106 Please set RESET_TO_BL31 to 0.") 107endif 108 109ifeq ($(USE_ROMLIB),1) 110all : bl1_romlib.bin 111endif 112 113bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin romlib.bin 114 @echo "Building combined BL1 and ROMLIB binary for Juno $@" 115 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT) 116 117# Errata workarounds for Cortex-A53: 118ERRATA_A53_819472 := 1 119ERRATA_A53_824069 := 1 120ERRATA_A53_826319 := 1 121ERRATA_A53_827319 := 1 122ERRATA_A53_835769 := 1 123ERRATA_A53_836870 := 1 124ERRATA_A53_843419 := 1 125ERRATA_A53_855873 := 1 126 127# Errata workarounds for Cortex-A57: 128ERRATA_A57_806969 := 0 129ERRATA_A57_813419 := 1 130ERRATA_A57_813420 := 1 131ERRATA_A57_814670 := 1 132ERRATA_A57_817169 := 1 133ERRATA_A57_826974 := 1 134ERRATA_A57_826977 := 1 135ERRATA_A57_828024 := 1 136ERRATA_A57_829520 := 1 137ERRATA_A57_833471 := 1 138ERRATA_A57_859972 := 0 139 140# Errata workarounds for Cortex-A72: 141ERRATA_A72_859971 := 0 142 143# Enable option to skip L1 data cache flush during the Cortex-A57 cluster 144# power down sequence 145SKIP_A57_L1_FLUSH_PWR_DWN := 1 146 147# Do not enable SVE 148ENABLE_SVE_FOR_NS := 0 149 150# Enable the dynamic translation tables library. 151ifeq (${ARCH},aarch32) 152 ifeq (${RESET_TO_SP_MIN},1) 153 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 154 endif 155else 156 ifeq (${RESET_TO_BL31},1) 157 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 158 endif 159endif 160 161ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 162 ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1) 163 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 164 else 165 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 166 endif 167endif 168 169BL1_CPPFLAGS += -march=armv8-a+crc 170BL2_CPPFLAGS += -march=armv8-a+crc 171BL2U_CPPFLAGS += -march=armv8-a+crc 172BL31_CPPFLAGS += -march=armv8-a+crc 173BL32_CPPFLAGS += -march=armv8-a+crc 174 175# Add the FDT_SOURCES and options for Dynamic Config 176FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \ 177 plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts 178 179FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 180TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 181 182# Add the FW_CONFIG to FIP and specify the same to certtool 183$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) 184# Add the TB_FW_CONFIG to FIP and specify the same to certtool 185$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) 186 187include plat/arm/board/common/board_common.mk 188include plat/arm/common/arm_common.mk 189include plat/arm/soc/common/soc_css.mk 190include plat/arm/css/common/css_common.mk 191