1 /* 2 * Copyright 2018-2022 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <lib/mmio.h> 8 9 #include <dram.h> 10 11 static void lpddr4_mr_write(uint32_t mr_rank, uint32_t mr_addr, uint32_t mr_data) 12 { 13 /* 14 * 1. Poll MRSTAT.mr_wr_busy until it is 0. This checks that there 15 * is no outstanding MR transaction. No 16 * writes should be performed to MRCTRL0 and MRCTRL1 if MRSTAT.mr_wr_busy = 1. 17 */ 18 while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) 19 ; 20 21 /* 22 * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, 23 * MRCTRL0.mr_rank and (for MRWs) 24 * MRCTRL1.mr_data to define the MR transaction. 25 */ 26 mmio_write_32(DDRC_MRCTRL0(0), (mr_rank << 4)); 27 mmio_write_32(DDRC_MRCTRL1(0), (mr_addr << 8) | mr_data); 28 mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); 29 } 30 31 void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, 32 unsigned int fsp_index) 33 34 { 35 uint32_t mr, emr, emr2, emr3; 36 uint32_t mr11, mr12, mr22, mr14; 37 uint32_t val; 38 uint32_t derate_backup[3]; 39 uint32_t (*mr_data)[8]; 40 41 /* 1. program targetd UMCTL2_REGS_FREQ1/2/3,already done, skip it. */ 42 43 /* 2. MR13.FSP-WR=1, MRW to update MR registers */ 44 mr_data = info->mr_table; 45 mr = mr_data[fsp_index][0]; 46 emr = mr_data[fsp_index][1]; 47 emr2 = mr_data[fsp_index][2]; 48 emr3 = mr_data[fsp_index][3]; 49 mr11 = mr_data[fsp_index][4]; 50 mr12 = mr_data[fsp_index][5]; 51 mr22 = mr_data[fsp_index][6]; 52 mr14 = mr_data[fsp_index][7]; 53 54 val = (init_fsp == 1) ? 0x2 << 6 : 0x1 << 6; 55 emr3 = (emr3 & 0x003f) | val | 0x0d00; 56 57 /* 12. set PWRCTL.selfref_en=0 */ 58 mmio_clrbits_32(DDRC_PWRCTL(0), 0xf); 59 60 /* It is more safe to config it here */ 61 mmio_clrbits_32(DDRC_DFIPHYMSTR(0), 0x1); 62 63 lpddr4_mr_write(3, 13, emr3); 64 lpddr4_mr_write(3, 1, mr); 65 lpddr4_mr_write(3, 2, emr); 66 lpddr4_mr_write(3, 3, emr2); 67 lpddr4_mr_write(3, 11, mr11); 68 lpddr4_mr_write(3, 12, mr12); 69 lpddr4_mr_write(3, 14, mr14); 70 lpddr4_mr_write(3, 22, mr22); 71 72 do { 73 val = mmio_read_32(DDRC_MRSTAT(0)); 74 } while (val & 0x1); 75 76 /* 3. disable AXI ports */ 77 mmio_write_32(DDRC_PCTRL_0(0), 0x0); 78 79 /* 4.Poll PSTAT.rd_port_busy_n=0 and PSTAT.wr_port_busy_n=0. */ 80 do { 81 val = mmio_read_32(DDRC_PSTAT(0)); 82 } while (val != 0); 83 84 /* 6.disable SBRCTL.scrub_en, skip if never enable it */ 85 /* 7.poll SBRSTAT.scrub_busy Q2: should skip phy master if never enable it */ 86 /* Disable phy master */ 87 #ifdef DFILP_SPT 88 /* 8. disable DFI LP */ 89 /* DFILPCFG0.dfi_lp_en_sr */ 90 val = mmio_read_32(DDRC_DFILPCFG0(0)); 91 if (val & 0x100) { 92 mmio_write_32(DDRC_DFILPCFG0(0), 0x0); 93 do { 94 val = mmio_read_32(DDRC_DFISTAT(0)); // dfi_lp_ack 95 val2 = mmio_read_32(DDRC_STAT(0)); // operating_mode 96 } while (((val & 0x2) == 0x2) && ((val2 & 0x7) == 3)); 97 } 98 #endif 99 /* 9. wait until in normal or power down states */ 100 do { 101 /* operating_mode */ 102 val = mmio_read_32(DDRC_STAT(0)); 103 } while (((val & 0x7) != 1) && ((val & 0x7) != 2)); 104 105 /* 10. Disable automatic derating: derate_enable */ 106 val = mmio_read_32(DDRC_DERATEEN(0)); 107 derate_backup[0] = val; 108 mmio_clrbits_32(DDRC_DERATEEN(0), 0x1); 109 110 val = mmio_read_32(DDRC_FREQ1_DERATEEN(0)); 111 derate_backup[1] = val; 112 mmio_clrbits_32(DDRC_FREQ1_DERATEEN(0), 0x1); 113 114 val = mmio_read_32(DDRC_FREQ2_DERATEEN(0)); 115 derate_backup[2] = val; 116 mmio_clrbits_32(DDRC_FREQ2_DERATEEN(0), 0x1); 117 118 /* 11. disable automatic ZQ calibration */ 119 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(31)); 120 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); 121 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); 122 123 /* 12. set PWRCTL.selfref_en=0 */ 124 mmio_clrbits_32(DDRC_PWRCTL(0), 0x1); 125 126 /* 13.Poll STAT.operating_mode is in "Normal" (001) or "Power-down" (010) */ 127 do { 128 val = mmio_read_32(DDRC_STAT(0)); 129 } while (((val & 0x7) != 1) && ((val & 0x7) != 2)); 130 131 /* 14-15. trigger SW SR */ 132 /* bit 5: selfref_sw, bit 6: stay_in_selfref */ 133 mmio_setbits_32(DDRC_PWRCTL(0), 0x60); 134 135 /* 16. Poll STAT.selfref_state in "Self Refresh 1" */ 136 do { 137 val = mmio_read_32(DDRC_STAT(0)); 138 } while ((val & 0x300) != 0x100); 139 140 /* 17. disable dq */ 141 mmio_setbits_32(DDRC_DBG1(0), 0x1); 142 143 /* 18. Poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty */ 144 do { 145 val = mmio_read_32(DDRC_DBGCAM(0)); 146 val &= 0x30000000; 147 } while (val != 0x30000000); 148 149 /* 19. change MR13.FSP-OP to new FSP and MR13.VRCG to high current */ 150 emr3 = (((~init_fsp) & 0x1) << 7) | (0x1 << 3) | (emr3 & 0x0077) | 0x0d00; 151 lpddr4_mr_write(3, 13, emr3); 152 153 /* 20. enter SR Power Down */ 154 mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x20); 155 156 /* 21. Poll STAT.selfref_state is in "SR Power down" */ 157 do { 158 val = mmio_read_32(DDRC_STAT(0)); 159 } while ((val & 0x300) != 0x200); 160 161 /* 22. set dfi_init_complete_en = 0 */ 162 163 /* 23. switch clock */ 164 /* set SWCTL.dw_done to 0 */ 165 mmio_write_32(DDRC_SWCTL(0), 0x0000); 166 167 /* 24. program frequency mode=1(bit 29), target_frequency=target_freq (bit 29) */ 168 mmio_write_32(DDRC_MSTR2(0), fsp_index); 169 170 /* 25. DBICTL for FSP-OP[1], skip it if never enable it */ 171 172 /* 26.trigger initialization in the PHY */ 173 174 /* Q3: if refresh level is updated, then should program */ 175 /* as updating refresh, need to toggle refresh_update_level signal */ 176 val = mmio_read_32(DDRC_RFSHCTL3(0)); 177 val = val ^ 0x2; 178 mmio_write_32(DDRC_RFSHCTL3(0), val); 179 180 /* Q4: only for legacy PHY, so here can skipped */ 181 182 /* dfi_frequency -> 0x1x */ 183 val = mmio_read_32(DDRC_DFIMISC(0)); 184 val &= 0xFE; 185 val |= (fsp_index << 8); 186 mmio_write_32(DDRC_DFIMISC(0), val); 187 /* dfi_init_start */ 188 val |= 0x20; 189 mmio_write_32(DDRC_DFIMISC(0), val); 190 191 /* polling dfi_init_complete de-assert */ 192 do { 193 val = mmio_read_32(DDRC_DFISTAT(0)); 194 } while ((val & 0x1) == 0x1); 195 196 /* change the clock frequency */ 197 dram_clock_switch(info->timing_info->fsp_table[fsp_index], info->bypass_mode); 198 199 /* dfi_init_start de-assert */ 200 mmio_clrbits_32(DDRC_DFIMISC(0), 0x20); 201 202 /* polling dfi_init_complete re-assert */ 203 do { 204 val = mmio_read_32(DDRC_DFISTAT(0)); 205 } while ((val & 0x1) == 0x0); 206 207 /* 27. set ZQCTL0.dis_srx_zqcl = 1 */ 208 if (fsp_index == 0) { 209 mmio_setbits_32(DDRC_ZQCTL0(0), BIT(30)); 210 } else if (fsp_index == 1) { 211 mmio_setbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); 212 } else { 213 mmio_setbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); 214 } 215 216 /* 28,29. exit "self refresh power down" to stay "self refresh 2" */ 217 /* exit SR power down */ 218 mmio_clrsetbits_32(DDRC_PWRCTL(0), 0x60, 0x40); 219 /* 30. Poll STAT.selfref_state in "Self refresh 2" */ 220 do { 221 val = mmio_read_32(DDRC_STAT(0)); 222 } while ((val & 0x300) != 0x300); 223 224 /* 31. change MR13.VRCG to normal */ 225 emr3 = (emr3 & 0x00f7) | 0x0d00; 226 lpddr4_mr_write(3, 13, emr3); 227 228 /* enable PHY master */ 229 mmio_write_32(DDRC_DFIPHYMSTR(0), 0x1); 230 231 /* 32. issue ZQ if required: zq_calib_short, bit 4 */ 232 /* polling zq_calib_short_busy */ 233 mmio_setbits_32(DDRC_DBGCMD(0), 0x10); 234 235 do { 236 val = mmio_read_32(DDRC_DBGSTAT(0)); 237 } while ((val & 0x10) != 0x0); 238 239 /* 33. Reset ZQCTL0.dis_srx_zqcl=0 */ 240 if (fsp_index == 1) 241 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(30)); 242 else if (fsp_index == 2) 243 mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(30)); 244 else 245 mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(30)); 246 247 /* set SWCTL.dw_done to 1 and poll SWSTAT.sw_done_ack=1 */ 248 mmio_write_32(DDRC_SWCTL(0), 0x1); 249 250 /* wait SWSTAT.sw_done_ack to 1 */ 251 do { 252 val = mmio_read_32(DDRC_SWSTAT(0)); 253 } while ((val & 0x1) == 0x0); 254 255 /* 34. set PWRCTL.stay_in_selfreh=0, exit SR */ 256 mmio_clrbits_32(DDRC_PWRCTL(0), 0x40); 257 /* wait tXSR */ 258 259 /* 35. Poll STAT.selfref_state in "Idle" */ 260 do { 261 val = mmio_read_32(DDRC_STAT(0)); 262 } while ((val & 0x300) != 0x0); 263 264 #ifdef DFILP_SPT 265 /* 36. restore dfi_lp.dfi_lp_en_sr */ 266 mmio_setbits_32(DDRC_DFILPCFG0(0), BIT(8)); 267 #endif 268 269 /* 37. re-enable CAM: dis_dq */ 270 mmio_clrbits_32(DDRC_DBG1(0), 0x1); 271 272 /* 38. re-enable automatic SR: selfref_en */ 273 mmio_setbits_32(DDRC_PWRCTL(0), 0x1); 274 275 /* 39. re-enable automatic ZQ: dis_auto_zq=0 */ 276 /* disable automatic ZQ calibration */ 277 if (fsp_index == 1) 278 mmio_clrbits_32(DDRC_FREQ1_ZQCTL0(0), BIT(31)); 279 else if (fsp_index == 2) 280 mmio_clrbits_32(DDRC_FREQ2_ZQCTL0(0), BIT(31)); 281 else 282 mmio_clrbits_32(DDRC_ZQCTL0(0), BIT(31)); 283 /* 40. re-emable automatic derating: derate_enable */ 284 mmio_write_32(DDRC_DERATEEN(0), derate_backup[0]); 285 mmio_write_32(DDRC_FREQ1_DERATEEN(0), derate_backup[1]); 286 mmio_write_32(DDRC_FREQ2_DERATEEN(0), derate_backup[2]); 287 288 /* 41. write 1 to PCTRL.port_en */ 289 mmio_write_32(DDRC_PCTRL_0(0), 0x1); 290 291 /* 42. enable SBRCTL.scrub_en, skip if never enable it */ 292 } 293